CN109473442B - Preparation method of semiconductor device channel layer and semiconductor device channel layer - Google Patents
Preparation method of semiconductor device channel layer and semiconductor device channel layer Download PDFInfo
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Abstract
The invention discloses a preparation method of a semiconductor device channel layer and the semiconductor device channel layer. Wherein, the preparation method comprises the following steps: providing a semiconductor device, wherein a channel through hole is formed in the semiconductor device, and a functional layer is formed in the channel through hole; depositing a channel material layer on the functional layer, wherein the channel material layer comprises an ion-doped channel material layer, one side, close to the functional layer, of the channel material layer is provided with a first ion doping concentration, and the first ion doping concentration is greater than or equal to zero; performing a heat treatment process to form the channel material layer into a channel layer at least on one side close to the functional layer, wherein the channel layer has a second ion doping concentration, and the second ion doping concentration is greater than zero; wherein the second ion doping concentration is greater than the first ion doping concentration.
Description
Technical Field
The invention relates to the technical field of semiconductor processes and memory devices, in particular to a preparation method of a semiconductor device channel layer and the semiconductor device channel layer.
Background
The channel layer of the semiconductor device is a key channel for carrier movement; especially for memory devices, the current-conducting capability of the channel layer has a significant impact on its erase and read performance.
At this stage, the channel layer is mainly composed of polysilicon or other silicon-based materials. For the polysilicon channel, a silicon material is deposited mainly by a CVD method, and then the silicon material is recrystallized by high-temperature annealing, so that the carrier conduction performance of the silicon channel is improved.
However, as the structure of semiconductor devices is continuously changed along with the development of the technology, the conventional channel layer structure and the forming process thereof cannot meet the functional requirements of new devices gradually. Therefore, how to prepare a channel layer structure having a higher carrier conduction capability and meeting the functional requirements of the device becomes a technical problem to be solved urgently at the present stage in the field.
Disclosure of Invention
In view of the above, the main objective of the present invention is to provide a method for manufacturing a channel layer of a semiconductor device and a channel layer of a semiconductor device.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the embodiment of the invention provides a preparation method of a semiconductor device channel layer, which comprises the following steps:
providing a semiconductor device, wherein a channel through hole is formed in the semiconductor device, and a functional layer is formed in the channel through hole;
depositing a channel material layer on the functional layer, wherein the channel material layer comprises an ion-doped channel material layer, one side, close to the functional layer, of the channel material layer is provided with a first ion doping concentration, and the first ion doping concentration is greater than or equal to zero;
performing a heat treatment process to form the channel material layer into a channel layer at least on one side close to the functional layer, wherein the channel layer has a second ion doping concentration, and the second ion doping concentration is greater than zero;
wherein the second ion doping concentration is greater than the first ion doping concentration.
In the above scheme, depositing a channel material layer on the functional layer specifically includes: and depositing a channel material layer with a single-layer structure on the functional layer, wherein the channel material layer has a first ion doping concentration which is greater than zero.
In the above scheme, the first ion doping concentration is less than or equal to 20%.
In the scheme, the thickness of the channel material layer is 10-40 nm.
In the foregoing scheme, the channel material layer is a stack layer, and depositing the channel material layer on the functional layer specifically includes:
depositing a first channel material layer with a first ion doping concentration on the functional layer, wherein the first ion doping concentration is greater than or equal to zero;
depositing a second channel material layer having a third ion doping concentration on the first channel material layer, the third ion doping concentration being greater than the first ion doping concentration.
In the above scheme, when the first ion doping concentration is equal to zero, the first channel material layer includes a silicon layer.
In the above scheme, the thickness of the first channel material layer is 5-20 nm.
In the above scheme, the functional layer includes a blocking layer, a storage layer and a tunneling layer sequentially arranged along a radially inward direction of the channel via.
In the above scheme, the ion-doped channel material layer includes a silicon germanium layer.
In the above scheme, the channel material layer is deposited by a chemical vapor deposition method, and the gas source used in the chemical vapor deposition process includes germane and silane.
In the above scheme, the reaction temperature of the heat treatment process is 300-800 ℃.
In the scheme, the reaction time of the heat treatment process is 3-60 minutes.
In the above scheme, the heat treatment process is performed in an oxygen-containing environment.
In the above embodiment, the oxygen-containing environment includes oxygen or water vapor.
In the above scheme, the thickness of the channel layer is 3-20 nm.
In the above scheme, in the performing of the thermal treatment process, the other side of the channel material layer is oxidized to form an oxide layer;
the method further comprises the following steps: removing the oxide layer to expose the channel layer; depositing a channel protection layer on the channel layer.
In the above scheme, in the performing of the thermal treatment process, the other side of the channel material layer is oxidized to form an oxide layer;
the method further comprises the following steps: and reserving the oxidation layer, and depositing a channel protection layer on the oxidation layer.
In the above scheme, the method further comprises: annealing the channel layer after performing a heat treatment process or after depositing a channel protection layer.
In the above scheme, the semiconductor device is a three-dimensional memory.
Embodiments of the present invention further provide a channel layer of a semiconductor device, where the channel layer is formed in a channel via of the semiconductor device, doped ions are provided in the channel layer, and ion doping concentration is gradually reduced along a radially inward direction of the channel via.
In the above scheme, the ion doping concentration of the channel layer is greater than 20%.
In the above aspect, the channel layer includes a germanium-silicon layer.
In the above scheme, the thickness of the channel layer is 3-20 nm.
In the above scheme, the semiconductor device further includes a functional layer in the channel via, where the functional layer includes a blocking layer, a storage layer, and a tunneling layer sequentially arranged in a radially inward direction of the channel via; and one side with the highest ion doping concentration in the channel layer is contacted with the tunneling layer.
In the above scheme, the side of the channel layer with the lowest ion doping concentration is in contact with the channel protection layer.
In the above scheme, the semiconductor device is a three-dimensional memory.
According to the preparation method of the semiconductor device channel layer and the semiconductor device channel layer, provided by the embodiment of the invention, the semiconductor device is provided, the channel through hole is formed in the semiconductor device, and the functional layer is formed in the channel through hole; depositing a channel material layer on the functional layer, wherein the channel material layer comprises an ion-doped channel material layer, one side, close to the functional layer, of the channel material layer is provided with a first ion doping concentration, and the first ion doping concentration is greater than or equal to zero; performing a heat treatment process to form the channel material layer into a channel layer at least on one side close to the functional layer, wherein the channel layer has a second ion doping concentration, and the second ion doping concentration is greater than zero; wherein the second ion doping concentration is greater than the first ion doping concentration; thereby forming a channel layer of a semiconductor device, wherein the channel layer is formed in a channel through hole of the semiconductor device, doped ions are arranged in the channel layer, and the ion doping concentration is gradually reduced along the radial direction inward of the channel through hole. Thus, by depositing a channel material layer on the functional layer and adopting a heat treatment process, the doped ions are enriched towards the functional layer, so that a semiconductor device channel layer with higher doping concentration is obtained; moreover, because the required high doping concentration can be realized through the enrichment effect of the heat treatment process, the channel material layer with high concentration does not need to be directly deposited when the channel material layer is deposited, the influence of the doping concentration on the grain size and the process stability in the deposition process is avoided, the channel material layer with relatively low concentration or even no doping is deposited, the requirement of the field on the grain size in the channel layer is ensured, the ion doping concentration is gradually increased in the heat treatment process, and the channel layer with high doping concentration is finally obtained, so that the channel carrier concentration is increased, the channel resistance is reduced, and the working performance of a semiconductor device is improved.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a channel layer of a semiconductor device according to an embodiment of the present invention;
fig. 2 to 4 and fig. 6 are schematic cross-sectional views of device structures in the process of manufacturing a channel layer of a semiconductor device according to an embodiment of the present invention;
fig. 5a to 5c are modified examples of a method for manufacturing a channel layer of a semiconductor device according to an embodiment of the present invention.
Description of reference numerals:
10-a semiconductor substrate;
11-a laminated structure; 111-a first material layer; 112-a second material layer; 113-a sacrificial layer;
12-a functional layer; 121-a barrier layer; 122-a storage layer; 123-tunneling layer;
13-a channel material layer; 131. 131' -a first channel material layer; 132. 132' -a first channel material layer;
14-a channel layer;
15-an oxide layer;
16-channel protection layer.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In the related art, there is a higher demand for the turn-on capability of the channel layer of the semiconductor device; for example, for a three-dimensional memory device, as the number of device stacks increases, the channel length also increases, and the channel layer resistance needs to be further reduced to meet the functional requirements of the device. In this case, it is increasingly difficult to satisfy the actual demand by improvement of the lattice structure alone. Therefore, doping impurity ions to improve carrier density and further improve channel conduction capability becomes a hot point for developing next-generation memories. However, as the depth-to-width ratio of the channel through hole of the three-dimensional memory device is larger and larger, the conventional ion implantation method and the CVD impurity ion doping method cannot meet the requirement of the channel on the uniformity of the germanium concentration, and the doping concentration and the grain size control cannot meet the requirement of process control; the selective epitaxial growth commonly used in two-dimensional devices is not suitable for three-dimensional structure devices. Accordingly, the present invention is directed to a method for manufacturing a channel layer of a semiconductor device and a channel layer structure of a semiconductor device, so as to increase the carrier concentration of a channel, reduce the resistance of the channel, and improve the working performance of the semiconductor device.
Fig. 1 is a schematic flow chart of a method for manufacturing a channel layer of a semiconductor device according to an embodiment of the present invention; the method comprises the following steps:
103, performing a heat treatment process to form the channel material layer into a channel layer at least on one side close to the functional layer, wherein the channel layer has a second ion doping concentration, and the second ion doping concentration is greater than zero;
wherein the second ion doping concentration is greater than the first ion doping concentration.
The present invention will be described in further detail with reference to specific examples.
Example 1
First, please refer to fig. 2. As shown, in step 101, a semiconductor device is provided, the semiconductor device comprising a semiconductor substrate 10; the semiconductor substrate 10 may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
A stacked structure 11 in which first material layers 111 and second material layers 112 are alternately stacked is formed on the semiconductor substrate 10. Here, the first material layer 111 may be a dielectric layer, which includes, but is not limited to, silicon oxide, silicon nitride layer, silicon oxynitride, and other high dielectric constant (high-k) dielectric layers; the second material layer 112 may be a sacrificial layer, and may be formed of, for example, one of an oxide layer, a nitride layer, a silicon carbide layer, a silicon layer, and a silicon germanium layer. In this embodiment, the first material layer 111 may be made of SiO2The second material layer 112 may be formed of SiN, so that the stack structure 11 formed is an NO stack. The first material layer and the second material layer may be formed using a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or an Atomic Layer Deposition (ALD) process; the first material layer and the second material layer may have the same thickness as each other, or may have different thicknesses from each other. In one embodiment, the first material layer 111 at the lowest layer in the stacked structure 11 may be formed by oxidation; the bottom penultimate first material layer 111 in the stacked structure 11 may be formed by deposition and is thicker than the first material layers of the other layers in the stacked structure 11; each second material layer 112 may have substantially the same thickness. In another embodiment, the stacked structure 11 may further include a sacrificial layer 113, wherein the sacrificial layer 113 is located at a top region of the stacked structure 11. The sacrificial layer 113 is used for protecting the first material layer and the second material layer from being damaged when the stacked structure 11 is subjected to etching treatment in the following; the material of the consumption layer 113 may include SiNO or SiO2。
In an embodiment of the present invention, the method further includes: and etching the laminated structure 11 to form a channel through hole CH, wherein the channel through hole CH exposes the semiconductor substrate 10. The trench via CH may be formed through a dry etching process. Optionally, an epitaxial layer (SEG) is formed on the semiconductor substrate 10 at the bottom of the trench via CH. The epitaxial layer may be formed by selectively epitaxially growing single crystal silicon, and may serve as a lower selection pipe channel.
With continued reference to fig. 2, a functional layer 12 of the semiconductor device is also included within the trench via CH of the semiconductor device. In an embodiment, the functional layer 12 may include a blocking layer, a storage layer, and a tunneling layer structure sequentially disposed along a radially inward direction of the trench via CH; the layers can be made of single materials or composite layers; in particular, the functional layer 12 may be an ONO stack, an AONO stack, an ONOP stack or other suitable gate stack structure. In this embodiment, the process of forming the functional layer 12 may specifically include: depositing a high-k dielectric layer (e.g., Al) in the trench via CH2O3Layer), the high-k dielectric layer may have a relatively thin thickness; depositing an oxide layer (e.g., SiO) on the high-k dielectric layer2A layer); the high-k dielectric layer and the oxide layer jointly form a barrier layer 121, and the barrier layer 121 is a composite charge barrier layer; continuing to deposit a storage layer 122 over the oxide layer, the storage layer 122 being, for example, a charge trapping layer, which may be a nitride (e.g., SiN layer); depositing a tunneling layer 123 on the storage layer 122, wherein the material of the tunneling layer 123 may be an oxide (e.g., SiO)2A layer); the blocking layer 121, the memory layer 122, and the tunneling layer 123 collectively function to control the charge storage function of the memory device, and therefore, the functional layer 12 may also be referred to as a memory layer of the semiconductor device. The functional layer 12 may be deposited using a CVD or ALD process.
In one embodiment, after the formation of the functional layer 12, a step of etching the bottom of the functional layer 12 to expose the epitaxial layer SEG may be included.
Next, please refer to fig. 3. In step 102, a channel material layer 13 is deposited on the functional layer 12, where the channel material layer 13 includes an ion-doped channel material layer, and a side of the channel material layer 13 close to the functional layer 12 has a first ion doping concentration, and the first ion doping concentration is greater than or equal to zero.
In one embodiment, the ion-doped channel material layer 13 includes a germanium-silicon layer, i.e., the doping ions are germanium (Ge) ions. After the Ge ions form a Ge-doped channel layer in the subsequent process, the carrier concentration of the channel layer can be increased; when the semiconductor device is a memory device, the programming and erasing performance of the memory device can be improved.
In one embodiment, the first ion doping concentration is lower and is less than or equal to 20%. When the doping ions are Ge ions, the concentration of the Ge ions in the channel material layer 13 is 20% or less. It is to be appreciated that in this step 102, the deposited channel material layer is entirely a low concentration ion doped material layer.
In one embodiment, the channel material layer 13 is CVD deposited by a chemical vapor deposition process, wherein a gas source used in the chemical vapor deposition process includes germane and silane; therefore, the germanium content in the channel material layer formed by deposition can be adjusted by adjusting the germane content ratio. In another embodiment, the thickness of the channel material layer 13 may be 10-40 nm.
Next, please refer to fig. 4. In step 103, performing a heat treatment process to form the channel material layer 13 into a channel layer 14 at least on a side close to the functional layer 12, wherein the channel layer 14 has a second ion doping concentration, and the second ion doping concentration is greater than zero; wherein the second ion doping concentration is greater than the first ion doping concentration.
Further, the ion doping concentration of the channel layer 14 is formed to gradually decrease in a direction radially inward of the channel via CH. The side of the channel layer 14 with the highest ion doping concentration is in contact with the tunneling layer 123 of the functional layer 12.
In one embodiment, the reaction temperature of the heat treatment process is 300-800 ℃. Preferably, the reaction temperature is 500-600 ℃. It can be understood that controlling the reaction temperature is helpful to control the conversion rate of the channel material layer, and it is found through research that in the heat treatment process, the reaction temperature of 300-; furthermore, the reaction temperature is 500-600 ℃, the doping concentration of the formed channel layer is most suitable, and the ion doping uniformity is best. Further, the reaction time of the heat treatment process is 3 to 60 minutes.
In one embodiment, the heat treatment process is performed in an oxygen-containing environment. It can be understood that, because the surface of the channel material layer with low doping concentration (first ion doping concentration) is slowly oxidized in the heat treatment process, the oxidation speed of the channel material is high, and the doping ions are enriched towards the functional layer and redistributed in the channel layer, so that the semiconductor device channel layer with high doping concentration and good uniformity is obtained. Further, the oxygen-containing environment comprises oxygen or water vapor; in the embodiment of the invention, oxygen or water vapor is used as carrier gas (carrier gas) in the heat treatment reaction process, so that the reaction temperature distribution is more uniform; in addition, the oxide protective layer can be formed on the surface of the channel material layer.
Next, please refer to fig. 6. In an embodiment of the present invention, the method may further include: after forming the channel layer 14, a channel protection layer 16 is deposited on the channel layer 14.
Specifically, in performing the heat treatment process, the other side of the channel material layer is oxidized to form an oxide layer 15. In an embodiment, the method further comprises: removing the oxide layer 15 to expose the channel layer 14; a channel protection layer 16 is deposited on the channel layer 14. Specifically, the oxide layer 15 may be removed using a wet etching process. In another embodiment, the method further comprises: the oxide layer 15 is retained and a channel protection layer 16 is deposited on the oxide layer 15. Here, the channel protection layer 16 functions as a protection structure of the channel layer together with the oxide layer 15 (not distinguished in the drawing, that is, the oxide layer 15 formed by oxidation is not shown).
Wherein the channel protection layer 16 may be composed of a silicon-based compound; for example SiO2And (3) a layer. The channel protection layer 16 may be deposited using a CVD or ALD method. The channel protection layer 16 remains in the finally fabricated semiconductor device and serves to protect the channel layer 14 from damage; the channel protection layer 16 may or may not fill the channel via CH.
At this time, the side of the channel layer 14 where the ion doping concentration is the lowest is in contact with the channel protection layer 16.
Next, please continue to refer to fig. 6. In an embodiment of the present invention, the method further includes: the channel layer 14 is annealed after a heat treatment process is performed or after the channel protection layer 16 is deposited. It can be understood that, through the annealing process, the dopant ions can be better fixed in the channel layer, and the uniformity of the dopant ions in the channel layer is further improved, so that the carrier concentration of the channel layer is improved, and the channel resistance is reduced. The selection of annealing after the channel protective layer is deposited can eliminate the interface state between the protective layer and the channel layer, and further improve the working performance of the device. It should be noted that the annealing process may be a diffusion annealing process performed exclusively or a high temperature process performed for other subsequent processes.
Further, the semiconductor device in the embodiment of the present invention may be a three-dimensional memory; specifically, the three-dimensional NAND memory can be used.
Example 2
This embodiment is a variation of the method for manufacturing a channel layer of a semiconductor device in embodiment 1, and is a detailed selection of a channel material layer deposited in the manufacturing method described in embodiment 1, and other method steps and related structures are described in embodiment 1, and are not described again here.
Please refer to fig. 5 a. In this embodiment, the channel material layer 13 is a single layer, and the channel material layer 13 is deposited on the functional layer 12, specifically: and depositing a channel material layer 13 with a single-layer structure on the functional layer 12, wherein the channel material layer 13 has a first ion doping concentration which is greater than zero.
Further, the first ion doping concentration is preferably 20% or less. The thickness of the channel material layer 13 is preferably 10-40 nm. The thickness of the channel layer 14 finally formed is preferably 3 to 20 nm.
It can be understood that, in the present embodiment, a single-layer channel material layer is deposited, the whole channel material layer has a first ion doping concentration, and when a subsequent thermal treatment process is performed, one side of the single-layer channel material layer, which is far away from the functional layer, is gradually oxidized to form an oxide layer; the dopant ions on this side are concentrated toward the functional layer (i.e., on the side of the channel material layer closer to the functional layer), and finally form a channel layer at least on the side closer to the functional layer.
Example 3
This embodiment is a further variation of the method for manufacturing a channel layer of a semiconductor device in embodiment 1, and is a detailed selection of a channel material layer deposited in the manufacturing method described in embodiment 1, and other method steps and related structures are described in embodiment 1, and are not described herein again.
Please refer to fig. 5 b. In this embodiment, the channel material layer 13 is a laminated layer, and depositing the channel material layer 13 on the functional layer 12 specifically includes: depositing a first channel material layer 131 having a first ion doping concentration greater than zero on the functional layer 12; a second channel material layer 132 having a third ion doping concentration greater than the first ion doping concentration is deposited on the first channel material layer 131. The thickness of the first channel material layer 131 is preferably 5-20 nm.
It is to be understood that the deposition of the channel material layer in this embodiment is achieved by depositing at least two material layers. Firstly, depositing a first channel material layer with lower doping concentration (first ion doping concentration); then, depositing a second channel material layer having a higher doping concentration (third ion doping concentration) on the first channel material layer; when the subsequent heat treatment process is carried out, the side, far away from the functional layer, of the channel material layer is gradually oxidized to form an oxide layer, in the process, the doping ions in the second channel material layer with higher doping concentration are enriched towards the functional layer (namely, in the first channel material layer with lower doping concentration), and finally, a channel layer is formed on the side, near the functional layer.
In addition, it should be noted that the present embodiment only exemplifies the case where the channel material layer includes a two-layer structure deposited in sequence, and those skilled in the art should understand that the channel material layer includes a multi-layer structure deposited in sequence, and the channel material layer deposited later has a higher ion doping concentration than the channel material layer deposited earlier (especially, the channel material layer on the side close to the functional layer), and also falls within the protection scope of the present invention. For example, the channel material layer includes a multi-layered structure sequentially deposited on the functional layer, and the ion doping concentration of the multi-layered structure is gradually increased according to the deposition order.
Example 4
This embodiment is a further variation of the method for manufacturing a channel layer of a semiconductor device in embodiment 1, and is a detailed selection of a channel material layer deposited in the manufacturing method described in embodiment 1, and other method steps and related structures are described in embodiment 1, and are not described herein again.
Please refer to fig. 5 c. In this embodiment, the channel material layer 13 is also a stacked layer, and depositing the channel material layer 13 on the functional layer 12 specifically includes: depositing a first channel material layer 131' having a first ion doping concentration equal to zero on said functional layer 12; a second channel material layer 132 'having a third ion doping concentration greater than zero is deposited on the first channel material layer 131'.
Further, the first channel material layer 131' includes a silicon layer. The thickness of the first channel material layer 131' is preferably 5-20 nm.
It is to be understood that the deposition of the channel material layer in this embodiment is achieved by depositing at least two material layers. First, depositing a layer of undoped first channel material (e.g., silicon layer); then, depositing an ion-doped second channel material layer on the undoped first channel material layer; the ion-doped second channel material layer herein may have a higher doping concentration. During the subsequent heat treatment process, the side of the channel material layer far away from the functional layer is gradually oxidized to form an oxide layer, and in the process, the doping ions in the ion-doped second channel material layer are enriched towards the functional layer (i.e. in the undoped first channel material layer), and finally a channel layer is formed on the side close to the functional layer.
In addition, it should be noted that, in this embodiment, only the case where the channel material layer includes a two-layer structure of an undoped material layer and a doped material layer deposited in sequence is illustrated, and it should be understood by those skilled in the art that the channel material layer includes a multi-layer structure deposited in sequence, and the first layer is an undoped material layer (with a doping concentration equal to zero), and the subsequently deposited channel material layer includes a doped material layer (with a doping concentration greater than zero), which also fall within the protection scope of the present invention.
Based on the method, the embodiment of the invention also provides a semiconductor device channel layer. The channel layer 14 is formed in a channel via CH of the semiconductor device, the channel layer 14 having dopant ions therein and having a concentration of ion doping gradually decreasing in a radially inward direction of the channel via CH.
In one embodiment, the ion doping concentration of the channel layer 14 is greater than 20%.
In one embodiment, the channel layer 14 includes a germanium-silicon layer.
In one embodiment, the thickness of the channel layer 14 is 3-20 nm.
In an embodiment, the semiconductor device further includes a functional layer 12 in the trench via CH, where the functional layer 12 includes a blocking layer 121, a storage layer 122, and a tunneling layer 123 sequentially arranged along a radially inward direction of the trench via CH; the side of the channel layer 14 with the highest ion doping concentration is in contact with the tunneling layer 123.
In one embodiment, the side of the channel layer 14 where the ion doping concentration is the lowest is in contact with the channel protection layer 16.
In one embodiment, the semiconductor device is a three-dimensional memory.
It should be noted that the embodiments of the methods for manufacturing the channel layer of the semiconductor device and the channel layer of the semiconductor device provided in the embodiments of the present invention belong to the same concept, and specific implementation processes and other detailed structures thereof are described in detail in the embodiments of the methods and will not be described herein again. It should be noted that the technical features described in the embodiments of the present invention may be arbitrarily combined without conflict between the technical features.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.
Claims (25)
1. A method for preparing a channel layer of a semiconductor device, the method comprising the steps of:
providing a semiconductor device, wherein a channel through hole is formed in the semiconductor device, and a functional layer is formed in the channel through hole;
depositing a channel material layer on the functional layer, wherein the channel material layer comprises an ion-doped channel material layer, one side, close to the functional layer, of the channel material layer is provided with a first ion doping concentration, and the first ion doping concentration is greater than or equal to zero;
performing a heat treatment process in an oxygen-containing environment to oxidize a side of the channel material layer far away from the functional layer to form an oxide layer, wherein the channel material layer is formed into a channel layer at least at a side close to the functional layer, and the channel layer has a second ion doping concentration which is greater than zero;
wherein the second ion doping concentration is greater than the first ion doping concentration.
2. Method according to claim 1, characterized in that a layer of channel material is deposited on the functional layer, in particular: and depositing a channel material layer with a single-layer structure on the functional layer, wherein the channel material layer has a first ion doping concentration which is greater than zero.
3. The method of claim 2, wherein the first ion doping concentration is 20% or less.
4. The method of claim 2, wherein the channel material layer has a thickness of 10-40 nm.
5. The method according to claim 1, wherein the channel material layer is a laminate and the depositing of the channel material layer on the functional layer specifically comprises:
depositing a first channel material layer with a first ion doping concentration on the functional layer, wherein the first ion doping concentration is greater than or equal to zero;
depositing a second channel material layer having a third ion doping concentration on the first channel material layer, the third ion doping concentration being greater than the first ion doping concentration.
6. The method of claim 5, wherein the first channel material layer comprises a silicon layer when the first ion doping concentration is equal to zero.
7. The method of claim 5, wherein the first channel material layer has a thickness of 5-20 nm.
8. The method of claim 1, wherein the functional layer comprises a blocking layer, a storage layer, and a tunneling layer sequentially disposed in a radially inward direction of the trench via.
9. The method of any of claims 1-8, wherein the ion-doped channel material layer comprises a silicon germanium layer.
10. The method of any of claims 1-8, wherein the layer of channel material is deposited by a chemical vapor deposition process using a gas source comprising germane and silane.
11. The method as claimed in any one of claims 1 to 8, wherein the reaction temperature of the heat treatment process is 300 ℃ and 800 ℃.
12. The method of claim 11, wherein the reaction time of the heat treatment process is 3-60 minutes.
13. The method of claim 1, wherein the oxygen-containing environment comprises oxygen or water vapor.
14. The method of any of claims 1-8, wherein the channel layer has a thickness of 3-20 nm.
15. The method of claim 1,
the method further comprises the following steps: removing the oxide layer to expose the channel layer; depositing a channel protection layer on the channel layer.
16. The method of claim 1,
the method further comprises the following steps: and reserving the oxidation layer, and depositing a channel protection layer on the oxidation layer.
17. The method of any one of claims 1, 15 or 16, further comprising: annealing the channel layer after performing a heat treatment process or after depositing a channel protection layer.
18. The method of claim 1, wherein the semiconductor device is a three-dimensional memory.
19. A channel layer of a semiconductor device, wherein the channel layer is formed within a channel via of the semiconductor device, the channel layer having dopant ions therein and the ion doping concentration gradually decreasing in a radially inward direction of the channel via.
20. The semiconductor device channel layer of claim 19 wherein the channel layer has an ion doping concentration greater than 20%.
21. The semiconductor device channel layer of claim 19 wherein the channel layer comprises a germanium-silicon layer.
22. The semiconductor device channel layer of claim 19 wherein the channel layer has a thickness of 3-20 nm.
23. The semiconductor device channel layer of claim 19 further comprising a functional layer within the channel via of the semiconductor device, the functional layer comprising a barrier layer, a storage layer, and a tunneling layer disposed sequentially in a radially inward direction of the channel via; and one side with the highest ion doping concentration in the channel layer is contacted with the tunneling layer.
24. The semiconductor device channel layer of claim 19 wherein the side of the channel layer having the lowest concentration of ion doping is in contact with the channel protection layer.
25. The semiconductor device channel layer of claim 19 wherein the semiconductor device is a three-dimensional memory.
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