CN109473440B - Preparation method of semiconductor device channel layer and semiconductor device - Google Patents
Preparation method of semiconductor device channel layer and semiconductor device Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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Abstract
The invention discloses a preparation method of a semiconductor device channel layer and the semiconductor device channel layer. Wherein, the preparation method comprises the following steps: providing a semiconductor device, wherein a channel through hole is formed in the semiconductor device, and a functional layer is formed in the channel through hole; depositing a channel layer on the functional layer, wherein the channel layer is a first semiconductor material layer; depositing a doping layer on the channel layer, wherein the doping layer is a second semiconductor material layer doped with impurities; performing a thermal oxidation process to form a second semiconductor material oxide layer on one side of the second semiconductor material layer far away from the functional layer; wherein the impurity is selected from materials having a higher solid solubility in the first layer of semiconductor material than in the second layer of oxide of semiconductor material.
Description
Technical Field
The invention relates to the technical field of semiconductor processes and memory devices, in particular to a preparation method of a semiconductor device channel layer and the semiconductor device channel layer.
Background
The channel layer of the semiconductor device is a key channel for carrier movement; especially for memory devices, the current-conducting capability of the channel layer has a significant impact on its erase and read performance.
At this stage, the channel layer is mainly composed of polysilicon or other silicon-based materials. For the polysilicon channel, a silicon material is deposited mainly by a CVD method, and then the silicon material is recrystallized by high-temperature annealing, so that the carrier conduction performance of the silicon channel is improved.
However, as the structure of semiconductor devices is continuously changed along with the development of the technology, the conventional channel layer structure and the forming process thereof cannot meet the functional requirements of new devices gradually. Therefore, how to prepare a channel layer structure having a higher carrier conduction capability and meeting the functional requirements of the device becomes a technical problem to be solved urgently at the present stage in the field.
Disclosure of Invention
In view of the above, the main objective of the present invention is to provide a method for manufacturing a channel layer of a semiconductor device and a channel layer of a semiconductor device.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the embodiment of the invention provides a preparation method of a semiconductor device channel layer, which comprises the following steps:
providing a semiconductor device, wherein a channel through hole is formed in the semiconductor device, and a functional layer is formed in the channel through hole;
depositing a channel layer on the functional layer, wherein the channel layer is a first semiconductor material layer;
depositing a doping layer on the channel layer, wherein the doping layer is a second semiconductor material layer doped with impurities;
performing a thermal oxidation process to form a second semiconductor material oxide layer on one side of the second semiconductor material layer far away from the functional layer;
wherein the impurity is selected from materials having a higher solid solubility in the first layer of semiconductor material than in the second layer of oxide of semiconductor material.
In the above scheme, the first semiconductor material layer and the second semiconductor material layer are both silicon-based material layers.
In the above scheme, the first semiconductor material layer is a polysilicon layer.
In the above scheme, the second semiconductor material layer is an amorphous silicon layer.
In the above scheme, the impurities are N-type impurity ions or rare earth elements.
In the above scheme, the second semiconductor material layer having impurity doping is deposited by a CVD or ALD process.
In the above scheme, the impurity gas source used in the deposition process includes phosphane or arsane.
In the above scheme, the oxidation temperature of the thermal oxidation process is 300-800 ℃.
In the scheme, the oxidation time of the thermal oxidation process is 3-60 minutes.
In the above scheme, the reaction gas of the thermal oxidation process includes oxygen or water vapor.
In the above scheme, the functional layer includes a blocking layer, a storage layer and a tunneling layer sequentially arranged along a radially inward direction of the channel via.
In the above scheme, the method further comprises: and after the thermal oxidation process is carried out, removing the second semiconductor material oxide layer and depositing a channel protection layer.
In the above scheme, the method further comprises: and after the thermal oxidation process is carried out, the second semiconductor material oxide layer is reserved, and a channel protection layer is deposited.
In the above scheme, the method further comprises: the channel layer is annealed after a thermal oxidation process is performed or after a channel protection layer is deposited.
In the above scheme, the semiconductor device is a three-dimensional memory.
The embodiment of the invention also provides a semiconductor device channel layer, which is prepared and formed by the preparation method in any one of the schemes.
Embodiments of the present invention further provide a channel layer of a semiconductor device, where the channel layer is formed in a channel via of the semiconductor device, the channel layer is doped with an impurity for increasing carrier density, and a doping concentration of the impurity is gradually decreased along a radially inward direction of the channel via.
In the above scheme, the impurities include N-type impurity ions or rare earth elements.
In the above scheme, the semiconductor device is a three-dimensional memory.
According to the preparation method of the semiconductor device channel layer and the semiconductor device channel layer, provided by the embodiment of the invention, the semiconductor device is provided, the channel through hole is formed in the semiconductor device, and the functional layer is formed in the channel through hole; depositing a channel layer on the functional layer, wherein the channel layer is a first semiconductor material layer; depositing a doping layer on the channel layer, wherein the doping layer is a second semiconductor material layer doped with impurities; performing a thermal oxidation process to form a second semiconductor material oxide layer on one side of the second semiconductor material layer far away from the functional layer; wherein the impurity is selected from materials having a higher solid solubility in the first layer of semiconductor material than in the second oxide layer of semiconductor material; thereby forming a channel layer of a semiconductor device, wherein the channel layer is formed in a channel through hole of the semiconductor device, the channel layer is doped with impurities for improving carrier density, and the doping concentration of the impurities is gradually reduced along the radial direction inward of the channel through hole. Thus, by depositing the channel layer on the functional layer, adopting the thermal oxidation process to enrich the doped ions towards the functional layer and redistribute the doped ions in the channel layer, the channel layer of the semiconductor device with high doped concentration and good uniformity is obtained; moreover, because the required high doping concentration can be realized through the enrichment function of the thermal oxidation process, the channel material layer with high concentration does not need to be directly deposited when the channel material layer is deposited, the influence of the doping concentration on the grain size and the process stability in the deposition process is avoided, the channel material layer with relatively low concentration or even no doping is deposited, the requirement of the field on the grain size in the channel layer is ensured, the ion doping concentration is gradually increased in the thermal oxidation process, and the channel layer with high doping concentration is finally obtained, so that the channel carrier concentration is increased, the channel resistance value is reduced, and the working performance of a semiconductor device is improved.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a channel layer of a semiconductor device according to an embodiment of the present invention;
fig. 2 to 6 are schematic cross-sectional views of device structures in a process of manufacturing a channel layer of a semiconductor device according to an embodiment of the present invention.
Description of reference numerals:
10-a semiconductor substrate;
11-a laminated structure; 111-a first material layer; 112-a second material layer; 113-a sacrificial layer;
12-a functional layer; 121-a barrier layer; 122-a trapping layer; 123-tunneling layer;
13-a channel layer;
14-a doped layer;
15-a second oxide layer of semiconductor material;
16-channel protection layer.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on … …," "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above", "over … …", and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In the related art, there is a higher demand for the turn-on capability of the channel layer of the semiconductor device; for example, for a three-dimensional memory device, as the number of device stacks increases, the channel length also increases, and the channel layer resistance needs to be further reduced to meet the functional requirements of the device. In this case, it is increasingly difficult to satisfy the actual demand by improvement of the lattice structure alone. Therefore, doping impurity ions to improve carrier density and further improve channel conduction capability becomes a hot point for developing next-generation memories. However, as the depth-to-width ratio of the channel through hole of the three-dimensional memory device is larger and larger, the conventional ion implantation method and the CVD impurity ion doping method cannot meet the requirement of the channel on the uniformity of the germanium concentration, and the doping concentration and the grain size control cannot meet the requirement of process control; the selective epitaxial growth commonly used in two-dimensional devices is not suitable for three-dimensional structure devices. Accordingly, the present invention is directed to a method for manufacturing a channel layer of a semiconductor device and a channel layer structure of a semiconductor device, so as to increase the carrier concentration of a channel, reduce the resistance of the channel, and improve the working performance of the semiconductor device.
The present invention will be described in further detail with reference to examples.
Fig. 1 is a schematic flow chart of a method for manufacturing a channel layer of a semiconductor device according to an embodiment of the present invention; as shown in fig. 1, the method comprises the steps of:
102, depositing a channel layer on the functional layer, wherein the channel layer is a first semiconductor material layer;
103, depositing a doping layer on the channel layer, wherein the doping layer is a second semiconductor material layer doped with impurity ions;
104, performing a thermal oxidation process to form a second semiconductor material oxide layer on the side, away from the functional layer, of the second semiconductor material layer;
wherein the impurity ions are selected from materials having a higher solid solubility in the first layer of semiconductor material than in the second layer of oxide of semiconductor material.
In particular, fig. 2 to 6 show schematic cross-sectional views of device structures in a manufacturing process of a three-dimensional memory device according to an embodiment of the present invention.
First, please refer to fig. 2. As shown, in step 101, a semiconductor device is provided, the semiconductor device comprising a semiconductor substrate 10; the semiconductor substrate 10 may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
A stacked structure 11 in which first material layers 111 and second material layers 112 are alternately stacked is formed on the semiconductor substrate 10. Here, the first material layer 111 may be a dielectric layer, which includes, but is not limited to, silicon oxide, silicon nitride layer, silicon oxynitride, and other high dielectric constant (high-k) dielectric layers; the second material layer 112 may be a sacrificial layer, and may be formed of, for example, one of an oxide layer, a nitride layer, a silicon carbide layer, a silicon layer, and a silicon germanium layer. In this embodiment, the first material layer 111 may be made of SiO2The second material layer 112 may be formed of SiN, so that the stack structure 11 formed is an NO stack. The first material layer and the second material layer may be formed using a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or an Atomic Layer Deposition (ALD) process; the first material layer and the second material layer may have the same thickness as each other, or may have different thicknesses from each other. In one embodiment, the first material layer 111 at the lowest layer in the stacked structure 11 may be formed by oxidation; the bottom penultimate first material layer 111 in the stacked structure 11 may be formed by deposition and compared toFirst material layer thickness of other layers in the laminated structure 11; each second material layer 112 may have substantially the same thickness. In another embodiment, the stacked structure 11 may further include a sacrificial layer 113, wherein the sacrificial layer 113 is located at a top region of the stacked structure 11. The sacrificial layer 113 is used for protecting the first material layer and the second material layer from being damaged when the stacked structure 11 is subjected to etching treatment in the following; the material of the consumption layer 113 may include SiNO or SiO2。
In an embodiment of the present invention, the method further includes: and etching the laminated structure 11 to form a channel through hole CH, wherein the channel through hole CH exposes the semiconductor substrate 10. The trench via CH may be formed through a dry etching process. Optionally, an epitaxial layer (SEG) is formed on the semiconductor substrate 10 at the bottom of the trench via CH. The epitaxial layer may be formed by selectively epitaxially growing single crystal silicon, and may serve as a lower selection pipe channel.
With continued reference to fig. 2, a functional layer 12 of the semiconductor device is also included within the trench via CH of the semiconductor device. In an embodiment, the functional layer 12 may include a blocking layer, a storage layer, and a tunneling layer structure sequentially disposed along a radially inward direction of the trench via CH; the layers can be made of single materials or composite layers; in particular, the functional layer 12 may be an ONO stack, an AONO stack, an ONOP stack or other suitable gate stack structure. In this embodiment, the process of forming the functional layer 12 may specifically include: depositing a high-k dielectric layer (e.g., Al) in the trench via CH2O3Layer), the high-k dielectric layer may have a relatively thin thickness; depositing an oxide layer (e.g., SiO) on the high-k dielectric layer2A layer); the high-k dielectric layer and the oxide layer jointly form a barrier layer 121, and the barrier layer 121 is a composite charge barrier layer; continuing to deposit a storage layer 122 over the oxide layer, the storage layer 122 being, for example, a charge trapping layer, which may be a nitride (e.g., SiN layer); depositing a tunneling layer 123 on the storage layer 122, wherein the material of the tunneling layer 123 may be an oxide (e.g., SiO)2A layer); the blocking layer 121, the memory layer 122, and the tunneling layer 123 collectively function to control the charge storage function of the memory device, and therefore, the functional layer 12 may also be referred to as a memory layer of the semiconductor device. The functional layer 12 may be deposited using a CVD or ALD process.
In one embodiment, after the formation of the functional layer 12, a step of etching the bottom of the functional layer 12 to expose the epitaxial layer SEG may be included.
Next, please refer to fig. 3. In step 102, a channel layer 13 is deposited on the functional layer 12, the channel layer 13 being a first semiconductor material layer. Specifically, the first semiconductor material may be a silicon-based material; further, it may be a polysilicon material, for example, including elemental polysilicon or doped polysilicon; in addition, the first semiconductor material may further include at least one of semiconductor materials such as polycrystalline silicon germanium, silicon carbon, germanium, and the like. In one embodiment, the channel layer 13 may be deposited by a CVD or ALD method. The thickness of the channel layer 13 may be 3-20 nm. In the embodiment of the present invention, due to the process limitation, the deposition of the channel layer needs to be completed first, and then the deposition of the doping layer needs to be performed. The channel layer provides a channel for movement of carriers for the semiconductor device.
Next, please refer to fig. 4. In step 103, a doped layer 14 is deposited on the channel layer 13, wherein the doped layer 14 is a second semiconductor material layer doped with impurity ions. Specifically, the second semiconductor material may also be a silicon-based material; further, amorphous silicon may be used. The impurity ions are selected from materials having a higher solid solubility in the first layer of semiconductor material than in the second oxide layer of semiconductor material. The second semiconductor material layer having impurity ion doping may be deposited by a CVD or ALD process; and is preferably deposited by an ALD process to achieve better layer thickness control.
In one embodiment, the impurity ions are N-type impurity ions. Preferably, the impurity ions may be phosphorus (P) or arsenic (As). The source of impurity ions used in the deposition process may comprise phosphane or arsane. Further, the gas source may also include a polyfluoro/chlorophosphane or a polyfluoro/chloropharsane, such as at least one of methyldifluorophosphane, methyldichlorophosphane, methyldifluoroarsene, and methyldichloroarsene; when the gas source comprises polyfluoro/chlorophosphane or polyfluoro/chloroarsene, acid may be generated in the reaction by-product, thereby improving the defect situation of the process. The impurity ion may be other suitable group-five elements, such as antimony (Sb) and bismuth (Bi). The impurity ions can enter the channel layer after the subsequent process, so that the channel layer is changed from the intrinsic layer to the N-type semiconductor layer, the number of electrons in the channel layer is increased, and the conduction performance of the channel layer is improved.
In another embodiment, the impurity ions are rare earth elements. Further, the impurity ions may include rare earth elements such as lanthanum (La), cerium (Ce), europium (Eu), and the like. After the rare earth element impurity ions enter the channel layer through a subsequent process, the carrier concentration of the channel layer can be improved, and therefore the conduction performance of the channel layer is improved.
Next, please refer to fig. 5. In step 104, a thermal oxidation process is performed to form a second semiconductor material oxide layer 15 on a side of the second semiconductor material layer (i.e., the doped layer 14) away from the functional layer 12.
As can be understood, since the solid solubility of the impurity ions in the first semiconductor material layer 13 is higher than that in the second semiconductor material oxide layer 15, the impurity ions can be enriched toward the functional layer 12 as the thermal oxidation process proceeds; that is, with the formation of the second semiconductor material oxide layer 15, the impurity ions are diffused from the second semiconductor material layer into the first semiconductor material layer, so that a required ion-doped channel layer is obtained, the channel carrier concentration is increased, the channel resistance is reduced, and the working performance of the semiconductor device is improved. The preparation method provided by the embodiment of the invention can meet the requirement of a multi-layer storage structure (such as 64 layers or more) on the low resistance of the channel layer.
Further, the channel layer formed by the preparation method provided by the present embodiment is doped with impurities for increasing carrier density, and due to the effect of the thermal oxidation process, the doping concentration of the impurities is gradually decreased in a radially inward direction of the channel via.
In one embodiment, the oxidation temperature of the thermal oxidation process is 300-800 ℃. Further, the oxidation time of the thermal oxidation process is 3-60 minutes. The oxidation reaction gas of the thermal oxidation process may include oxygen or water vapor; in the embodiment of the invention, oxygen or water vapor is used as carrier gas (carrier gas) in the thermal oxidation reaction process, so that the reaction temperature distribution is more uniform; in addition, the oxide protective layer can be formed on the surface of the channel material layer.
It should be noted that, in the embodiment of the present invention, the side of the second semiconductor material layer (i.e., the doped layer 14) away from the functional layer 12 is formed as the second semiconductor material oxide layer 15, which means that at least the side of the second semiconductor material layer 14 away from the functional layer 12 is oxidized into an oxide layer, and there is no strict limitation on which part of the second and first semiconductor material layers the formation of the oxide layer is finally terminated, as long as an unoxidized channel layer is finally remained. For example, one of the following situations may be included: 1) a part of the second semiconductor material layer far away from the functional layer is formed into a second semiconductor material oxide layer, and the other part of the second semiconductor material layer is not oxidized; further, when the second semiconductor material layer is an amorphous silicon layer, the remaining unoxidized portion is recrystallized in a thermal oxidation process and a subsequent annealing process; 2) the second semiconductor material layer is oxidized into an oxide layer, and the first semiconductor material layer becomes a final channel layer of the semiconductor device after being enriched by impurity ions; 3) the second semiconductor material layer is oxidized into an oxide layer in a whole, and a part of the first semiconductor material layer close to the second semiconductor material layer is oxidized, but at least a channel layer which is not oxidized is remained in the first semiconductor material layer.
In an embodiment, the first semiconductor material layer and the second semiconductor material layer are silicon-based material layers, and the second semiconductor material layerThe oxide layer of bulk material being an oxide layer of silicon, e.g. SiO2And (3) a layer.
Please refer to fig. 6. In an embodiment of the present invention, the method may further include: after performing the thermal oxidation process, the channel protection layer 16 is deposited. The channel protection layer 16 may be composed of a silicon-based compound; for example SiO2A layer; the channel protection layer 16 remains in the finally fabricated semiconductor device and serves to protect the channel layer 14 from damage; the channel protection layer 16 may or may not fill the channel via CH. Here, the channel protection layer 16 may be directly deposited on the second oxide layer of semiconductor material and may function as a protection structure of the channel layer together with the second oxide layer of semiconductor material (not distinguished in the drawing, i.e., the second oxide layer of semiconductor material 15 is not shown). In other embodiments, the oxide layer of the second semiconductor material generated by oxidation may be removed in advance, and then a protective layer 16 may be deposited on the doped channel layer; that is, in an embodiment, the method further comprises: after the thermal oxidation process is carried out, the second semiconductor material oxide layer is reserved, and a channel protection layer is deposited; in another embodiment, the method further comprises: and after the thermal oxidation process is carried out, removing the second semiconductor material oxide layer and depositing a channel protection layer. The channel protection layer 16 may be deposited using a CVD or ALD method.
Please continue to refer to fig. 6. In an embodiment of the present invention, the method may further include: the channel layer is annealed after a thermal oxidation process is performed or after a channel protection layer is deposited. Through the annealing process, the impurity ions can be better fixed in the channel layer, and the uniformity of the impurity ions in the channel layer is improved, so that the carrier concentration of the channel layer is improved, and the resistance value of the channel is further reduced. The selection of annealing after the channel protective layer is deposited can eliminate the interface state between the protective layer and the channel layer, and further improve the working performance of the device. It should be noted that the annealing process may be a diffusion annealing process performed exclusively or a high temperature process performed for other subsequent processes.
Further, the semiconductor device in the embodiment of the present invention may be a three-dimensional memory; specifically, the three-dimensional NAND memory can be used.
Based on the above method, an embodiment of the present invention further provides a channel layer of a semiconductor device, the channel layer being formed by the manufacturing method described in any one of the above embodiments.
Embodiments of the present invention further provide a channel layer of a semiconductor device, where the channel layer is formed in a channel via of the semiconductor device, the channel layer is doped with an impurity for increasing carrier density, and a doping concentration of the impurity is gradually decreased along a radially inward direction of the channel via.
In one embodiment, the impurity includes an N-type impurity ion or a rare earth element.
In one embodiment, the semiconductor device is a three-dimensional memory.
It should be noted that the embodiments of the method for manufacturing the semiconductor device channel layer structure and the semiconductor device channel layer structure provided in the embodiments of the present invention belong to the same concept, and specific implementation processes and other detailed structures thereof are described in detail in the embodiments of the method and are not described herein again.
It should be noted that the technical features described in the embodiments of the present invention may be arbitrarily combined without conflict between the technical features.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.
Claims (19)
1. A method for preparing a channel layer of a semiconductor device, the method comprising the steps of:
providing a semiconductor device, wherein a channel through hole is formed in the semiconductor device, and a functional layer is formed in the channel through hole;
depositing a channel layer on the functional layer, wherein the channel layer is a first semiconductor material layer;
depositing a doping layer on the channel layer, wherein the doping layer is a second semiconductor material layer doped with impurities;
performing a thermal oxidation process to form a second semiconductor material oxide layer on the side of the second semiconductor material layer far away from the functional layer, so that the impurities are diffused from the second semiconductor material layer to the first semiconductor material layer;
wherein the impurity is selected from materials having a higher solid solubility in the first layer of semiconductor material than in the second layer of oxide of semiconductor material.
2. The method of claim 1, wherein the first semiconductor material layer and the second semiconductor material layer are silicon-based material layers.
3. The method of claim 2, wherein the first layer of semiconductor material is a layer of polysilicon.
4. The method of claim 2, wherein the second semiconductor material layer is an amorphous silicon layer.
5. The method of claim 1, wherein the impurity is an N-type impurity ion or a rare earth element.
6. The method of claim 1, wherein the second layer of semiconductor material having impurity doping is deposited by a CVD or ALD process.
7. The method of claim 6, wherein the source of the impurity gas used in the deposition process comprises phosphane or arsane.
8. The method as claimed in any one of claims 1 to 7, wherein the oxidation temperature of the thermal oxidation process is 300-800 ℃.
9. The method according to claim 8, characterized in that the oxidation time of the thermal oxidation process is 3-60 minutes.
10. The method according to any one of claims 1 to 7, wherein the reaction gas of the thermal oxidation process comprises oxygen or water vapor.
11. The method of claim 1, wherein the functional layer comprises a blocking layer, a storage layer, and a tunneling layer sequentially disposed in a radially inward direction of the trench via.
12. The method of claim 1, further comprising: and after the thermal oxidation process is carried out, removing the second semiconductor material oxide layer and depositing a channel protection layer.
13. The method of claim 1, further comprising: and after the thermal oxidation process is carried out, the second semiconductor material oxide layer is reserved, and a channel protection layer is deposited.
14. The method according to claim 1 or 13, further comprising: the channel layer is annealed after a thermal oxidation process is performed or after a channel protection layer is deposited.
15. The method of claim 1, wherein the semiconductor device is a three-dimensional memory.
16. A channel layer of a semiconductor device, wherein the channel layer is formed by the fabrication method of any one of claims 1 to 15.
17. A semiconductor device is characterized in that a channel through hole is formed in the semiconductor device, a functional layer, a channel layer and a second semiconductor material layer are sequentially formed in the channel through hole, and a part of the second semiconductor material layer far away from the functional layer is formed into a second semiconductor material oxide layer; wherein,
the channel layer is doped with impurities for increasing carrier density, and the doping concentration of the impurities is gradually reduced along the radial inward direction of the channel through hole.
18. The semiconductor device according to claim 17, wherein the impurity comprises an N-type impurity ion or a rare earth element.
19. The semiconductor device according to claim 17, wherein the semiconductor device is a three-dimensional memory.
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