KR20080094381A - Non-volatile memory integrate circuit device - Google Patents

Abstract

A non-volatile memory integrated circuit device is provided to reduce a leakage current by using a high dielectric material in a dielectric layer. A source region and a drain region are formed on a substrate. A channel region is formed between the source region and the drain region. A tunnel dielectric layer(110) is formed on the channel region. A floating gate(120) is formed on the tunnel dielectric layer. An intergate dielectric layer structure(130) is formed on the floating gate, including a first insulation layer(131) having metal and oxygen and a second insulation layer(135) having metal, oxygen and nitrogen. A control gate(140) is formed on the intergate dielectric layer structure. The first insulation layer can be an aluminum oxide layer, and the second insulation layer can be a hafnium silicate nitride layer.

Description

Non-volatile memory integrated circuit device

1 is a cross-sectional view of a nonvolatile memory integrated circuit device according to an embodiment of the present invention.

2A-3C are cross-sectional views of an inter-gate dielectric film structure of a nonvolatile memory integrated circuit circuit device in other embodiments of the present invention.

4 is a cross-sectional view of a nonvolatile memory integrated circuit device according to another embodiment of the present invention.

FIG. 5A is a circuit diagram of a cell array region of a NAND type nonvolatile memory integrated circuit device to which embodiments of the present invention are applied, and FIG. 5B is a layout of the cell array region.

FIG. 6 is a cross-sectional view of a NAND type nonvolatile memory integrated circuit device to which embodiments of the present invention, which are formed along the circuit diagram and the layout shown in FIGS. 5A and 5B, are applied.

7 is a graph showing the effect of a NAND type nonvolatile memory integrated circuit device according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

110, 110_1, and 610: tunnel dielectric layers 120 and 620: floating gates

130, 130_1, and 730a: inter-gate dielectric film structures 131 and 631: first insulating film

135, 635: second insulating film 140, 640: control gate

650: damascene metal film pattern

 The present invention relates to a nonvolatile memory integrated circuit device, and more particularly, to a nonvolatile memory integrated circuit device using a dielectric film using a high-k material.

The nonvolatile memory integrated circuit device can retain stored data even when the power supply is cut off. Therefore, nonvolatile memory integrated circuit devices are widely used in information communication devices such as digital cameras, mobile phones, PDAs, MP3 players, and the like.

(ε:유전율, A:유전막의 면적, T:유전막의 두께)이므로 유전막 의 두께를 조절하여 캐피시턴스를 조절하였으나, 유전막의 두께가 얇아질수록 유전막에서의 누설전류 문제가 생겼다. 그래서 유전막의 면적 내지 유전막을 이루는 물질의 유전율을 변화시켜 캐패시턴스를 조절하게 되었다. 유전막의 면적을 조절하는 것에는 집적회로 내에서 한계가 있으므로, 현재는 유전율(ε)이 높은 고유전율 물질을 도입하여 캐패시턴스를 높이는 추세이다. 하지만 고유전율 물질을 도입함에 있어, 고유전율 물질의 결정화와 전자 트랩(electron trap) 문제가 대두되고 있다.However, due to the multifunctionality and high functionality of the information communication apparatus, a large capacity and high integration of the nonvolatile memory integrated circuit device are required. Accordingly, the size of the memory cells constituting the nonvolatile memory integrated circuit device is rapidly progressing. . Thus, in order to improve performance of a nonvolatile memory integrated circuit device, a memory cell of a nonvolatile memory integrated circuit device requires a tunnel dielectric film and an inter-gate dielectric film structure, each dielectric film having a higher capacitance. Capacitance (C) is

(ε: dielectric constant, A: dielectric film area, T: dielectric film thickness), the capacitance was adjusted by controlling the thickness of the dielectric film. However, as the thickness of the dielectric film became thinner, a leakage current problem in the dielectric film occurred. Therefore, the capacitance is adjusted by changing the dielectric constant of the material of the dielectric film and the area of the dielectric film. Since controlling the area of the dielectric film has a limitation in the integrated circuit, it is currently a trend to increase capacitance by introducing a high-k material having a high dielectric constant?. However, in introducing high dielectric constant materials, crystallization and electron trap problems of high dielectric constant materials have emerged.

An object of the present invention is to provide a nonvolatile memory integrated circuit device having improved performance by using a dielectric film made of a high dielectric constant material.

The technical problem of the present invention is not limited to the technical problem mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In accordance with one aspect of the present invention, a nonvolatile memory integrated circuit device includes a source and drain region formed on a substrate, a channel region formed between the source and drain regions, a tunnel dielectric layer formed on the channel region, and a tunnel dielectric layer. A floating gate formed on the floating gate, the inter-gate dielectric film structure formed on the floating gate, wherein the inter-gate dielectric film structure includes a first insulating film containing metal and oxygen and a second insulating film including metal, oxygen, and nitrogen An inter dielectric layer structure, and a control gate formed on the inter-gate dielectric layer structure.

According to another aspect of the present invention, a nonvolatile memory integrated circuit device includes a source and drain region formed on a substrate, a channel region formed between the source and drain regions, and a tunnel dielectric layer formed on the channel region. The dielectric film includes a tunnel dielectric film including a first insulating film including metal and oxygen, a second insulating film including metal, oxygen, and nitrogen, a floating gate formed on the tunnel dielectric film, an inter-gate dielectric film structure and a gate formed on the floating gate, and the like. And a control gate formed on the liver dielectric layer structure.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. In the following description of the manufacturing method, a process that can be formed according to process steps well known to those skilled in the art will be briefly described in order to avoid being construed as obscuring the present invention. Also, like reference numerals refer to like elements throughout the specification.

1 to 6C, a nonvolatile memory integrated circuit device according to embodiments of the present invention will be described.

1 is a cross-sectional view of a nonvolatile memory integrated circuit device according to an embodiment of the present invention.

Referring to FIG. 1, a memory cell includes source and gate regions 105a and 105b and a channel region 107 formed on a substrate 101. Source and gate regions 105a and 105b may be doped with N-type or P-type, and channel region 107 serves as a current transfer path between source and gate regions 105a and 105b in operation of a nonvolatile memory integrated circuit device. Do it.

The tunnel dielectric layer 110, the floating gate 120, the inter-gate dielectric layer structure 130, and the control gate 140 are formed on the channel region 107. In the nonvolatile memory integrated circuit device, data is stored by applying an appropriate voltage to the control gate 140 and the substrate 101 to insert or draw electrons into the floating gate 120 through the tunnel dielectric layer 110. In this case, the inter-gate dielectric layer structure 130 maintains charge characteristics charged in the floating gate 120 and transfers the voltage of the control gate 140 to the floating gate 120.

Specifically, the inter-gate dielectric film structure 130 has a three-layer stacked structure in which the second insulating film 135 is disposed between the first insulating film 131. The first insulating layer 131 includes metal and oxygen, and may be Al _x O _y , Hf _x O _y , HfSi _x O _{y ,} Zr _x O _y , ZrSi _x O _{y ,} Ta _x O _y, or the like. The second insulating layer 135 includes metal, oxygen, and nitrogen, and Al _x O _y N _{z ,} Hf _x O _y N _z , HfSi _x O _y N _z , Zr _x O _y N _{z ,} ZrSi _x O _y N _z , Ta _x O _y N _z And the like. The material constituting the second insulating layer 135 is a nitride of metal oxide (MO _x ) to silicon metal oxide (MSi _x O _y ), and has a higher dielectric constant than the material constituting the first insulating layer 131. In addition, the material constituting the second insulating film 135 has less room to trap electrons than the material constituting the first insulating film 131. (The detailed description thereof will be described later using experimental examples.)

The first insulating layer 131 may be formed by depositing a material containing a metal and oxygen by a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. It may also be made by first depositing a metal material and then oxidizing the metal film. The oxidation process may be a wet oxidation process performed in an atmosphere in which O ₂ , H ₂ O gas is provided, or a radical oxidation process proceeding in an atmosphere in which O ₂ , H ₂ gas is provided.

The second insulating layer 135 may be made by depositing a metal and oxygen-containing material by a process such as CVD, PVD, ALD, and the like and nitriding the metal oxide film by an ammonia (NH ₃ ) annealing, plasma nitridation process, or the like. Ammonia (NH ₃ ) may also be nitrided by replacing with nitrogen monoxide (NO) or nitrogen dioxide (NO ₂ ). The second insulating film may be formed by first depositing a metal material and then sequentially oxidizing and nitriding the metal film. Alternatively, the metal material may be deposited first, and then formed by performing an acid-nitridation reaction in an oxygen and nitrogen atmosphere.

For example, when the first insulating film 131 is Al _x O _y and the second insulating film 135 is HfSi _x O _y N _z , first, the first insulating film 131 is Al _x O _y. The film can be formed by evaporation by a process such as CVD, PVD, ALD, or the like. Alternatively, Al may be deposited first, followed by oxidation of the Al film to make Al _x O _y . The Al _x O _y film may have a thickness of about 10 to about 100 microns. Next, HfSi _x O _y N _z which is the second insulating layer 135. In order to make a film, HfO ₂ , SiO ₂ may be first deposited by a process such as CVD, PVD, ALD, etc. to form an HfSi _x O _y film, and then nitrided by ammonia (NH ₃ ) annealing. Nitriding by ammonia (NH ₃ ) annealing can be carried out within a temperature range of 400-1200 ° C. and 10 seconds for 3 hours. Here, the temperature of the annealing process may be adjusted within the crystallization temperature of the HfSi _x O _y film, and the thickness of the HfSi _x O _y layer may be 10 to 200 kPa.

Other embodiments of the present invention will be described with reference to FIGS. 2A to 3C.

2A-3C are cross-sectional views of an inter-gate dielectric film structure of a nonvolatile memory integrated circuit device in other embodiments of the present invention. The size, shape, material, etc. of each component described in the above structure are omitted to avoid duplication of description.

Referring to FIG. 2A, in the inter-gate dielectric film structure 130_1, the first insulating film 131 and the second insulating film 135 are stacked in three or more layers. The second insulating layer 135 is stacked between the first insulating layer 131, and the thickness of each of the insulating layers 131 and 115 is laminated in three or more layers in a thinner form than in the above embodiment. Since the thicknesses of the insulating films 131 and 135 become thinner, the crystallization of the material layer generated during the deposition of the material layer can be suppressed. Crystallization that occurs during material layer deposition is caused by the temperature at which the material is crystallized and the thickness of the deposited layer, because the effect of thickness is greater than the effect of temperature. When a material having a high dielectric constant is used as the insulating film, although the leakage current through the insulating film must decrease as the equivalent oxide thickness increases, in practice, this may not be the case. One of the causes of this is surface roughness due to the crystallization of the material layer and the influence of the electric field concentrated on the grain boundary. Therefore, as the crystallization is suppressed, the amount of leakage current can be reduced, which can improve the reliability of the nonvolatile memory integrated circuit device.

Referring to FIG. 2B, in another embodiment of the present invention, in the inter-gate dielectric layer structure 130_2, the first insulating layer 131 and the second insulating layer 135 are alternately stacked by an ALD process. The difference from other embodiments of the present invention is that the first and second insulating layers 131 and 135 are stacked to a molecular thickness. In another embodiment of the present invention, the first insulating layer 131 may be formed by depositing a metal oxide by an ALD process, or may be formed by first depositing a metal material and then oxidizing the metal film. The second insulating layer 135 may be formed by depositing a metal oxide by an ALD process and nitriding a metal oxide layer. Alternatively, the second insulating layer 135 may be formed by sequentially oxidizing and nitriding a metal layer after depositing a metal material. After the metal film is formed by vapor deposition, an acid-nitridation reaction may be applied to the metal film to form the second insulating film 135.

3A through 3C, the inter-gate dielectric layer structures 130_3, 130_4 and 130_5 according to still another embodiment of the present invention may have a first insulating layer 131 stacked between the second insulating layers 135. Referring to FIG. 3A, the inter-gate dielectric film structure 130_3 may have a stacked structure of three layers in which the first insulating film 131 is interposed between the second insulating films 135. Referring to FIG. 3B, the inter-gate dielectric film structure 130_4 may have a structure of a plurality of layers having a first insulating film 131 between the second insulating film 135. Referring to FIG. 3C, a plurality of layers may be formed by an ALD process. An inter-gate dielectric film structure 130_5 having a structure may be formed. In the inter-gate dielectric film structure having the same effect, in the case of the stacked structure in which the first insulating film 131 is disposed between the second insulating films 135, the stacked structure in which the second insulating film 135 is provided between the first insulating films 131. In comparison, the thicknesses of the insulating layers 131 and 135 may vary.

4 is a cross-sectional view of a nonvolatile memory integrated circuit device according to another embodiment of the present invention. The size, shape, material, etc. of each component described in the above structure are omitted to avoid duplication of description.

Referring to FIG. 4, the tunnel dielectric layer 110_1 is formed in a structure including a first insulating layer 111 and a second insulating layer 115. The tunnel dielectric layer 110_1 has a three-layer stacked structure in which a second insulating layer 135 is provided between the first insulating layers 131. However, the inter-gate dielectric film structure 132 may be formed of ONO, SiO ₂ , Al _x O _y , or the like, and may be configured in the form described in the above embodiments.

Although not shown in the drawings, the tunnel dielectric film may have a structure having a plurality of layers having a second insulating film between the first insulating films, or a stacked structure having a first insulating film between the second insulating films. However, when the tunnel dielectric layer is a laminated structure including the first insulating layer and the second insulating layer, the inter-gate dielectric layer structure may be thinner than when the tunnel dielectric layer is the laminated structure including the first insulating layer and the second insulating layer.

5A to 6, a specific example in which embodiments according to the present invention are utilized in a NAND type nonvolatile memory integrated circuit device will be described. However, the memory cell structure of the present invention can be applied to both NOR type and NAND type nonvolatile memory integrated circuit devices, and is not limited to the NAND type nonvolatile memory integrated circuit devices.

5A is a circuit diagram of a cell array region of a NAND type nonvolatile memory integrated circuit device to which embodiments according to an aspect of the present invention is applied, and FIG. 5B is a layout of the cell array region.

5A and 5B, a plurality of active regions AR are arranged in a cell array region of a NAND type nonvolatile memory integrated circuit device, and a string select line SSL and a ground select are perpendicular to the active region AR. Line GSL and common source line CSL are arranged. A plurality of word lines WL0 to WLm−1 are arranged between the string select line SSL and the ground select line GSL. The plurality of bit lines BL0 to BLn-1 are arranged to intersect the plurality of word lines WL0 to WLm-1. Memory cell transistors MC are defined in regions where bit lines BL0 to BLn-1 and word lines WL0 to WLm-1 cross each other, and bit lines WL0 to WLm-1 and string select lines The string select transistor SST and the ground select transistor GST are defined in regions where the SSL and the ground select line GSL cross each other. The string select transistor SST, the plurality of memory cell transistors MC, and the ground select transistor GST are connected in series to form one string S. The strings S formed for each of the cell blocks BLK0 to BLK1-1 for each bit line BL are connected in parallel. That is, the drain of the string select transistor SST of each string S is connected to the bit line BL. The source of the ground select transistor GST is connected to the common source line CSL.

6 is a cross-sectional view of a nonvolatile memory integrated circuit device according to an embodiment of the present invention formed along the circuit diagram and layout shown in FIGS. 5A and 5B. Here, the cell array region of FIG. 6 is a portion cut along VI′-VI of FIG. 5B.

Referring to FIG. 6, a plurality of active regions AR are repeatedly arranged in a cell array region, and a plurality of first and second stacked gate structures 604 and 605 are formed on the cell array region. In addition, an interlayer insulating layer 660 is formed on the plurality of first and second stacked gate structures 604 and 605, and a bit line contact hole BLC on the bit line junction region 605a for connection with the bit line BL. ) Is formed. The first stacked gate structure 604 may correspond to a gate of the memory cell transistor MC, and the second stacked gate structure 606 may correspond to a gate of the string select transistor SST or the ground select transistor GST. can do. In each string (see S in FIG. 5A), a plurality of memory cell transistors (see MC in FIG. 5A) are connected in series, so that the first stacked gate structures 604 may be connected to the respective first stacked gate structures 604. The drain and source regions (see 105a and 105b in FIG. 1) are arranged to share the junction region 605.

The first stacked gate structure 604 is a structure in which the tunnel dielectric layer 610, the floating gate 620, the inter-gate dielectric layer structure 630, the control gate 640, and the damascene metal layer pattern 350 are sequentially stacked. .

The tunnel dielectric layer 610 may be configured by citing a material suitable for tunneling electrons, for example, SiO ₂ , Hf _× O _y , and the like. In addition, the tunnel dielectric layer 610 may be configured by the embodiments described above.

The floating gate 620 is a region in which electrons tunneling the tunnel dielectric layer 610 are stored, and may be made of polysilicon doped with metal or impurities.

The inter-gate dielectric film structure 630 may be a stacked structure of three layers having a second insulating film 635 between the first insulating film 631. In addition, although not shown in the drawings, the inter-gate dielectric film structure may be configured by the embodiments of the present invention described above.

The control gate 640 adjusts the voltage applied to the floating gate 620, and may be made of metal or doped polysilicon. In addition, the damascene metal film pattern 650 is a metal film pattern manufactured through a damascene process, and may be W, Al, Cu, Pt, and a mixed film thereof.

On the other hand, in the second stacked gate structure 606, the inter-gate dielectric layer structure 637 may be partially removed (shown in FIG. 6), or may be entirely removed to electrically connect the floating gate 620 and the control gate 640. have. The material and the thickness of the tunnel dielectric layer 610, the floating gate 620, and the inter-gate dielectric layer structure 630 of the second stacked gate structure 606 may be the same as that of the first stacked gate structure 604. have. The material constituting the control gate 640 and the damascene metal film pattern 650 of the second stacked gate structure 606 may also be the same as that of the first stacked gate structure 604. Further, although the second stacked gate structure 606 and the first stacked gate structure 604 are shown at the same height in the drawing, the second stacked gate structure may be lower than the first stacked gate structure 604.

More detailed information about the present invention will be described through the following specific experimental examples, and details not described herein will be omitted because it is sufficiently technically inferred by those skilled in the art.

Experimental Example

In a NAND type nonvolatile memory integrated circuit device, when the inter-gate dielectric film structure is composed of Al _x O _y (I) and the inter-gate dielectric film structure is formed according to an embodiment of the present invention (see FIG. 6), the first insulating film is Al _x O _{In the case where y} and the second insulating film were composed of HfSi _x O _y N _z (II), electron traps generated in the inter-gate dielectric film structure were measured. The results are shown in FIG.

Here, in the case of the Al _x O _y single layer (I), the thickness of the film was 200 to 400 GPa, and according to the embodiment of the present invention (II), the first insulating film Al _x O _y was 50 to 75 GPa and the second insulating film was HfSi _x. O _y N _z is 70 to 100 Hz.

In FIG. 7, the x axis represents time, and the y axis represents voltage caused by an electron trap generated in the inter-gate dielectric film structure over time. In the present experimental example, it can be seen that the electron trap was about 50% smaller in case (II) according to the embodiment of the present invention than in the case of Al _{x Oy} single layer (see reference numeral a).

In the case of HfSi _x O _y , there are fewer bulk traps that can structurally trap electrons compared to Al _x O _y , and the bulk trap is further reduced by nitriding, for example, NH ₃ annealing. The electron trap in the inter-gate dielectric film structure can be reduced.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the nonvolatile memory integrated circuit device as described above, there are one or more of the following effects.

First, leakage current can be reduced by using a high dielectric constant material in the dielectric film.

Second, by reducing the electron trap in the dielectric film, it is possible to more effectively control the amount of charge stored in the floating gate according to the voltage applied to the control gate, thereby improving the performance of the nonvolatile memory integrated circuit device.

Third, crystallization of the high dielectric constant material can be suppressed, so that the reliability of the nonvolatile memory integrated circuit device can be improved.

Claims (10)

Source and drain regions formed on the substrate; A channel region formed between the source and drain regions; A tunnel dielectric layer formed on the channel region; A floating gate formed on the tunnel dielectric layer; An inter-gate dielectric film structure formed on the floating gate, wherein the inter-gate dielectric film structure includes a first insulating film including metal and oxygen and a second insulating film including metal, oxygen, and nitrogen; And And a control gate formed on the inter-gate dielectric layer structure. The method of claim 1, The second insulating film is a metal oxynitride film (MO _x N _y ), a metal silicate nitride film (MSi _x O _y N _z ) A nonvolatile memory integrated circuit device. The method of claim 1, And the first insulating film is aluminum oxide (Al _x O _y ), and the second insulating film is a hafnium silicate nitride film (HfSi _x O _y N _z ). The method of claim 1, The non-gate dielectric film structure of claim 1, wherein a second insulating film is stacked between the first insulating film. The method of claim 1, The non-gate dielectric film structure of claim 1, wherein the first insulating film is stacked between the second insulating films. Source and drain regions formed on the substrate; A channel region formed between the source and drain regions; A tunnel dielectric layer formed on the channel region, wherein the tunnel dielectric layer includes a first insulating layer including metal and oxygen and a second insulating layer including metal, oxygen, and nitrogen; A floating gate formed on the tunnel dielectric layer; An inter-gate dielectric film structure formed on the floating gate; And And a control gate formed on the inter-gate dielectric layer structure. The method of claim 6, The second insulating film is a metal oxynitride film (MO _x N _y ), a metal silicate nitride film (MSi _x O _y N _z ) A nonvolatile memory integrated circuit device. The method of claim 6, And the first insulating film is aluminum oxide (Al _x O _y ), and the second insulating film is a hafnium silicate nitride film (HfSi _x O _y N _z ). The method of claim 6, The tunnel dielectric layer of claim 1, wherein a second insulating layer is stacked between the first insulating layer. The method of claim 6, The tunnel dielectric layer of claim 1, wherein a first insulating layer is stacked between the second insulating layer.

Images