CN109473140A - A kind of circuit for eliminating flash memory programming interference - Google Patents
A kind of circuit for eliminating flash memory programming interference Download PDFInfo
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- CN109473140A CN109473140A CN201811198901.0A CN201811198901A CN109473140A CN 109473140 A CN109473140 A CN 109473140A CN 201811198901 A CN201811198901 A CN 201811198901A CN 109473140 A CN109473140 A CN 109473140A
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- burst pulse
- programming
- circuit
- nand gate
- flash memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
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Abstract
The invention discloses a kind of circuits of elimination flash memory programming interference, comprising: narrow-pulse generation circuit, for generating the positive burst pulse that a width is τ；Burst pulse output circuit generates the positive burst pulse and negative sense burst pulse that width is τ, i.e. programming precharge burst pulse PROGDR_P and programming license burst pulse PROGEN_P for the output according to the narrow-pulse generation circuit；Bit line charging circuit, for opening NMOS tube under the control for the positive burst pulse that the width of the programming precharge burst pulse PROGDR_P is τ through the invention, the programming interference of NORD cell can be eliminated for corresponding bit line quick pre-charging electricity to Vdd-Vt.
Description
Technical field
The present invention relates to storage unit programming technique fields, more particularly to a kind of circuit of elimination flash memory programming interference.
Background technique
Fig. 1 is the NORD Cell array schematic diagram of the prior art.Wherein storage array is M*N, each to show M storage
Unit, every a line have N number of storage unit, and for each storage unit there are two position is stored, corresponding bit line is respectively first bit line BL0 < j
>, the second bit line BL1<j>, j=0,1 ... ..., N-1, the first bit line BL0<j>and the second bit line BL1<j>of each column, which are spaced, to be connected
It connects, i.e. the storage list of the second bit line BL1, the 2nd row of the storage unit of the first bit line BL0 and the 1st row of the storage unit of the 0th row
Second bit line BL1 of the storage unit of first the first bit line BL0, the 3rd row ... it is connected to form first bit line BL0 < j of the column
>, and the storage list of the first bit line BL0 of the storage unit of the second bit line BL1 of the storage unit of the 0th row and the 1st row, the 2nd row
First bit line BL0 of the storage unit of first the second bit line BL1, the 3rd row ... it is connected to form second bit line BL1 < j of the column
>, the corresponding two control grids in two storage positions of each storage unit, i.e., the first control grid CG0<i>, the second control grid
CG1<i>, two storage position common word line WL<i>of each storage unit, i=0,1 ... ..., M-1, the storage unit of every a line
Share the first control grid CG0<i>, the second control grid CG1<i>and wordline WL<i>, the structure of each storage unit such as Fig. 2
It is shown.
Fig. 2 is a kind of double separate gate storage units (NORD Cell) structural schematic diagram in the prior art.As shown in Fig. 2, should
Double separate gate storage units, comprising: semiconductor P-type substrate (P_sub) 10 is arranged on N trap (N-Well) 11, N trap 11 thereon and has
There are spaced source region (S) 110 and drain region (D) 120 and channel region 130；Channel region 130 is located at source region
(S) between 110 and drain region (D) 120；First bit line BL0 and the second bit line BL1 is connected to source region 110 and leakage
Polar region domain 120；First floating gate 210 is set to 130 top of channel region in 110 upper right side of source region；Second floating gate 220, setting
Above the channel region 130 on 120 upper left side of drain region, the first floating gate 210 and the second floating gate 220 respectively constitute the first storage position
Unit and the second storage bit unit；First control gate 310 and the second control gate 320 are respectively arranged at the first floating gate 210 and second
220 top of floating gate, the first and second control grid lines are separately connected the first control gate 310 and the second control gate 320；Wordline area 40,
Above channel region 130 between the first floating gate 210 and the second floating gate 220, wordline WL connection wordline area 40, all isolation are used
Silica (between BL0, CG0, WL, CG1, BL1) ignore.
Source electrode injection mode (SourceSide is generally used when the prior art is to double separate gate flash memories programming shown in Fig. 2
Injection), it is assumed that left side stores position a (ellipse circled storage position) and is selected, and word line voltage WL=1.4V, the first control is arranged
Gate line voltages CG0=8.6V processed, the first bit line BL0 voltage BL0=5.25V, the second control gate line voltages CG1=5.25V, second
Bit line BL1 is programming actuation voltage Vdp.
Programming actuation voltage Vdp is automatically generated by programming pull-down current Idp, if choosing the selected bit of storage unit
Bit line program high pressure Vsp=5.25v apply up, under choosing the bit-line voltage of the unselected position of storage unit to program
Pull-up voltage Vdp gets on may can generate very much programming interference to the storage unit (cell) that same column is not chosen slowly.
For NORD cell, it is assumed that choose and store position a shown in Fig. 2, timing is as shown in figure 3, piece selects CEb to drag down, address
AMS-8(high position arrives low level) effectively, when programming mode PROG signal gets up, program current Idp starts to pull down, the second bit line BL1's
Voltage Vdp is pulled to 0, and PROG2 is waited to completely set up, and the corresponding first bit line BL0 of the IO for needing to program is applied programming high pressure
Vsp, when programming high pressure Vsp is applied up, the programming actuation voltage Vdp of the second bit line BL1 has an establishment process,
There may be programmings to interfere by the cell that same column is not chosen in this process
Summary of the invention
In order to overcome the deficiencies of the above existing technologies, purpose of the present invention is to provide a kind of interference of elimination flash memory programming
Circuit, with eliminate NORD cell programming interference.
In view of the above and other objects, the present invention proposes a kind of circuit of elimination flash memory programming interference, comprising:
Narrow-pulse generation circuit, for generating the positive burst pulse that a width is τ；
Burst pulse output circuit generates the narrow arteries and veins of forward direction that width is τ for the output according to the narrow-pulse generation circuit
Punching and negative sense burst pulse, i.e. programming precharge burst pulse PROGDR_P and programming license burst pulse PROGEN_P；
Bit line charging circuit, the positive burst pulse for being τ for the width in the programming precharge burst pulse PROGDR_P
Control under open NMOS tube with by corresponding bit line quick pre-charging electricity to Vdd-Vt, wherein Vdd is supply voltage, and Vt is
The threshold voltage of NMOS tube.
Preferably, the narrow-pulse generation circuit is realized using the first NAND gate and burst pulse generator.
Preferably, programming control signal PROG2 is connected to the input terminal and the first NAND gate of the burst pulse generator
One input terminal, the output end of the burst pulse generator are connected to another input terminal of the first NAND gate, the first NAND gate it is defeated
Outlet connects the burst pulse output circuit.
Preferably, the burst pulse output circuit includes the second NAND gate and several phase inverters.
Preferably, the burst pulse output circuit includes the second NAND gate and the first phase inverter, the second phase inverter.
Preferably, the output end of the narrow-pulse generation circuit is connected to the input terminal and the second NAND gate of the first phase inverter
An input terminal, programming enabling signal PROG is connected to another input terminal of the second NAND gate, and the output end of the second NAND gate connects
It is connected to the input terminal of the second phase inverter, the output end of the first phase inverter programs precharge burst pulse PROGDR_P, the second reverse phase
The output end of device programs license burst pulse PROGEN_P.
Preferably, the bit line charging circuit includes multiple NMOS tube NM2<7:0>.
Preferably, each NMOS tube grid meets the programming precharge burst pulse PROGDR_P, and drain electrode connects supply voltage, source electrode
Connect corresponding bit line IOD<7:0>.
Preferably, when programming, programming mode PROG is got higher, and programming enabling signal PROG, which is synchronized, to be drawn high, in programming high-voltage electricity
After lotus pump is established, programming control signal PROG2 is drawn high, and is connected to an input terminal of the first NAND gate, another way warp all the way
Another input terminal that the positive burst pulse that a width is τ is connected to first NAND gate is generated after the burst pulse generator,
First NAND gate output one starts from the negative sense burst pulse that the width of programming control signal PROG2 rising edge is τ, which is τ's
The output after the first inverter obtains the positive burst pulse that width is τ to negative sense burst pulse all the way, i.e. programming is pre-charged narrow arteries and veins
Rush PROGDR_P, the width be τ negative sense burst pulse another way with program enabling signal PROG be respectively connected to second with it is non-
The output of two input terminals of door, the second NAND gate obtains the negative sense burst pulse that width is τ using the second inverter, that is, compiles
Journey permits burst pulse PROGEN_P.
Preferably, within the time of high level that programming precharge burst pulse PROGDR_P width is τ, NMOS tube NM2 < 7:
0>conducting, IOD<7:0>are precharged to Vdd-Vt, and when programming precharge burst pulse PROGDR_P gets up, IOD<7:0>is compiled
Journey voltage Vdp is charged to Vdd-Vt in advance.
Compared with prior art, a kind of circuit for eliminating flash memory programming interference of the present invention is by utilizing narrow-pulse generation circuit
The positive burst pulse that a width is τ is generated, width is generated according to the output of narrow-pulse generation circuit using burst pulse output circuit
For the positive burst pulse and negative sense burst pulse of τ, i.e. programming precharge burst pulse PROGDR_P and programming license burst pulse PROGEN_
P, and the open position line charging circuit in the case where the width of programming precharge burst pulse PROGDR_P is the control of the positive burst pulse of τ
NMOS tube is to realize the purpose for eliminating flash memory programming interference for corresponding bit line quick pre-charging electricity to Vdd-Vt.
Detailed description of the invention
Fig. 1 is the NORD Cell array schematic diagram of the prior art；
Fig. 2 is a kind of double separate gate storage units (NORD Cell) structural schematic diagram in the prior art；
Fig. 3 is the timing diagram of the prior art；
Fig. 4 is a kind of circuit structure diagram for the circuit for eliminating flash memory programming interference of the present invention；
Fig. 5 is the timing diagram of the specific embodiment of the invention；
Fig. 6 is the analogous diagram of the specific embodiment of the invention.
Specific embodiment
Below by way of specific specific example and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand further advantage and effect of the invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Specific example implemented or applied, details in this specification can also be based on different perspectives and applications, without departing substantially from
Various modifications and change are carried out under spirit of the invention.
Fig. 4 is a kind of circuit structure diagram for the circuit for eliminating flash memory programming interference of the present invention.As shown in figure 4, the present invention one
Kind eliminates the circuit of flash memory programming interference, comprising: narrow-pulse generation circuit 10, burst pulse output circuit 20 and bit line charging circuit
30。
Wherein, narrow-pulse generation circuit 10 is made of the first NAND gate I83 and burst pulse generator I82, for generating one
Width is the positive burst pulse of τ；Burst pulse output circuit 20 is by the second NAND gate I85 and the first phase inverter I84, the second phase inverter
I86 composition generates the positive burst pulse and negative sense burst pulse that width is τ for the output according to narrow-pulse generation circuit 10, i.e.,
Programming precharge burst pulse PROGDR_P and programming license burst pulse PROGEN_P；Bit line charging circuit 30 is by multiple NMOS tubes
NM2<7:0>composition, for being opened under the control for the positive burst pulse that the width of programming precharge burst pulse PROGDR_P is τ
NMOS is with by corresponding bit line IOD<7:0>(BL1 of corresponding diagram 2) quick pre-charging electricity to Vdd-Vt, wherein Vdd is power supply electricity
Pressure, Vt are the threshold voltage of NMOS tube.
Specifically, programming control signal PROG2 is connected to the input terminal and the first NAND gate I83 of burst pulse generator I82
An input terminal, the output end of burst pulse generator I82 is connected to another input terminal of the first NAND gate I83, the first NAND gate
The output end of I83 is connected to the input terminal of the first phase inverter I84 and an input terminal of the second NAND gate I85, programs enabling signal
PROG is connected to another input terminal of the second NAND gate I85, and the output end of the second NAND gate I85 is connected to the second phase inverter I86
Input terminal, the output end of the first phase inverter I84 programs precharge burst pulse PROGDR_P, the output of the second phase inverter I86
End i.e. programming license burst pulse PROGEN_P, each NMOS tube grid of bit line charging circuit 30 connect the programming precharge burst pulse
PROGDR_P, drain electrode connect supply voltage, and source electrode connects corresponding bit line IOD<7:0>.
When programming, programming enabling signal PROG, which is synchronized, to be drawn high, after programming high voltage electricity pump is established, programming control signal
PROG2 is drawn high, and is connected to an input terminal of the first NAND gate I83 all the way, and another way generates after burst pulse generator I82
One width is that the positive burst pulse of τ is connected to another input terminal of the first NAND gate I83, and the first NAND gate I83 output one starts from
The width of programming control signal PROG2 rising edge is the negative sense burst pulse of τ, which is the negative sense burst pulse of τ all the way through first
Output obtains the positive burst pulse that width is τ, i.e. programming precharge burst pulse PROGDR_P, the width after phase inverter I84 reverse phase
Two input terminals of the second NAND gate I85 are respectively connected to for the another way and programming enabling signal PROG of the negative sense burst pulse of τ, the
The output of two NAND gate I85 obtains the negative sense burst pulse that width is τ using the second phase inverter I86 reverse phase, i.e. programming license is narrow
Pulse PROGEN_P.
As shown in figure 5, programming license burst pulse PROGEN_P has short in the moment that programming control signal PROG2 gets up
The decline (low level that width is τ) of time, programming precharge burst pulse PROGDR_P have (the width τ of short time
High level).
Fig. 6 is the analogous diagram of the specific embodiment of the invention.The height electricity for being τ in programming precharge burst pulse PROGDR_P width
In the flat time, NMOS tube NM2<7:0>conducting, IOD<7:0>(BL1 of corresponding diagram 2) is precharged to Vdd-Vt (Vt NMOS
The threshold voltage of pipe NM2<7:0>), the IOD<7:0>(BL1 of corresponding diagram 2) when programming precharge burst pulse PROGDR_P gets up
Namely Vdp has just been charged to Vdd-Vt (diagram simulated conditions: Vdd=1.5V, Vt=0.9V) in advance.Programming license burst pulse
PROGEN_P decline moment Idp is no longer pulled down, and the programming high pressure Vsp=5.25 of the bit line BL0 of storage unit selected in this way is built
Immediately, other end (the bit line BL1's of selected storage unit) voltage is higher than program voltage Vdp design threshold, will not generate
Programming interference.After equal programming enabling signal PROGDR_P goes down below, at this point, programming precharge burst pulse PROGDR_P has been drawn
Height, NMOS tube NM2<7:0>cut-off, the voltage of the bit line BL1 of selected storage unit are slowly pulled to program voltage Vdp design
Threshold value.
In conclusion a kind of circuit for eliminating flash memory programming interference of the present invention is by generating one using narrow-pulse generation circuit
Width be τ positive burst pulse, using burst pulse output circuit according to the output of narrow-pulse generation circuit generate width for τ just
To burst pulse and negative sense burst pulse, i.e. programming precharge burst pulse PROGDR_P and programming license burst pulse PROGEN_P, and
Programming precharge burst pulse PROGDR_P width be τ positive burst pulse control under open position line charging circuit NMOS with
By corresponding bit line quick pre-charging electricity to Vdd-Vt, the purpose for eliminating flash memory programming interference is realized.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.Any
Without departing from the spirit and scope of the present invention, modifications and changes are made to the above embodiments by field technical staff.Therefore,
The scope of the present invention, should be as listed in the claims.
Claims (10)
1. a kind of circuit for eliminating flash memory programming interference, comprising:
Narrow-pulse generation circuit, for generating the positive burst pulse that a width is τ；
Burst pulse output circuit, for according to the narrow-pulse generation circuit output generate width be τ positive burst pulse and
Negative sense burst pulse, i.e. programming precharge burst pulse PROGDR_P and programming license burst pulse PROGEN_P；
Bit line charging circuit, the control for the positive burst pulse that the width in the programming precharge burst pulse PROGDR_P is τ
System is lower to open NMOS tube with by corresponding bit line quick pre-charging electricity to Vdd-Vt, wherein Vdd is supply voltage, and Vt is NMOS tube
Threshold voltage.
2. a kind of circuit for eliminating flash memory programming interference as described in claim 1, it is characterised in that: the burst pulse generates electricity
It is realized using the first NAND gate and burst pulse generator on road.
3. a kind of circuit for eliminating flash memory programming interference as claimed in claim 2, it is characterised in that: programming control signal
PROG2 is connected to the input terminal of the burst pulse generator and an input terminal of the first NAND gate, the burst pulse generator
Output end is connected to another input terminal of the first NAND gate, and the output end of the first NAND gate connects the burst pulse output circuit.
4. a kind of circuit for eliminating flash memory programming interference as claimed in claim 2, it is characterised in that: the burst pulse output electricity
Road includes the second NAND gate and several phase inverters.
5. a kind of circuit for eliminating flash memory programming interference as claimed in claim 4, it is characterised in that: the burst pulse output electricity
Road includes the second NAND gate and the first phase inverter, the second phase inverter.
6. a kind of circuit for eliminating flash memory programming interference as claimed in claim 5, it is characterised in that: the burst pulse generates electricity
The output end on road is connected to the input terminal of the first phase inverter and an input terminal of the second NAND gate, programs enabling signal PROG connection
To another input terminal of the second NAND gate, the output end of the second NAND gate is connected to the input terminal of the second phase inverter, the first reverse phase
The output end of device programs precharge burst pulse PROGDR_P, and the output end of the second phase inverter programs license burst pulse
PROGEN_P。
7. a kind of circuit for eliminating flash memory programming interference as claimed in claim 5, it is characterised in that: the bit line charging circuit
Including multiple NMOS tube NM2<7:0>.
8. a kind of circuit for eliminating flash memory programming interference as claimed in claim 7, it is characterised in that: each NMOS tube grid meets institute
Programming precharge burst pulse PROGDR_P is stated, drain electrode connects supply voltage, and source electrode connects corresponding bit line IOD<7:0>.
9. a kind of circuit for eliminating flash memory programming interference as claimed in claim 8, it is characterised in that: when programming, programming license
Signal PROG, which is synchronized, to be drawn high, and after programming high voltage electricity pump is established, programming control signal PROG2 is drawn high, and is connected to all the way
One input terminal of one NAND gate, another way generate the positive burst pulse that a width is τ after the burst pulse generator and connect
To another input terminal of first NAND gate, the first NAND gate output one starts from the width of programming control signal PROG2 rising edge
Degree is the negative sense burst pulse of τ, and it is τ that the negative sense burst pulse which is τ, which exports after the first inverter obtain width all the way,
Positive burst pulse, i.e. programming precharge burst pulse PROGDR_P, which is that the another way of negative sense burst pulse of τ is permitted with programming
Signal PROG is respectively connected to two input terminals of the second NAND gate, and the output of the second NAND gate is using the second inverter
Obtain the negative sense burst pulse that width is τ, i.e. programming license burst pulse PROGEN_P.
10. a kind of circuit for eliminating flash memory programming interference as claimed in claim 9, it is characterised in that: narrow in programming precharge
Pulse PROGDR_P width is in the time of the high level of τ, and NMOS tube NM2<7:0>conducting, IOD<7:0>is precharged to Vdd-
Vt, when programming precharge burst pulse PROGDR_P gets up, IOD<7:0>i.e. program voltage Vdp has been charged to Vdd-Vt in advance.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811198901.0A CN109473140B (en) | 2018-10-15 | 2018-10-15 | Circuit for eliminating flash memory programming interference |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811198901.0A CN109473140B (en) | 2018-10-15 | 2018-10-15 | Circuit for eliminating flash memory programming interference |
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| CN109473140B CN109473140B (en) | 2020-11-20 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101034589A (en) * | 2006-03-08 | 2007-09-12 | 旺宏电子股份有限公司 | Methods and apparatus for a non-volatile memory device with reduced program disturb |
| US20090290429A1 (en) * | 2008-05-23 | 2009-11-26 | Yingda Dong | Enhanced bit-line pre-charge scheme for increasing channel boosting in non-volatile storage |
| US20100080064A1 (en) * | 2008-09-30 | 2010-04-01 | Ercole Rosario Di Iorio | Bit line bias for programming a memory device |
| US20150063020A1 (en) * | 2013-09-03 | 2015-03-05 | Micron Technology, Inc. | Semiconductor device |
| CN107045893A (en) * | 2017-04-14 | 2017-08-15 | 上海华虹宏力半导体制造有限公司 | A kind of circuit for eliminating flash memory programming interference |
-
2018
- 2018-10-15 CN CN201811198901.0A patent/CN109473140B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101034589A (en) * | 2006-03-08 | 2007-09-12 | 旺宏电子股份有限公司 | Methods and apparatus for a non-volatile memory device with reduced program disturb |
| US20090290429A1 (en) * | 2008-05-23 | 2009-11-26 | Yingda Dong | Enhanced bit-line pre-charge scheme for increasing channel boosting in non-volatile storage |
| US20100080064A1 (en) * | 2008-09-30 | 2010-04-01 | Ercole Rosario Di Iorio | Bit line bias for programming a memory device |
| US20150063020A1 (en) * | 2013-09-03 | 2015-03-05 | Micron Technology, Inc. | Semiconductor device |
| CN107045893A (en) * | 2017-04-14 | 2017-08-15 | 上海华虹宏力半导体制造有限公司 | A kind of circuit for eliminating flash memory programming interference |
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