CN109473140B - Circuit for eliminating flash memory programming interference - Google Patents
Circuit for eliminating flash memory programming interference Download PDFInfo
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- CN109473140B CN109473140B CN201811198901.0A CN201811198901A CN109473140B CN 109473140 B CN109473140 B CN 109473140B CN 201811198901 A CN201811198901 A CN 201811198901A CN 109473140 B CN109473140 B CN 109473140B
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
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Abstract
The invention discloses a circuit for eliminating flash memory programming interference, which comprises: the narrow pulse generating circuit is used for generating a forward narrow pulse with the width tau; a narrow pulse output circuit for generating a positive-going narrow pulse and a negative-going narrow pulse of width τ, i.e., a program precharge narrow pulse PROGDR _ P and a program permission narrow pulse PROGEN _ P, according to an output of the narrow pulse generating circuit; the bit line charging circuit is used for opening the NMOS tube under the control of the positive narrow pulse with the width tau of the programming pre-charging narrow pulse PROGDR _ P so as to quickly pre-charge the corresponding bit line to Vdd-Vt.
Description
Technical Field
The present invention relates to the field of memory cell programming technologies, and in particular, to a circuit for eliminating flash memory programming interference.
Background
FIG. 1 is a schematic diagram of a NORD Cell array of the prior art. The memory array is M × N, each column has M memory cells, each row has N memory cells, each memory cell has two memory bits, the corresponding bit lines are respectively a first bit line BL0< j >, a second bit line BL1< j >, j is 0,1, … …, N-1, the first bit line BL0< j > and the second bit line BL1< j > of each column are connected at intervals, namely, the first bit line BL0 of the memory cell of the 0 th row is connected with the second bit line BL1 of the memory cell of the 1 st row, the first bit line BL0 of the memory cell of the 2 nd row, the second bit line BL1, … … of the memory cell of the 3 rd row to form the first bit line BL0< j > of the column, and the second bit line BL1 of the memory cell of the 0 th row is connected with the first bit line BL 36 of the memory cell of the 1 st row, the second bit line BL 8937 of the memory cell of the 2 nd row, the second bit line BL 9638 of the memory cell 369638 of the memory cell of the 0 th row to form the second bit line 3638, 3638 of the memory cell 3638, 3638 of the column, 3638, and the bit line 36, the two storage bits of each memory cell correspond to two control gates, namely a first control gate CG0< i >, a second control gate CG1< i >, the two storage bits of each memory cell share a word line WL < i >, i is 0,1, … …, M-1, the memory cells of each row share a first control gate CG0< i >, a second control gate CG1< i > and a word line WL < i >, and the structure of each memory cell is shown in FIG. 2.
Fig. 2 is a schematic diagram of a dual split gate memory Cell (NORD Cell) in the prior art. As shown in fig. 2, the dual split gate memory cell includes: a semiconductor P-type substrate (P _ sub)10 on which an N-Well (N-Well)11 is disposed, the N-Well 11 having spaced apart source (S) and drain (D) regions 110 and 120 and a channel region 130; a channel region 130 between the source region (S)110 and the drain region (D) 120; a first bit line BL0 and a second bit line BL1 connected to the source region 110 and the drain region 120, respectively; a first floating gate 210 disposed over the channel region 130 above and to the right of the source region 110; a second floating gate 220 disposed above the channel region 130 above and to the left of the drain region 120, the first floating gate 210 and the second floating gate 220 constituting a first memory bit cell and a second memory bit cell, respectively; a first control gate 310 and a second control gate 320, which are respectively disposed above the first floating gate 210 and the second floating gate 220, and the first and second control gate lines are respectively connected to the first control gate 310 and the second control gate 320; the word line region 40 is located above the channel region 130 between the first floating gate 210 and the second floating gate 220, the word line WL is connected to the word line region 40, and all the isolation silicon oxides (between BL0, CG0, WL, CG1 and BL1) are omitted.
In the prior art, a source injection (source injection) method is generally used for programming the dual split gate flash memory shown in fig. 2, assuming that a left storage bit a (storage bit at an oval circle) is selected, a word line voltage WL is set to 1.4V, a first control gate line voltage CG0 is set to 8.6V, a first bit line BL0 voltage BL0 is set to 5.25V, a second control gate line voltage CG1 is set to 5.25V, and a second bit line BL1 is a programming pull-down voltage Vdp.
The program pull-down voltage Vdp is automatically generated by the program pull-down current Idp, and if the bit line program high voltage Vsp of the selected bit of the selected memory cell is equal to 5.25v and is applied, the bit line voltage of the unselected bit of the selected memory cell, i.e., the program pull-down voltage Vdp, is too slowly removed, which may cause program disturb to the non-selected memory cells (cells) in the same column.
For NORD cell, assuming bit a of FIG. 2 is selected, the timing sequence is as shown in FIG. 3, the chip select CEb is pulled low, and address AMS-8(high to low) active, when the program mode PROG signal is asserted, the program current Idp starts to be pulled down, the voltage Vdp of the second bit line BL1 is pulled to 0, and when the PROG2 is fully established, the first bit line BL0 corresponding to the IO to be programmed is applied with the program high voltage Vsp, and when the program high voltage Vsp is applied, the program pull-down voltage Vdp of the second bit line BL1 has a establishing process in which the cells not selected in the same column may generate program disturb
Disclosure of Invention
To overcome the above-mentioned deficiencies of the prior art, the present invention provides a circuit for eliminating program disturb of flash memory, so as to eliminate program disturb of NORD cell.
To achieve the above and other objects, the present invention provides a circuit for eliminating flash program disturb, comprising:
the narrow pulse generating circuit is used for generating a forward narrow pulse with the width tau;
a narrow pulse output circuit for generating a positive-going narrow pulse and a negative-going narrow pulse of width τ, i.e., a program precharge narrow pulse PROGDR _ P and a program permission narrow pulse PROGEN _ P, according to an output of the narrow pulse generating circuit;
and a bit line charging circuit for turning on the NMOS transistor under the control of the positive narrow pulse with the width tau of the program precharge narrow pulse PROGDR _ P to quickly precharge the corresponding bit line to Vdd-Vt, wherein Vdd is a power supply voltage, and Vt is a threshold voltage of the NMOS transistor.
Preferably, the narrow pulse generating circuit is implemented by using a first nand gate and a narrow pulse generator.
Preferably, the programming control signal PROG2 is connected to an input terminal of the narrow pulse generator and an input terminal of the first nand gate, an output terminal of the narrow pulse generator is connected to another input terminal of the first nand gate, and an output terminal of the first nand gate is connected to the narrow pulse output circuit.
Preferably, the narrow pulse output circuit comprises a second nand gate and a plurality of inverters.
Preferably, the narrow pulse output circuit includes a second nand gate, and a first inverter and a second inverter.
Preferably, the output terminal of the narrow pulse generating circuit is connected to the input terminal of the first inverter and an input terminal of the second nand gate, the program enable signal PROG is connected to another input terminal of the second nand gate, the output terminal of the second nand gate is connected to the input terminal of the second inverter, the output terminal of the first inverter is the program precharge narrow pulse PROGDR _ P, and the output terminal of the second inverter is the program enable narrow pulse PROGEN _ P.
Preferably, the bit line charging circuit includes a plurality of NMOS transistors NM2< 7: 0 >.
Preferably, the gate of each NMOS transistor is connected to the program precharge narrow pulse proddr _ P, the drain is connected to the power voltage, and the source is connected to the corresponding bit line IOD < 7: 0 >.
Preferably, during programming, the programming mode PROG goes high, the programming permission signal PROG is pulled high synchronously, after the programming high-voltage charge pump is established, the programming control signal PROG2 is pulled high, one path of the programming control signal PROG is connected to one input end of the first nand gate, the other path of the programming control signal PROG is connected to the other input end of the first nand gate by the narrow pulse generator to generate a positive narrow pulse with width τ, the first nand gate outputs a negative narrow pulse with width τ starting from the rising edge of the programming control signal PROG2, one path of the negative narrow pulse with width τ is inverted by the first inverter to output a positive narrow pulse with width τ, that is, a programming pre-charging narrow pulse PROGDR _ P, the other path of the negative narrow pulse with width τ and the programming permission signal PROG are respectively connected to two input ends of the second nand gate, the output of the second nand gate is inverted by the second inverter to obtain a negative narrow pulse with width τ, i.e., the program permission narrow pulse PROGEN _ P.
Preferably, during the time when the program precharge narrow pulse proddr _ P has a high level with the width τ, the NMOS transistor NM2< 7: 0> on, IOD < 7: 0> is precharged to Vdd-Vt, IOD <7 when the program precharge narrow pulse PROGDR _ P is up: 0> i.e., the programming voltage Vdp has been precharged to Vdd-Vt.
Compared with the prior art, the circuit for eliminating the programming interference of the flash memory generates a positive narrow pulse with the width tau by using the narrow pulse generating circuit, generates the positive narrow pulse and the negative narrow pulse with the width tau, namely the programming pre-charging narrow pulse PROGDR _ P and the programming permission narrow pulse PROGEN _ P, according to the output of the narrow pulse generating circuit by using the narrow pulse output circuit, and opens the NMOS tube of the bit line charging circuit under the control of the positive narrow pulse with the width tau of the programming pre-charging narrow pulse PROGDR _ P to quickly pre-charge the corresponding bit line to Vdd-Vt, thereby realizing the aim of eliminating the programming interference of the flash memory.
Drawings
FIG. 1 is a schematic diagram of a NORD Cell array of the prior art;
FIG. 2 is a schematic diagram of a prior art double split gate memory Cell (NORD Cell);
FIG. 3 is a timing diagram of the prior art;
FIG. 4 is a circuit diagram of a circuit for eliminating program disturb in a flash memory according to the present invention;
FIG. 5 is a timing diagram of an embodiment of the present invention;
FIG. 6 is a simulation diagram of an embodiment of the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
FIG. 4 is a circuit diagram of a circuit for eliminating program disturb in a flash memory according to the present invention. As shown in fig. 4, a circuit for eliminating flash program disturb of the present invention includes: a narrow pulse generating circuit 10, a narrow pulse output circuit 20, and a bit line charging circuit 30.
The narrow pulse generating circuit 10 is composed of a first nand gate I83 and a narrow pulse generator I82, and is used for generating a forward narrow pulse with width τ; the narrow pulse output circuit 20 is composed of a second nand gate I85, a first inverter I84, and a second inverter I86, and is configured to generate a positive-going narrow pulse and a negative-going narrow pulse with a width τ, i.e., a program precharge narrow pulse proddr _ P and a program permission narrow pulse PROGEN _ P, according to the output of the narrow pulse generating circuit 10; the bit line charging circuit 30 is formed by a plurality of NMOS transistors NM2< 7: 0> composition for turning on the NMOS under the control of a forward narrow pulse of width τ of the program precharge narrow pulse PROGDR _ P to connect the corresponding bit line IOD < 7: 0> (corresponding to BL1 of FIG. 2) is quickly precharged to Vdd-Vt where Vdd is the supply voltage and Vt is the threshold voltage of the NMOS transistor.
Specifically, the program control signal PROG2 is connected to the input terminal of the narrow pulse generator I82 and an input terminal of the first nand gate I83, the output terminal of the narrow pulse generator I82 is connected to the other input terminal of the first nand gate I83, the output terminal of the first nand gate I83 is connected to the input terminal of the first inverter I84 and an input terminal of the second nand gate I85, the program permission signal PROG is connected to the other input terminal of the second nand gate I85, the output terminal of the second nand gate I85 is connected to the input terminal of the second inverter I86, the output terminal of the first inverter I84 is the program precharge narrow pulse PROGDR _ P, the output terminal of the second inverter I86 is the program permission narrow pulse PROGEN _ P, each NMOS transistor gate of the bit line charging circuit 30 is connected to the program precharge narrow pulse PROGDR _ P, the drain is connected to the source voltage, and the source is connected to the corresponding bit line IOD < 7: 0 >.
During programming, the programming permission signal PROG is synchronously pulled up, after the programming high-voltage charge pump is established, the programming control signal PROG2 is pulled up, one path of the narrow pulse generator is connected to one input end of the first nand gate I83, the other path of the narrow pulse generator generates a positive narrow pulse with width tau after passing through the narrow pulse generator I82 and is connected to the other input end of the first nand gate I83, the first nand gate I83 outputs a negative narrow pulse with width tau starting from the rising edge of the program control signal PROG2, one path of the negative narrow pulse with the width tau is inverted by a first inverter I84 and then output to obtain a positive narrow pulse with the width tau, namely, the programming precharge narrow pulse PROGDR _ P, the other path of the negative-going narrow pulse with the width τ and the programming permission signal PROG are respectively connected to two input terminals of the second nand gate I85, and the output of the second nand gate I85 is inverted by the second inverter I86 to obtain the negative-going narrow pulse with the width τ, namely, the programming permission narrow pulse PROGEN _ P.
As shown in fig. 5, at the instant when the program control signal PROG2 is turned on, the program permission narrow pulse PROGEN _ P is turned off for a short time (low level with width τ), and the program precharge narrow pulse PROGDR _ P is turned on for a short time (high level with width τ).
FIG. 6 is a simulation diagram of an embodiment of the present invention. During the time of programming the precharge narrow pulse proddr _ P with the high level of width τ, the NMOS transistor NM2< 7: 0> on, IOD < 7: 0> (corresponding to BL1 of FIG. 2) is precharged to Vdd-Vt (Vt is the threshold voltage of NMOS transistor NM2< 7: 0 >), IOD < 7: 0> (corresponding to BL1 of fig. 2), i.e., Vdp, has been precharged to Vdd-Vt (simulation conditions: Vdd ═ 1.5V, Vt ═ 0.9V are shown). The falling time Idp of the program enable narrow pulse PROGEN _ P is not pulled down any more, so that when the programming high voltage Vsp of the bit line BL0 of the selected memory cell is set to 5.25, the voltage at the other end (of the bit line BL1 of the selected memory cell) is higher than the programming voltage Vdp design threshold, and no program disturb occurs. The latter, and so on, after the program enable signal proddr _ P is asserted, at which time the program precharge narrow pulse proddr _ P has been pulled high, the NMOS transistor NM2< 7: 0> is off and the voltage on bit line BL1 of the selected memory cell is slowly pulled to the programming voltage Vdp by the design threshold.
In summary, the circuit for eliminating flash program disturb of the present invention generates a positive narrow pulse with a width τ by using the narrow pulse generating circuit, generates a positive narrow pulse and a negative narrow pulse with a width τ, i.e., the program precharge narrow pulse proddr _ P and the program enable narrow pulse PROGEN _ P, according to the output of the narrow pulse generating circuit by using the narrow pulse outputting circuit, and turns on the NMOS of the bit line charging circuit under the control of the positive narrow pulse with the width τ of the program precharge narrow pulse proddr _ P to quickly precharge the corresponding bit line to Vdd-Vt, thereby achieving the purpose of eliminating flash program disturb.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (6)
1. A circuit for eliminating program disturb in a dual split gate flash memory, comprising:
the narrow pulse generating circuit is used for generating a forward narrow pulse with the width tau;
a narrow pulse output circuit for generating a positive-going narrow pulse and a negative-going narrow pulse of width τ, i.e., a program precharge narrow pulse PROGDR _ P and a program permission narrow pulse PROGEN _ P, according to an output of the narrow pulse generating circuit;
a bit line charging circuit for turning on the NMOS transistor under the control of a positive-going narrow pulse with a width τ of the program precharge narrow pulse proddr _ P to quickly precharge the corresponding bit line to Vdd-Vt, where Vdd is a power supply voltage and Vt is a threshold voltage of the NMOS transistor, the narrow pulse generating circuit being implemented with a first nand gate and a narrow pulse generator;
the narrow pulse output circuit comprises a second NAND gate, a first inverter and a second inverter, wherein the output end of the narrow pulse generating circuit is connected to the input end of the first inverter and one input end of the second NAND gate, a programming permission signal PROG is connected to the other input end of the second NAND gate, the output end of the second NAND gate is connected to the input end of the second inverter, the output end of the first inverter is a programming pre-charging narrow pulse PROGDR _ P, and the output end of the second inverter is a programming permission narrow pulse PROGEN _ P.
2. The circuit of claim 1, wherein the circuit for eliminating program disturb of dual split gate flash memory comprises: the programming control signal PROG2 is connected to the input terminal of the narrow pulse generator and an input terminal of the first nand gate, the output terminal of the narrow pulse generator is connected to the other input terminal of the first nand gate, and the output terminal of the first nand gate is connected to the narrow pulse output circuit.
3. The circuit of claim 1, wherein the circuit for eliminating program disturb of dual split gate flash memory comprises: the bit line charging circuit includes a plurality of NMOS transistors NM2< 7: 0 >.
4. The circuit of claim 3, wherein the circuit for eliminating program disturb of dual split gate flash memory comprises: the grid electrode of each NMOS tube is connected with the programming pre-charging narrow pulse PROGDR _ P, the drain electrode is connected with the power voltage, and the source electrode is connected with the corresponding bit line IOD < 7: 0 >.
5. The circuit of claim 4, wherein the circuit for eliminating program disturb of the dual split gate flash memory comprises: during programming, the programming permission signal PROG is synchronously pulled up, after the programming high-voltage charge pump is established, the programming control signal PROG2 is pulled up, one path of the positive narrow pulse is connected to one input end of the first nand gate, the other path of the positive narrow pulse is generated by the narrow pulse generator and is connected to the other input end of the first nand gate, the first nand gate outputs a negative narrow pulse with the width tau starting from the rising edge of the programming control signal PROG2, one path of the negative narrow pulse with the width tau is inverted by the first inverter and then output to obtain a positive narrow pulse with the width tau, the other path of the negative narrow pulse with the width tau and the programming permission signal PROG are respectively connected to two input ends of the second nand gate, and the output of the second nand gate is inverted by the second inverter to obtain the negative narrow pulse with the width tau, namely the programming permission narrow pulse PROGEN _ P.
6. The circuit of claim 5, wherein the circuit for eliminating program disturb of dual split gate flash memory comprises: during the time of programming the precharge narrow pulse proddr _ P with the high level of width τ, the NMOS transistor NM2< 7: 0> on, IOD < 7: 0> is precharged to Vdd-Vt, IOD <7 when the program precharge narrow pulse PROGDR _ P is up: 0> i.e., the programming voltage Vdp has been precharged to Vdd-Vt.
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| US7313018B2 (en) * | 2006-03-08 | 2007-12-25 | Macronix International Co., Ltd. | Methods and apparatus for a non-volatile memory device with reduced program disturb |
| US7719902B2 (en) * | 2008-05-23 | 2010-05-18 | Sandisk Corporation | Enhanced bit-line pre-charge scheme for increasing channel boosting in non-volatile storage |
| US20100080064A1 (en) * | 2008-09-30 | 2010-04-01 | Ercole Rosario Di Iorio | Bit line bias for programming a memory device |
| JP2015049918A (en) * | 2013-09-03 | 2015-03-16 | マイクロン テクノロジー， インク． | Write pulse width setting method, data write method, and semiconductor device |
| CN107045893B (en) * | 2017-04-14 | 2020-06-16 | 上海华虹宏力半导体制造有限公司 | Circuit for eliminating flash memory programming interference |
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