CN109412607A - Interpretation method and device - Google Patents
Interpretation method and device Download PDFInfo
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- CN109412607A CN109412607A CN201710700352.1A CN201710700352A CN109412607A CN 109412607 A CN109412607 A CN 109412607A CN 201710700352 A CN201710700352 A CN 201710700352A CN 109412607 A CN109412607 A CN 109412607A
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- decoding
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
- H04L1/0063—Single parity check
Abstract
Present disclose provides a kind of interpretation method and devices, belong to decoding technique field.Method include: the bit currently decoded be PC- freeze bit, and in any bar decoding path bit decoding result not over verification when, it is determined that at least one targeted information bits decoded in decoding path；Since first aim information bit, overturn the decoding result of targeted information bits, and targeted information bits are return back in decoding path and are decoded again, every overturning and rollback decoding once then compare the extra heavy new obtained decoding result that decodes and are verified, when not over verification, continue decoding that next targeted information bits are overturn and retracted；When the decoding result that at least one targeted information bits was overturn and retracted decoding and bit decodes again is not over verification, then increases the quantity of decoding path and continue to decode.The disclosure adjusts the quantity of decoding path during decoding, substantially reduces decoding delay.
Description
Technical field
This disclosure relates to decoding technique field, in particular to a kind of interpretation method and device.
Background technique
(Polar) code that polarizes is theoretically to be proved to be the reachable coding mode of channel capacity, and Polar code can pass through company
Continuous list (Successive Cancellation List, SCL) decoding algorithm of eliminating is decoded.The quantity of decoding path
(LIST quantity) is the important parameter of SCL decoding algorithm, and the decoding performance of SCL decoding algorithm is mentioned with the increase of LIST quantity
It rises, however, the promotion of LIST quantity will lead to the increase of decoding complexity.Therefore, it during actually decoding, needs to adjust
LIST quantity is decoded, to obtain compromise between complexity and performance.
Currently, being decoded using following scheme adjustment LIST quantity:
1. the upper limit L of a LIST quantity L is arrangedmax；
2. initializing L=1；
3. being decoded using SCL decoding algorithm, to path metric (Path Metric, PM) value maximum after the completion of decoding
L decoding path carry out cyclic redundancy check (Cyclic Redundancy Check, CRC)；
4. if it is minimum to export PM value at least one decoding path there is at least one decoding path by CRC check
Decoding path path hard values (bit sequence), decoding terminates；Otherwise 5 are executed；
5. L is increased twice, if L≤Lmax, then 3 are executed；Otherwise the smallest decoding road of PM value in all decoding paths is exported
The path hard values of diameter, decoding terminate.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
Above scheme only just can be carried out CRC check after the completion of primary decoding, and determine whether to adjust according to check results
Whole LIST quantity causes the adjustment period of LIST quantity longer, needs the long period can be only achieved in this way and meets estimated performance
LIST quantity, decoding delay are long.
Summary of the invention
In order to solve problems in the prior art, the embodiment of the present disclosure provides a kind of interpretation method and device.The technology
Scheme is as follows:
In a first aspect, providing a kind of interpretation method, which comprises
It is that even-odd check (Parity-Check, PC)-freezes bit, and any bar decoding path in the bit currently decoded
Described in bit decoding result not over verification when, it is determined that decoded in the decoding path at least one target letter
Bit is ceased, the targeted information bits are the information bit that designated bit position is differed with the bit position, the designated bit
Position is the integral multiple of the shift cycle of circulating register；
Since the first aim information bit at least one described targeted information bits, targeted information bits are overturn
Decoding as a result, and returning back to the targeted information bits in the decoding path and re-starting decoding, every overturning and rollback
Decoding is primary then to be verified the bit by the decoding result decoded again, when not over verification, is continued
Overturn and retracted to next targeted information bits decoding；
When at least one described targeted information bits are overturn and retracted decoding and the bit by again decoding
Decoding result not over verification when, then increase the quantity of decoding path and continue to decode.
Wherein, it is the bit for the check bit bit error rate that PC-, which freezes bit, for example, when PC- freezes the decoding knot of bit
Fruit shows bit error rate height not over verification, if showing that the bit error rate is low by verification.
The method that the embodiment of the present disclosure provides, during decoding, if the bit currently decoded is that PC- freezes bit,
And the PC- is when freezing the decoding result of bit not over verification, by the information for influencing the PC- and freezing bit check result
Bit is overturn and is retracted one by one decoding, freezes the decoding knot that bit decodes again to the PC- after the decoding that retracts every time
Fruit is verified, if verification is all not over illustrating that current error rate is higher, at this point, electronic equipment is adjustable every time
The quantity of decoding path reduces the bit error rate to improve decoding performance, improves the verification percent of pass that PC- freezes bit.Above-mentioned technology
Scheme is compared with needing to be adjusted the quantity of decoding path after the completion of whole bit decodings in the prior art, this public affairs
The adjustment period for opening middle decoding path quantity is shorter, needs the short period so i.e. and can reach the decoding path for meeting estimated performance
Quantity, substantially reduce decoding delay.
In the first possible implementation of first aspect, decoded in the determination decoding path at least one
A targeted information bits include:
Determine that the previous PC- of the bit and the bit freezes multiple information bits between bit；
The information bit in the multiple information bit, meeting specified relationship formula is retrieved as at least one target letter
Cease bit.
Current PC-is freezed bit and previous PC- freezes satisfaction between bit and refers to by the method that the embodiment of the present disclosure provides
The information bit for determining relational expression is retrieved as freezing relevant at least one targeted information bits of bit to current PC-, provides one
Kind obtains the mode of targeted information bits.
In second of possible implementation of first aspect, the quantity for increasing decoding path simultaneously continues to decode
Include:
The quantity of current decoding path is adjusted to the smaller value in first path quantity and the second number of paths, described
One number of paths is twice of the quantity of the current decoding path, and second number of paths is pre-set number of paths
Maximum value；
All decoding paths are return back to the first aim information bit weight at least one described targeted information bits
New decoding.
The method that the embodiment of the present disclosure provides shows that the bit error rate is higher when the verification percent of pass that PC- freezes bit is low,
Decoding performance is poor, at this time by tuning up the quantity of decoding path, so that the quantity of decoding path levels off to maximum value, Ke Yibao
Demonstrate,prove decoding performance.
In the third possible implementation of first aspect, the method also includes:
After every overturning and primary rollback decoding, when the decoding result that the bit decodes again passes through verification, knot
Beam overturning and rollback decoding process；
Using the overturning result of the targeted information bits of this overturning translating as the targeted information bits of this overturning
Code result.
Wherein, overturning result refers to overturn the existing decoding result of the targeted information bits after obtain as a result, such as the mesh
Marking the existing decoding result of information bit is 0, then overturning result is 1.
The method that the embodiment of the present disclosure provides, if to some target information at least one targeted information bits
Bit is overturn and is retracted after decoding, so that the PC- freezes the decoding result that bit decodes again and passes through verification, then electronics is set
It is standby to terminate overturning and rollback decoding process, and using overturning result as the decoding of targeted information bits as a result, providing one
Kind terminates the opportunity of overturning and rollback decoding process.
In the 4th kind of possible implementation of first aspect, the method also includes:
When the decoding result of the bit described in all decoding paths passes through verification, by the quantity tune of current decoding path
Whole the larger value in third number of paths and the 4th number of paths, and continue to decode, the third number of paths is institute
The half of the quantity of current decoding path is stated, the 4th number of paths is pre-set number of paths minimum value.
The method that the embodiment of the present disclosure provides shows that the bit error rate is lower when the verification percent of pass that PC- freezes bit is high,
At this time by turning the quantity of decoding path down, so that the quantity of decoding path can reduce decoding complexity close to minimum value, protect
Demonstrate,prove decoding speed.
Second aspect, provides a kind of code translator, and described device includes multiple functional modules, the multiple functional module
For executing interpretation method provided by above-mentioned first aspect and its any possible implementation.
The third aspect, provides a kind of electronic equipment, and the electronic equipment includes processor and memory, the memory
In be stored at least one instruction, at least a Duan Chengxu, code set or instruction set, at least one instruction, described at least one
Duan Chengxu, the code set or instruction set are loaded by the processor and are executed to realize in above-mentioned first aspect or first aspect
Interpretation method provided by any possibility implementation.
Fourth aspect provides a kind of computer readable storage medium, is stored in the computer readable storage medium
At least one instruction, at least a Duan Chengxu, code set or instruction set, at least one instruction, an at least Duan Chengxu, institute
Code set or instruction set is stated to be loaded by processor and executed to realize that any possibility is in fact in above-mentioned first aspect or first aspect
Interpretation method provided by existing mode.
Detailed description of the invention
Fig. 1 is the structural schematic diagram for a kind of electronic equipment 100 that the embodiment of the present disclosure provides.
Fig. 2 is a kind of flow chart for interpretation method that the embodiment of the present disclosure provides.
Fig. 3 is a kind of Path selection schematic diagram for SCL decoding algorithm that the embodiment of the present disclosure provides.
Fig. 4 is a kind of structural schematic diagram for code translator that the embodiment of the present disclosure provides.
Specific embodiment
To keep the purposes, technical schemes and advantages of the disclosure clearer, below in conjunction with attached drawing to disclosure embodiment party
Formula is described in further detail.
In the method that the embodiment of the present disclosure provides, the executing subject of each step can be electronic equipment, such as communication system
The receiving end of middle information.For example, the electronic equipment can be base station, mobile terminal or other equipment with decoding function.For
Convenient for description, in the following embodiments, only it is illustrated so that the executing subject of each step is electronic equipment as an example.
Transmitting terminal in communication system can carry out polarization code volume to the information when needing to send information to electronic equipment
Code generates bit sequence, which is made of multiple bits, and the value of each bit is 0 or 1.Bit can be there are three types of class
Type, such as information bit freeze bit and PC- freezes bit, wherein information bit is the bit with information content, freezes bit
Freezing bit with PC- is the bit without information content.
There are multiple channels between transmitting terminal and electronic equipment, each bit in a bit sequence corresponds to a letter
Road.Each bit in the bit sequence is separately input into each ratio when sending bit sequence to electronic equipment by transmitting terminal
On special corresponding channel.Electronic equipment can receive multiple bit from multiple channel, and multiple bit is that electronics is set
Standby bit sequence to be decoded, electronic equipment can decode multiple bit, to obtain transmitting terminal in multiple channel
The bit sequence of upper transmission, that is, obtaining the decoding result of the bit sequence to be decoded.The embodiment of the present disclosure is for existing skill
The problem that the quantity adjustment period of decoding path is long in art, decoding delay is long, technical solution provided by the present disclosure is in decoding
In the process, the PC- decoding result for freezing bit is verified, and adjusts the quantity of decoding path, nothing according to its check results
It need to wait until that all decoding is adjusted whole bits again after the completion.
Fig. 1 is the structural schematic diagram for a kind of electronic equipment 100 that the embodiment of the present disclosure provides.Referring to Fig. 1, the electronic equipment
100 include processor and memory, is stored at least one instruction, at least a Duan Chengxu, code set or instruction set in memory,
At least one instruction, an at least Duan Chengxu, code set or instruction set are loaded by processor and are executed to realize in Fig. 2 embodiment
Interpretation method.It can also include communication interface, bus, input/output interface and display equipment, wherein processor, memory, defeated
Enter output interface, display equipment and communication interface and completes mutual communication by bus.
Memory may include high-speed random access memory (as caching), can also include nonvolatile memory,
A for example, at least disk memory, flush memory device or other volatile solid-state parts.Correspondingly, memory may be used also
To include Memory Controller, to provide the access of processor and input/output interface to memory.Bus is described by connection
Element circuit and between these elements realize transmission.For example, processor receives life from other elements by bus
It enables, decodes the order received, calculating or data processing are executed according to decoded order.Memory may include program module,
Such as kernel (kernel), middleware (middleware), application programming interface (Application Programming
Interface, API) and application.The program module can be by software, firmware or hardware or in which at least two form.
Input/output interface forwards user to pass through the order or data that input-output equipment (such as inductor, keyboard, touch screen) inputs.
Display equipment shows various information to user.Communication interface is by the electronic equipment 100 and other network equipments, user equipment, net
Network is attached.It is set for example, communication interface can be connected to external other networks by being wired or wirelessly connected to network
Standby or user equipment.Wireless communication may include following at least one: Wireless Fidelity (Wireless Fidelity, WiFi), blue
Tooth (Bluetooth, BT), the short distance wireless communication technology (Near Field Communication, NFC), global satellite is fixed
Position system (Global Positioning System, GPS) and cellular communication (cellular communication) (for example,
Long Term Evolution (Long Term Evolution, LTE), subsequent evolution (the Long Term of Long Term Evolution
Evolution-Advanced, LTE-A), CDMA (Code Division Multiple Access, CDMA), broadband code
Divide multiple access (Wideband CDMA, WCDMA), Universal Mobile Communication System (Universal Mobile
Telecommunication System, UMTS), wireless broadband Internet access (Wireless Broadband, WiBro) and the whole world are moved
Dynamic communication system (Global System for Mobile communication, GSM).Wire communication may include with down toward
Few one kind: universal serial bus (Universal Serial Bus, USB), high-definition multimedia interface (High
Definition Multimedia Interface, HDMI), asynchronous transmission standard interface (Recommended Standard
232, RS-232) and Plain Old Telephone Service (Plain Old Telephone Service, POTS).Network can be electricity
Communication network and communication network.Communication network can be computer network, internet, Internet of Things, telephone network.Electronic equipment 100
Network can be connected by communication interface, agreement used in electronic equipment 100 and other network device communications can be applied, be answered
Extremely with Program Interfaces (Application Programming Interface, API), middleware, kernel and communication interface
A few support.
In the exemplary embodiment, a kind of computer readable storage medium is additionally provided, instructed for example including at least one,
At least memory of a Duan Chengxu, code set or instruction set, above-mentioned at least one instruction at least a Duan Chengxu, code set or refer to
Enable collection that can be loaded and be executed by processor to complete the interpretation method in following Fig. 2 embodiments.For example, computer-readable storage medium
Matter can be read-only memory (Read-Only Memory, ROM), random access memory (Random-Access Memory,
RAM), CD-ROM (Compact Disc Read-Only Memory, CD-ROM), tape, floppy disk and optical data storage devices
Deng.
Fig. 2 is a kind of flow diagram for interpretation method that the embodiment of the present disclosure provides.The interpretation method is applied to electronics
In equipment, referring to fig. 2, which may include:
201, the maximum value and minimum value of decoding path quantity in SCL decoding algorithm are set.
For SCL decoding algorithm, the quantity of decoding path is bigger, and the decoding performance of SCL decoding algorithm is higher, but same
When decoding complexity will increase, decoding delay can increase；The quantity of decoding path is smaller, the complexity of SCL decoding algorithm is lower,
Decoding delay is shorter, but decoding performance can reduce simultaneously.In order to obtain compromise between complexity and performance, electronic equipment can be with
The quantity of decoding path is dynamically adjusted during decoding.
In the embodiment of the present disclosure, in order to avoid occurring, the quantity of decoding path is excessive to be caused decoding complexity excessively high or decodes
The too small two kinds of extreme cases for causing decoding performance too low of the quantity in path, electronic equipment is before starting decoding, for decoding
The quantity L in path, the maximum value that L can be set is Lmax, minimum value Lmin.L can be set when starting decoding in electronic equipment
Equal to 1, the value of L is adjusted according to practical decoding situation during decoding.It is less than L in the value of LminWhen, electronics is set
It is standby to continue to divide, i.e., retain whole decoding paths during decoding, until the quantity of decoding path reaches Lmin, this
Afterwards, continue to decode to step 206 according to subsequent step 202.
202, bit sequence to be decoded is decoded using SCL decoding algorithm, the decoding of the bit currently decoded
As a result.
Wherein, bit sequence to be decoded includes multiple bits to be decoded, and electronic equipment can be to multiple to be decoded
Bit is decoded one by one, and an each pair of bit is decoded, then the bit that the bit as currently decodes.Current decoding
Bit may be information bit, freeze bit or PC- freezes any bit in bit, the decoding result of each bit can
To be the value for the bit that SCL decoding algorithm is adjudicated, the decoding result of each bit can be 0 or 1.
In the embodiment of the present disclosure, each bit in bit sequence sent for transmitting terminal, electronic equipment be can use
SCL decoding algorithm is decoded, and every time after decoding, electronic equipment can be according to the quantity of current decoding path, from all decodings
Selection retains the maximum decoding path of PM value in path, and the quantity of the decoding path is identical as the quantity of current decoding path.Its
In, PM value can serve to indicate that the decoding result of the bit decoded on the decoding path all correct probability, which can
To be calculated using SCL decoding algorithm.
Referring to Fig. 3, a kind of Path selection schematic diagram of SCL decoding algorithm is provided.The decoder of electronic equipment first from
Root node starts to be decoded, and is extended to it according to bit for 0 or 1, extends later decoding path and need according to PM
Value size is ranked up, and then retains the maximum L decoding path of PM value, deletes other decoding paths.As shown in Fig. 2, working as
There are two decoding paths in left and right in decoding when proceeding to the second layer, the PM value of left side decoding path is 0.60, indicates first
The probability that the true value of bit is 0 is 0.60, and the PM value of the right decoding path is 0.40, indicates really taking for first bit
The probability that value is 1 is 0.40, if L=2, retains this two decoding paths.Occur four when decoding proceeds to third layer
Decoding path, PM value is respectively 0.33,0.27,0.30 and 0.20 from left to right, then retains two that PM value is 0.33 and 0.30
Decoding path continues to decode, and as shown by the solid line in the drawings, deletes two decoding paths that PM value is 0.27 and 0.20, no longer
Continue subsequent decoding process, as shown in phantom in FIG..
203, the bit currently decoded be PC- freeze bit, and in any bar decoding path the bit decoding result
When not over verification, it is determined that at least one targeted information bits decoded in the decoding path, the targeted information bits
It is the information bit that designated bit position is differed with the bit position, which is the shift cycle of circulating register
Integral multiple.
In the embodiment of the present disclosure, electronic equipment is during being decoded, for the inhomogeneity of the bit currently decoded
Type can take different processing strategies, for example, when the bit currently decoded is information bit or freezes bit, electronic equipment
Number of paths can not be adjusted, i.e. holding current path quantity L is constant；The bit currently decoded is that PC- freezes bit
When, the decoding result that electronic equipment can freeze bit to the PC- verifies, and according to check results, during decoding
The quantity of decoding path is adjusted, and specific adjustment process may include step 203 to step 206.Wherein, step 203 is to step
Rapid 205 be to have the PC- at least one decoding path to freeze the case where bit is not over verification, and step 206 is all decodings
The PC- freezes the case where bit passes through verification in path.
When the bit currently decoded is that PC- freezes bit, electronic equipment PC- in every decoding path freezes to compare
Spy is decoded after obtaining decoding result, and the decoding result that can freeze bit to the PC- verifies, and if PC is verified, is obtained
Check results.Check results may include that in PC verification, can be indicated with number 0 and 1 by verification and not over verification
Check results, such as when check results are 0, indicate, when check results are 1, to indicate not over verification by verification.It should
The process of PC verification may include: that the PC- decoding result for freezing the information bit decoded before bit is input to PC electricity
It is calculated in road, obtains the check results of PC circuit output, is i.e. then the PC- is freezed to compare by the check results that the PC- freezes bit
Special check results are compared with the PC- decoding result for freezing bit, if identical, pass through verification.
By the working principle of PC circuit it is found that cyclic shift circuits are only moved when the bit currently decoded is to freeze bit
Position；When freezing bit for PC-, the value that cyclic shift circuits export the first bit register as check value and is shifted；When for letter
When ceasing bit, the value of the first bit register is updated using the decoding result of the information bit.It is believed that when cyclic shift is deposited
When device length is S (S is prime number, the shift cycle corresponding to circulating register), some PC- freezes bit and only verifies its it
Freeze the information bit that bit position differs nS, i.e. targeted information bits with the PC- in preceding information bit, wherein n is positive
Integer.
In the step 203, if the PC- freezes the decoding result of bit not over school in any bar decoding path
It tests, then electronic equipment, which can determine in the decoding path, freezes relevant at least one targeted information bits of bit to the PC-.?
In a kind of possible implementation, electronic equipment determines that at least one targeted information bits decoded in the decoding path can wrap
It includes: determining that the PC- freezes bit and previous PC- freezes multiple information bits between bit；By in multiple information bit,
The information bit for meeting specified relationship formula is retrieved as at least one targeted information bits.The PC- freezes bit and previous PC-
Freezing all bits between bit may include information bit, freezes bit and PC- freezes bit, by bit type and refer to
Determine the restriction of relational expression, electronic equipment can filter out at least one targeted information bits from all bits.
Wherein, which can be formula (1):
Wherein, IiRefer to the index value of information bit；S refers to the length of circulating register (S is prime number)；I refers to
The index value of bit, value are 1 to N；InpRefer to that current PC-freezes the index value of bit, (InpValue is 1 to N, and p is current
PC- freezes bit and freezes the index value in bit since 1 in all PC-).
204, since the first aim information bit at least one targeted information bits, target information ratio is overturn
Special decoding as a result, and return back to the targeted information bits in the decoding path and re-start decoding, it is every to overturn and rollback is translated
Code is primary then to be verified the bit by the decoding result decoded again, when not over verification, is continued under
One targeted information bits is overturn and is retracted decoding.
In the embodiment of the present disclosure, the decoding result of the targeted information bits decoded will affect the PC- currently decoded and freeze
The decoding of knot bit is as a result, to influence the check results that the PC- freezes bit.The PC- freezes the check results of bit and is somebody's turn to do
It can satisfy formula (2) between the decoding result of at least one targeted information bits:
Wherein, PpFreeze the check results (such as 0 or 1) of bit for p-th of PC-；Pp-1Freeze bit for -1 PC- of pth
Check results；um, um+1... ..., unFreeze between bit for the two PC-, meets the decoding result of the information bit of formula (1)
(such as 0 or 1).
By formula (2) it is found that if the previous PC- that the PC- freezes bit freezes bit by verification, but the PC- freezes
Bit then causes the PC- to freeze bit and exists only in u not over the bit of verification not over verificationm, um+1... ..., un
In, it is unrelated with the information bit before previous PC- freezes bit, only freeze the information bit between bit with the two PC-
It is related.Due to S always odd number, therefore it can consider um, um+1... ..., unIn most possibly there is 1 bit decoding mistake.Therefore,
Electronic equipment can attempt the decoding result at least one targeted information bits and overturn one by one, and return back to and work as
The targeted information bits of preceding overturning decode again, obtain the PC- and freeze decoding that bit decodes again as a result, and to the decoding knot
Fruit is verified.
It should be noted that the step 204 is when the every overturning and rollback decoding primary after, which decodes again is obtained
When decoding result not over verification, electronic equipment continues to overturn and retract the process decoded.In a kind of possible implementation,
After every overturning and rollback decoding primary, when the decoding result which decodes again passes through verification, electronic equipment can be with
Terminate overturning and rollback decoding process, and using the overturning result of the targeted information bits of this overturning as the mesh of this overturning
Mark the decoding result of information bit.
In the embodiment of the present disclosure, electronic equipment overturns and is retracted the mistake of decoding at least one targeted information bits
Journey can be such that electronic equipment can first overturn the existing decoding of first aim information bit as a result, for example, first aim
The existing decoding result of information bit is 0, then it is 1 that electronic equipment, which can be decoded result overturning,.Then, electronic equipment can be with
First aim information bit is return back in the decoding path of step 203 and re-starts decoding, i.e., first aim is believed
The later bit of breath bit re-starts decoding, and PC- freezes the decoding knot that bit decodes again in step 203 available in this way
Fruit.It is verified at this point, electronic equipment can freeze the decoding result that bit decodes again to the PC-, if by verification,
Electronic equipment can terminate overturning and rollback decoding process, i.e., no longer to first aim information bit subsequent target information ratio
Spy overturns and retracts decoding, at this point, electronic equipment can be by overturning result (such as 1) conduct of first aim information bit
The decoding result of the first aim information bit；If electronic equipment can believe second target not over verification
It ceases bit and carries out process identical with first aim information bit, and so on, electronic equipment can be to other target informations
Bit carries out identical process.
By the process of above-mentioned overturning and the decoding that retracts it is found that electronic equipment terminates to overturn and rollback decoding process may exist
Two following situations:
The first situation, electronic equipment to some targeted information bits at least one targeted information bits into
After row overturning and the decoding that retracts, so that the PC- freezes decoding result that bit decodes again by verification, then electronic equipment can be with
Terminate overturning and rollback decoding process.The situation provides a kind of opportunity for terminating overturning and rollback decoding process, under the situation,
Electronic equipment may can terminate overturning and back off procedure without having overturn whole targeted information bits, and electronic equipment can be with
The overturning result of the targeted information bits overturn before terminating is as the decoding of the targeted information bits as a result, without to decoding
The quantity in path is adjusted.
Second case, electronic equipment are all overturn and are retracted decoding at least one targeted information bits
Afterwards, which freezes decoding result that bit decodes again still not over verification, then electronic equipment can terminate to overturn and return
Decoding process is moved back, and executes subsequent step 205.The situation provides another opportunity for terminating overturning and rollback decoding process,
It, may be every time not over school during the overturning of at least one targeted information bits and rollback decoding under the situation
It tests, i.e., at least one targeted information bits all overturn and after the decoding that retracts, and the PC- can not still be made to freeze the decoding of bit
As a result pass through verification.
205, when at least one targeted information bits are overturn and retracted decoding and the bit by again decoding
Decoding result not over verification when, then increase the quantity of decoding path and continue to decode.
The step 205 is for the second case in step 204, if electronic equipment terminates to overturn in this case
With rollback decoding process, illustrate that current error rate is higher, the verification percent of pass that PC- freezes bit is low, and decoding performance is poor.This
When, the quantity of the adjustable decoding path of electronic equipment improves the verification percent of pass that PC- freezes bit to improve decoding performance.
In a kind of possible implementation, the quantity that electronic equipment adjusts decoding path may include: that will currently decode road
The quantity of diameter is adjusted to the smaller value in first path quantity and the second number of paths, which is the current decoding
Twice of the quantity in path, second number of paths are pre-set number of paths maximum value.First path quantity and second
Number of paths is all larger than the quantity of current decoding path, this time adjusts namely increase the quantity of decoding path.When PC- freezes bit
Verification percent of pass it is low when, show that the bit error rate is higher, decoding performance is poor, at this time by tuning up the quantity of decoding path so that
The quantity of decoding path levels off to maximum value, it is ensured that decoding performance.
Since the quantity of decoding path changes, the decoding path item number retained after each bit decoding is become
Change, therefore electronic equipment needs the quantity according to the decoding path after variation, re-starts decoding.By step 204 it is found that causing
The PC- freezes bit and exists only at least one targeted information bits not over the bit of verification, therefore electronic equipment
The first aim information bit that all decoding paths can be return back at least one targeted information bits decodes again.
When the quantity of decoding path changes, only returning back to influences the targeted information bits weight that the PC- freezes bit check result
It is newly decoded, and keeps the decoding result of the bit decoded before targeted information bits constant, it in this way can be to avoid again
Whole decoding processes is carried out, unnecessary decoding delay is avoided.When the bit error rate is higher, the quantity of decoding path can lead to
The feedback for crossing check results quickly adjusts, and without decoding again from the beginning repeatedly, need to only return back to and freeze bit phase with the PC-
The first aim information bit of pass decodes again, accelerates convergence speed of the algorithm, solves the problems, such as that decoding delay is too long.
It is that PC- freezes bit, and any bar decoding path that above-mentioned steps 203 to step 205, which is in the bit currently decoded,
In PC- when freezing the decoding result of bit not over verification, electronic equipment freezes bit check result to the PC- is influenced
At least one targeted information bits is overturn and is retracted the process of decoding.In fact, freezing in the bit currently decoded for PC-
When bit, the decoding result that the PC- freezes bit in possible whole decoding paths passes through verification, then electronic equipment can execute
Subsequent step 206.
206, when the decoding result of the bit in all decoding paths passes through verification, then the quantity of decoding path is adjusted
And continue to decode.
In the embodiment of the present disclosure, if the decoding result that the PC- freezes bit in whole decoding paths passes through verification, say
Bright current error rate is lower, and the verification percent of pass that PC- freezes bit is high, and decoding performance is higher, but when decoding complexity height, decoding
Extend.At this point, the quantity of the adjustable decoding path of electronic equipment, to reduce decoding complexity and shorten decoding delay.
In a kind of possible implementation, the quantity that electronic equipment adjusts decoding path may include: that will currently decode road
The quantity of diameter is adjusted to the larger value in third number of paths and the 4th number of paths, which is the current decoding
The half of the quantity in path, the 4th number of paths are pre-set number of paths minimum value.Third number of paths and the 4th
Number of paths is respectively less than the quantity of current decoding path, this time adjusts namely reduce the quantity of decoding path.When PC- freezes bit
Verification percent of pass it is high when, show that the bit error rate is lower, at this time by turning the quantity of decoding path down, so that the quantity of decoding path
Close to minimum value, decoding complexity can be reduced, guarantees decoding speed.
Since the quantity of decoding path changes, the decoding path item number retained after each bit decoding is become
Change, therefore electronic equipment can freeze bit from the PC- and continue to decode according to the quantity of decoding path adjusted.When
After the completion of whole bit decodings in bit sequence, electronic equipment can be ranked up L decoding path, and choosing one has
The decoding path of maximum PM value is combined into as correct decoding path, and by the decoding result of bit each in the decoding path
Bit sequence output, to complete this decoding process.
Certainly, when the bit currently decoded is that PC- freezes bit, it is also possible to which the PC- freezes to compare in whole decoding paths
Special decoding result is not over verification, and every decoding path is all to terminate to overturn with the second case in step 204
And back off procedure, then show that the bit error rate is excessively high, decoding performance is too low, at this point, electronic equipment can consider decoding failure, directly ties
Beam SCL decoding algorithm.
The method that the embodiment of the present disclosure provides, during decoding, if the bit currently decoded is that PC- freezes bit,
And the PC- is when freezing the decoding result of bit not over verification, by the information for influencing the PC- and freezing bit check result
Bit is overturn and is retracted one by one decoding, freezes the decoding knot that bit decodes again to the PC- after the decoding that retracts every time
Fruit is verified, if verification is all not over illustrating that current error rate is higher, at this point, electronic equipment is adjustable every time
The quantity of decoding path reduces the bit error rate to improve decoding performance, improves the verification percent of pass that PC- freezes bit.Above-mentioned technology
Scheme is compared with needing to be adjusted the quantity of decoding path after the completion of whole bit decodings in the prior art, this public affairs
The adjustment period for opening middle decoding path quantity is shorter, needs the short period so i.e. and can reach the decoding path for meeting estimated performance
Quantity, substantially reduce decoding delay.
In addition, the quantity of decoding path is provided with maximum value and minimum value, when the bit error rate is lower, PC- freezes bit
It is high to verify percent of pass, by turning the quantity of decoding path down, so that the quantity of decoding path is close to minimum value, it is multiple to reduce decoding
Miscellaneous degree guarantees decoding speed；When the bit error rate is higher, the verification percent of pass that PC- freezes bit is low, by the number for tuning up decoding path
Amount, so that the quantity of decoding path levels off to maximum value, to guarantee decoding performance.
In addition, verifying during decoding to the bit currently decoded, and decoding path is adjusted according to check results
Quantity, when the bit error rate is higher, the quantity of decoding path can quickly be adjusted by the feedback of check results, without weighing repeatedly
New decoding need to only return back to and freeze the relevant first aim information bit of bit to the PC- and decode again, accelerate algorithm
Convergence rate solves the problems, such as that decoding delay is too long.
Fig. 4 is a kind of structural schematic diagram for code translator that the embodiment of the present disclosure provides.Referring to Fig. 4, which includes true
Cover half block 401, decoding module 402 and adjustment module 403.
Determining module 401, for freezing bit in the bit currently decoded for PC-, and the ratio in any bar decoding path
When special decoding result is not over verification, it is determined that at least one targeted information bits decoded in the decoding path, it should
Targeted information bits are the information bits that designated bit position is differed with the bit position, which is cyclic shift deposit
The integral multiple of the shift cycle of device；
Decoding module 402, for turning over since the first aim information bit at least one targeted information bits
Turn the decoding of targeted information bits as a result, and return back to the targeted information bits in the decoding path and re-start decoding, often
Overturning and the decoding that retracts once then pass through the decoding result decoded again to the bit and verify, when not over verification
When, continue decoding that next targeted information bits are overturn and retracted；
Adjust module 403, for when at least one targeted information bits overturn and retracted decoding and the bit
When by the decoding result that decodes again not over verification, then adjusts the quantity of decoding path and continue to decode.
In a kind of possible implementation, which freezes to compare for executing in above-mentioned steps 203 by the PC-
The information bit that special and previous PC- freezes to meet in multiple information bits between bit specified relationship formula is retrieved as this extremely
The process of few targeted information bits.
In a kind of possible implementation, which adjusts current decoding for executing in above-mentioned steps 205
After the quantity in path, all decoding paths are return back to the first aim information bit at least one targeted information bits
Again the process decoded.
In a kind of possible implementation, which is also used to execute in above-mentioned steps 204 when any time is turned over
Turn and the decoding that retracts after, when which freezes the decoding result that bit decodes again and pass through verification, terminate overturning and rollback translated
The process of code.
In a kind of possible implementation, which is also used to execute in above-mentioned steps 206 when all decodings
When the decoding result that the PC- freezes bit in path passes through verification, the process of the quantity of current decoding path is adjusted.
In the embodiment of the present disclosure, during decoding, if the bit currently decoded is that PC- freezes bit, and the PC- freezes
When tying the decoding result of bit not over verification, by freezing information bit one of bit check result to influencing the PC-
One decoding that overturn and retracted freezes the decoding result that bit decodes again to the PC- after the decoding that retracts every time and carries out school
It tests, if verification is all not over illustrating that current error rate is higher, at this point, the adjustable decoding path of electronic equipment every time
Quantity reduce the bit error rate to improve decoding performance, improve the verification percent of pass that PC- freezes bit.Above-mentioned technical proposal and existing
Have to need to be adjusted the quantity of decoding path after the completion of whole bit decodings in technology and compare, is decoded in the disclosure
The adjustment period of number of paths is shorter, needs the short period so i.e. and can reach the quantity for meeting the decoding path of estimated performance,
Substantially reduce decoding delay.
It should be understood that code translator provided by the above embodiment decoding when, only with above-mentioned each functional module draw
Divide and be illustrated, in practical application, can according to need and be completed by different functional modules above-mentioned function distribution, i.e.,
The internal structure of equipment is divided into different functional modules, to complete all or part of the functions described above.On in addition,
The code translator and interpretation method embodiment for stating embodiment offer belong to same design, and specific implementation process is detailed in method implementation
Example, which is not described herein again.
Those of ordinary skill in the art will appreciate that realizing that all or part of the steps of above-described embodiment can pass through hardware
It completes, relevant hardware can also be instructed to complete by program, the program can store in a kind of computer-readable
In storage medium, storage medium mentioned above can be read-only memory, disk or CD etc..
The foregoing is merely the alternative embodiments of the disclosure, not to limit the disclosure, all spirit in the disclosure and
Within principle, any modification, equivalent replacement, improvement and so on be should be included within the protection scope of the disclosure.
Claims (12)
1. a kind of interpretation method, which is characterized in that the described method includes:
It is that even-odd check PC- freezes bit, and the decoding knot of bit described in any bar decoding path in the bit currently decoded
When fruit is not over verification, it is determined that at least one targeted information bits decoded in the decoding path, the target letter
Ceasing bit is the information bit that designated bit position is differed with the bit position, and the designated bit position is circulating register
Shift cycle integral multiple；
Since the first aim information bit at least one described targeted information bits, translating for targeted information bits is overturn
Code as a result, and return back to the targeted information bits in the decoding path and re-start decoding, every overturning and rollback decode
It is primary then the decoding result that decodes again is passed through to the bit and is verified, when not over verification, continue under
One targeted information bits is overturn and is retracted decoding；
When at least one described targeted information bits overturn and retracted decoding and the bit pass through decode again translate
When code result is not over verification, then increases the quantity of decoding path and continue to decode.
2. the method according to claim 1, wherein decoded in the determination decoding path at least one
A targeted information bits include:
Determine that the previous even-odd check PC- of the bit and the bit freezes at least one information bit between bit；
The information bit at least one described information bit, meeting specified relationship formula is retrieved as at least one target letter
Cease bit.
3. the method according to claim 1, wherein it is described increase decoding path quantity and continue to decode
Include:
The quantity of current decoding path is adjusted to the smaller value in first path quantity and the second number of paths, the first via
Diameter quantity is twice of the quantity of the current decoding path, and second number of paths is that pre-set number of paths is maximum
Value；
The first aim information bit that all decoding paths are return back at least one described targeted information bits is translated again
Code.
4. the method according to claim 1, wherein the method also includes:
After every overturning and primary rollback decoding, when the decoding result that the bit decodes again passes through verification, terminate to turn over
Turn and rollback decoding process；
Using the overturning result of the targeted information bits of this overturning as the decoding knot of the targeted information bits of this overturning
Fruit.
5. the method according to claim 1, wherein the method also includes:
When the decoding result of the bit described in all decoding paths passes through verification, the quantity of current decoding path is adjusted to
The larger value in third number of paths and the 4th number of paths, and continue to decode, the third number of paths is described works as
The half of the quantity of preceding decoding path, the 4th number of paths are pre-set number of paths minimum value.
6. a kind of code translator, which is characterized in that described device includes:
Determining module, for freezing bit in the bit currently decoded for even-odd check PC-, and described in any bar decoding path
When the decoding result of bit is not over verification, it is determined that at least one the target information ratio decoded in the decoding path
Spy, the targeted information bits are the information bits that designated bit position is differed with the bit position, and the designated bit position is
The integral multiple of the shift cycle of circulating register；
Decoding module, for overturning mesh since the first aim information bit at least one described targeted information bits
Mark the decoding of information bit as a result, and return back to the targeted information bits in the decoding path and re-start decoding, often
Overturning and the decoding that retracts once then pass through the decoding result decoded again to the bit and verify, when not over school
When testing, continue decoding that next targeted information bits are overturn and retracted；
Module is adjusted, for being overturn and being retracted decoding and the bit passes through when at least one described targeted information bits
Again when the decoding result decoded is not over verification, then increases the quantity of decoding path and continue to decode.
7. device according to claim 6, which is characterized in that the determining module, for determining the bit and described
The previous even-odd check PC- of bit freezes multiple information bits between bit；By in the multiple information bit, satisfaction refers to
The information bit for determining relational expression is retrieved as at least one described targeted information bits.
8. device according to claim 6, which is characterized in that the adjustment module, for by the number of current decoding path
The smaller value being adjusted in first path quantity and the second number of paths is measured, the first path quantity is the current decoding road
Twice of the quantity of diameter, second number of paths are pre-set number of paths maximum value；All decoding paths are retracted
It is decoded again to the first aim information bit at least one described targeted information bits.
9. device according to claim 6, which is characterized in that the decoding module is also used to translate when every overturning and rollback
After code is primary, when the decoding result that the bit decodes again passes through verification, terminate overturning and rollback decoding process；It incite somebody to action this
Decoding result of the overturning result of the targeted information bits of secondary overturning as the targeted information bits of this overturning.
10. device according to claim 6, which is characterized in that the adjustment module is also used to when in all decoding paths
When the decoding result of the bit passes through verification, the quantity of current decoding path is adjusted to third number of paths and the 4th tunnel
The larger value in diameter quantity, and continue to decode, the third number of paths is the one of the quantity of the current decoding path
Half, the 4th number of paths is pre-set number of paths minimum value.
11. a kind of electronic equipment, which is characterized in that the electronic equipment includes processor and memory, is deposited in the memory
Contain at least one instruction, at least a Duan Chengxu, code set or instruction set, at least one instruction, an at least Duan Cheng
Sequence, the code set or instruction set are loaded by the processor and are executed to realize as any in claim 1 to claim 5
Interpretation method described in.
12. a kind of computer readable storage medium, which is characterized in that be stored at least one in the computer readable storage medium
Item instruction, at least a Duan Chengxu, code set or instruction set, at least one instruction, an at least Duan Chengxu, the code
Collection or instruction set are loaded by processor and are executed to realize such as decoding side described in any one of claims 1 to 5
Method.
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