CN114138099A - Method, device and terminal for configuring memory - Google Patents

Method, device and terminal for configuring memory Download PDF

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CN114138099A
CN114138099A CN202111353277.9A CN202111353277A CN114138099A CN 114138099 A CN114138099 A CN 114138099A CN 202111353277 A CN202111353277 A CN 202111353277A CN 114138099 A CN114138099 A CN 114138099A
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memory
channel condition
block
time unit
terminal
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熊晓竹
郭青云
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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Priority to PCT/CN2022/121446 priority patent/WO2023082872A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/203—Details of error rate determination, e.g. BER, FER or WER
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W16/00—Network planning, e.g. coverage or traffic planning tools; Network deployment, e.g. resource partitioning or cells structures
    • H04W16/22—Traffic simulation tools or models
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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Abstract

A method, an apparatus and a terminal for configuring a memory are provided. The method comprises the following steps: predicting a first channel condition parameter, wherein the first channel condition parameter is used for indicating the channel condition of the terminal in a first time unit after the current time unit; determining a first block error rate of a coding block corresponding to the first channel condition parameter and a first modulation and coding strategy according to the first channel condition parameter, the first modulation and coding strategy configured by the terminal and prestored mapping relationship information, wherein the mapping relationship information is used for indicating the mapping relationship among the channel condition parameter, the modulation and coding strategy and the block error rate of the coding block; and determining the throughput rate of a memory of the terminal in a first time unit according to the first block error rate, wherein the memory is used for storing the data of the coding block contained in the first transmission block transmitted in the first time unit. According to the embodiment of the application, the purpose of saving power consumption is achieved by predicting the throughput rate of the memory.

Description

Method, device and terminal for configuring memory
Technical Field
The present application relates to the field of communications technologies, and more particularly, to a method, an apparatus, and a terminal for configuring a memory.
Background
In the downlink receiving process, the terminal needs to access a memory, such as a double data rate synchronous random access memory (DDR). Therefore, the voltage and/or frequency of the memory needs to be set well before data accesses to the memory to match the throughput of the memory.
The conventional technology generally takes the peak throughput rate of the memory as a predicted value of the throughput rate of the memory, and sets the voltage and/or frequency of the memory based on the peak throughput rate of the memory, which increases the power consumption of the memory and is not favorable for achieving the purpose of power saving.
Disclosure of Invention
In order to solve the above problems, the present application provides a prediction method, a prediction apparatus, and a terminal.
In a first aspect, a method for configuring a memory is provided, comprising: predicting a first channel condition parameter, wherein the first channel condition parameter is used for indicating the channel condition of the terminal in a first time unit after the current time unit; determining a first block error rate of a coding block corresponding to the first channel condition parameter and a first modulation and coding strategy according to the first channel condition parameter, the first modulation and coding strategy configured by the terminal, and pre-stored mapping relationship information, wherein the mapping relationship information is used for indicating a mapping relationship among the channel condition parameter, the modulation and coding strategy, and the block error rate of the coding block; and determining the throughput rate of a memory of the terminal in the first time unit according to the first block error rate, wherein the memory is used for storing the data of the coding block contained in the first transmission block transmitted in the first time unit.
In a second aspect, an apparatus for configuring a memory is provided, comprising: a prediction module configured to predict a first channel condition parameter, wherein the first channel condition parameter is used for indicating a channel condition of a terminal in a first time unit after a current time unit; a processing module for processing the received data,
the terminal is configured to determine a first block error rate of a coding block corresponding to the first channel condition parameter and a first modulation and coding strategy according to the first channel condition parameter, the first modulation and coding strategy configured by the terminal, and pre-stored mapping relationship information, wherein the mapping relationship information is used for indicating a mapping relationship among the channel condition parameter, the modulation and coding strategy, and the block error rate of the coding block; and determining the throughput rate of a memory of the terminal in the first time unit according to the first block error rate, wherein the memory is used for storing the data of the coding block contained in the first transmission block transmitted in the first time unit.
In a third aspect, a chip is provided, which includes the apparatus for configuring a memory according to the second aspect.
In a fourth aspect, a terminal is provided that includes a memory and a processor. The memory is for storing code and the processor is for executing the code stored in the memory to perform a method as set forth in the first aspect.
In a fifth aspect, there is provided a computer readable storage medium having stored thereon code for performing the method of the first aspect.
A sixth aspect provides a computer program product comprising code for performing the method of the first aspect.
The embodiment of the application predicts the channel condition parameters of the first time unit, and accurately predicts the actual throughput rate of the memory in the first time unit based on the prediction result and the pre-stored mapping relation information. Compared with the mode of setting the voltage and/or the frequency of the memory based on the peak throughput rate of the memory, the voltage and/or the frequency of the memory in the first time unit are set based on the actual throughput rate of the memory in the first time unit, and the purpose of saving power consumption can be achieved.
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Fig. 1 is a schematic diagram of a system architecture to which embodiments of the present application may be applied.
Fig. 2 is a schematic flow chart of a method for configuring a memory provided by an embodiment of the present application.
Fig. 3 is an exemplary diagram of one possible implementation of step S230 in fig. 2.
Fig. 4 is an exemplary diagram of an implementation of the method shown in fig. 2 in an initial transmission scenario.
Fig. 5 is an exemplary diagram of an implementation of the method shown in fig. 2 in a retransmission scenario.
Fig. 6 is a schematic structural diagram of an apparatus for configuring a memory according to an embodiment of the present disclosure.
Fig. 7 is a schematic structural diagram of a terminal according to an embodiment of the present application.
Detailed Description
The embodiment of the present application can be applied to the communication system 100 shown in fig. 1. The communication system 100 is a cellular communication system. The cellular communication system may be, for example, a Long Term Evolution (LTE) system, a 5th generation (5G) system, or a New Radio (NR) system.
Communication system 100 may include a network device 110 (e.g., a base station) and a terminal 120. The terminal 120 may be a mobile station, a user equipment, a mobile terminal, a mobile phone (mobile phone), a tablet computer (Pad), a notebook computer, a palm computer, etc.
Network device 110 may transmit downlink data to terminal 120 via the downlink. The downlink data may be, for example, a Physical Downlink Shared Channel (PDSCH). After receiving the PDSCH, terminal 120 may perform a decoding operation on the PDSCH. If the decoding is incorrect, the terminal 120 may request the network device 110 to retransmit based on a hybrid automatic repeat request (HARQ) mechanism. The terminal 120 may need to access the memory for data whether the decoding is correct or incorrect. For example, during the initial data transmission process, the terminal 120 may need to store the data with decoding error to the HARQ memory on the memory. For another example, during the data retransmission process, the terminal 120 may need to read the data with failed decoding stored in the HARQ memory of the memory to the on-chip memory for combining with the retransmitted data. The memory may be an off-chip memory of the baseband chip. The memory may be DDR, for example.
The voltage and/or frequency of the memory needs to be set well before data accesses to the memory to match the throughput of the memory. For example, assuming that the network device schedules the terminal to receive the PDSCH in the current time slot, the terminal needs to predict the throughput rate of the memory in the current time slot before the current time slot arrives, so as to set the voltage and/or frequency of the memory to match the predicted value of the throughput rate.
In the prior art, the peer calculates the peak throughput rate that the memory can achieve under the current configuration of the terminal according to the parameters configured for the terminal by the network device. The terminal may then take the peak throughput rate as a predicted value of the throughput rate of the memory, thereby setting the voltage and/or frequency of the memory based on the peak throughput rate.
The peak throughput rate of the memory occurs in a high block error rate (BLER) scenario. For example, the terminal may include on-chip memory contained within the baseband chip and off-chip memory external to the baseband chip. During the process of receiving the downlink PDSCH, the modem of the terminal may cause a large number of decoding errors of a Code Block (CB) if the modem experiences a fast fading channel or is subjected to other interference. In the initial case, the soft bits of the coding block with decoding error need to be stored in the HARQ memory of the off-chip memory for HARQ combining at the time of retransmission. In case of retransmission, the soft bits stored in the HARQ memory of the off-chip memory need to be read to the on-chip HARQ memory first. Then, the terminal performs HARQ combining operation and decodes the combined data. If the decoding of the retransmitted data is erroneous again, the soft bits of the encoded block need to be stored again in the off-chip memory. In an extreme case, if all the coding blocks of a Transport Block (TB) are decoded incorrectly during initial transmission and retransmission, in case of retransmission, the soft bits of the coding blocks are read from the off-chip memory to the on-chip HARQ memory, and then moved from the on-chip HARQ memory to the off-chip memory for read-write operation, so that the throughput of the off-chip memory can reach the peak throughput mentioned above.
The data throughput of NR FR 17 Gbps (FR1 refers to a frequency range of 450MHz to 6000 MHz) is taken as an example for explanation. Assuming that the bit number of each soft bit of a coding block is 4 and the code rate is 2/3, at the initial transmission, if all coding blocks of a transmission block are decoded in error, the throughput rate of an off-chip memory caused by the soft bits of the coding block is 7Gbps 1.5 Gbps 4-42 Gbps (1.5 in the expression represents the reciprocal of the code rate). When retransmitting, the soft bits need to be read from the off-chip memory to the on-chip memory for HARQ combination. If all the coding blocks of the transmission block are decoded incorrectly again, the soft bits of the coding blocks obtained by initial transmission and retransmission need to be moved from the on-chip memory to the off-chip memory, and at this time, the off-chip memory reaches the peak throughput rate which can reach 2 times of the throughput rate of the off-chip memory during initial transmission, namely 84 Gbps.
In the conventional technology, after the network device configures the number of carriers, the carrier bandwidth and the subcarrier spacing of LTE/NR for the terminal, the terminal calculates the peak throughput rate of the memory according to these configuration parameters, and then uses the peak throughput rate as a predicted value of the throughput rate to set the voltage and/or frequency of the memory. For example, assuming that a network device configures 3 LTE carriers, each carrier has a bandwidth of 20MHz, the highest modulation scheme is 256QAM, and the highest number of layers is 4, the data throughput rate of the 3 carriers may reach 1.2Gbps, and assuming that the bit number of each soft bit of a coding block is 4 and the code rate is 2/3, the peak throughput rate of the memory is 1.2Gbps 1.5 × 4 × 2 — 14.4 Gbps.
Table 1 lists the relationship between the data throughput rate of the carrier, the peak throughput rate of the memory, and the predicted value of the throughput rate of the memory in the carrier configuration commonly used in NR, LTE, and endec in the conventional technology.
TABLE 1
Figure BDA0003354759100000051
Figure BDA0003354759100000061
As can be seen from the discussion above, conventional techniques treat the peak throughput rate of memory as a predictor of the throughput rate of memory. However, the throughput of the memory will only reach the peak throughput in extreme cases (retransmission scenario and coding block of the transport block all decoded in error). In other words, the throughput of the memory cannot reach a peak in most cases. Therefore, the prediction mode of the throughput rate of the memory in the traditional technology cannot accurately reflect the actual throughput rate of the memory. The conventional technology generally sets the voltage and/or frequency of the memory in units of time slots, and if the voltage and/or frequency of the memory is set in accordance with the peak throughput rate of the memory in each time slot, the power consumption of the memory is very large, and the power saving purpose cannot be achieved.
In fact, during the downlink receiving process, the throughput of the memory may be determined by the throughput of soft bits of the physical layer, the throughput of hard bits of a Medium Access Control (MAC) layer, and the throughput of data plane Packet Data Convergence Protocol (PDCP) layer to decrypt data (where the MAC layer and the PDCP layer both belong to the data plane). The throughput rate of the MAC layer hard bits and the throughput rate of the PDCP layer decrypted data determine the average throughput rate of the memory, while the throughput rate of the physical layer soft bits determines the peak throughput rate of the memory.
The throughput rate of the memory is typically dynamically changing. For example, the throughput rate of the memory may vary every slot. The following is an analysis of factors that may cause variations in the throughput rate of the memory.
First, the block error rate (BLER) of a transport block between a network device and a terminal generally needs to be maintained below a certain range, for example, the BLER needs to be maintained below 10%. To achieve this, when the channel condition of the terminal deteriorates, the network device typically adjusts a Modulation and Coding Scheme (MCS) to reduce the transmission rate between the network device and the terminal. In this case, the size of the transport block transmitted by the network device to the terminal may become small. When the channel condition of the terminal becomes better, the network adjusts the MCS to increase the transmission rate between the network device and the terminal. In this case, the size of the transport block transmitted by the network device to the terminal may become large. Variations in transport block size can cause variations in the average throughput rate of the memory. It follows that a change in MCS causes a change in the throughput of the memory.
Secondly, the channel condition of the terminal may also vary between two adjacent time slots. For example, when a downlink channel experiences a fast fading channel or interference, the channel condition of the terminal may deteriorate. However, the network device does not adjust the size of the transport block in real time, but has a certain delay. In a shorter time (e.g., one slot time), the network device may not have time to adjust the transport block size. The BLER of the transport block may increase very rapidly some time before the channel conditions have deteriorated to the point where the transport block size adjustment is complete. In this case, a large amount of data read/write operations related to the HARQ process will occur in the memory, resulting in a sudden increase in the throughput of the memory. It follows that a change in the BLER of the transport block of the terminal also causes a change in the throughput of the memory.
Again, each slot may be an initial transmission or a retransmission. Under the condition of initial transmission and coding block decoding error, the soft bits of the coding block need to be moved from the on-chip memory to the memory so as to carry out HARQ combination in the following process. In case of retransmission and decoding errors, the soft bits of the encoded block need to be moved from memory to on-chip memory first. And after the decoding is finished, the soft bits of the coding block are moved to the memory from the on-chip memory. It follows that a change in the transmission scenario (initial transmission scenario and retransmission scenario) causes a change in the throughput rate of the memory.
From the above analysis, it can be seen that the throughput of the memory may change due to the change of MCS, the change of BLER of the transport block, and the change of the initial transmission and retransmission scenarios. Therefore, the related art regards the peak throughput rate of the memory as a predicted value of the throughput rate of the memory, and cannot accurately reflect the actual throughput rate of the memory. The voltage and/or frequency of the memory are/is set according to the peak throughput rate of the memory, the power consumption of the memory is very large, and the aim of saving power cannot be achieved.
In order to solve the above problem, an embodiment of the present application will be described below with reference to fig. 2.
As shown in fig. 2, a first channel condition parameter is predicted at step S210. The channel condition parameters mentioned in the embodiments of the present application may be any type of parameters capable of describing a channel state. Illustratively, the channel condition parameter may be a signal to noise ratio (SNR).
The first channel condition parameter may be used to indicate a channel condition for the terminal for a first time unit after the current time unit. The time unit mentioned in the embodiments of the present application may refer to one or more symbols, one or more slots, one or more subframes, one or more milliseconds, and the like. The first time unit may be a next time unit to the current time unit. Alternatively, the first time unit and the current time unit may be separated by one or more time units. Taking time units as time slots as an example, the current time unit and the first time unit may be two adjacent time slots, that is, the first time unit is a time slot next to the current time slot.
The first channel condition parameter may be predicted in a variety of ways. For example, the first channel condition parameter may be predicted based on the channel condition parameters of the terminal in the current time unit. As another example, the first channel condition parameter may be predicted based on channel condition parameters of a historical time unit of the terminal prior to the current time unit. For another example, the channel condition parameters of the terminal in the current time unit and the channel condition parameters in the historical time unit may be weighted and summed to predict the first channel condition parameter.
As an example, assuming that the channel condition parameter is SNR, the time unit is a time slot, and the first time unit is a next time slot of the current time slot, the SNR of the next time slot may be predicted by using the following formula:
SNRest＝(1-a)*SNRhustory+a*SNRlatest
in the above equation, SNRestIs the predicted SNR of the next slot. SNRlatestIs the SNR of the current slot, i.e., the latest SNR value. SNRhistoryThe historical SNR may be, for example, the SNR of a time slot prior to the current time slot. a is a weighting factor. The value of a may be a fixed value, or may be adjusted according to the SNR prediction effect. Illustratively, a may be set to 0.4.
Because the channel variation of two adjacent time slots is limited, the variation of the channel condition parameters of two adjacent time slots is also limited, so that the channel condition parameter of the next time slot can be obtained more accurately according to the channel condition parameter of the current time slot.
In step S220, a first block error rate of the coding block corresponding to the first channel condition parameter and the first modulation and coding strategy is determined according to the first channel condition parameter, the first MCS configured by the terminal, and the pre-stored mapping relationship information.
The first MCS is a MCS currently configured by the terminal. The first MCS may be configured by the network device for the terminal according to channel conditions. The terminal may first acquire the first MCS before performing step S220. For example, the terminal may first receive Downlink Control Information (DCI) transmitted by the network device. Then, the terminal may obtain the index value of the MCS from the information field corresponding to the MCS in the downlink control information, thereby obtaining the first MCS.
The terminal may store the mapping relationship information in advance. The mapping relation information can be used for indicating the mapping relation among the channel condition parameter, the MCS and the block error rate of the coding block. The form of the mapping relationship information may be a mapping relationship curve or a mapping relationship table, which is not specifically limited in this embodiment of the present application.
The block error rate of a coding block may refer to the probability of a coding block in a transmission block having a decoding error under the condition of a transmission error of the transmission block. By transport block transmission error is meant a decoding error of at least one coded block in the transport block. It follows that the block error rate of a coded block can be understood as the conditional probability under the condition of transmission error of the transport block.
The mapping relationship information may be obtained in various ways. For example, in some embodiments, a relationship curve of channel condition parameters and block error rate of a coded block under different MCSs may be simulated. And then recording the relation among the MCS, the channel condition parameter and the block error rate in a mapping relation table according to the relation curve obtained by simulation. In other embodiments, to improve the accuracy of the mapping relationship information, the mapping relationship information may be an average result of the recorded performance curves in various channel environments.
The first block error rate may be a block error rate of a coding block corresponding to the first channel condition parameter and the first MCS. In other words, the first block error rate may indicate a block error rate of the coded block for the first time unit. The terminal can obtain the first block error rate by inquiring the mapping relation information according to the first channel condition parameter and the first MCS.
In the following, with reference to table 2, a possible form of mapping relationship information is given by taking the channel condition parameter as an SNR as an example.
TABLE 2
Figure BDA0003354759100000091
Figure BDA0003354759100000101
SNR in Table 2min_mcsxRepresents the minimum threshold for SNR when MCS is MCSX. When the SNR is less than the minimum threshold, the block error rate of the coded block is 1. SNRstepRepresenting the step size of the SNR value progression. SNRstepCan be set according to actual needs. In one embodiment, to achieve both accuracy and complexity, the SNR may be adjustedstepSet to 0.25 dB. BLERImcsxMCS is MCSX, SNR is SNRminmcsx+i*SNRstepThe block error rate of the block is coded.
Using the first channel condition parameter as SNRmin_mcs5+3*SNRstepFor example, the first MCS configured by the terminal is MCS5, the aforementioned first block error rate may be BLER3mcs5。
In step S230, a throughput rate of the memory of the terminal in the first time unit (the throughput rate may refer to the predicted actual throughput rate of the external memory) is determined according to the first block error rate. For example, the number of correctly decoded and incorrectly decoded coding blocks may be calculated from the first block error rate, and then the throughput of the memory may be determined from the number of correctly decoded and incorrectly decoded coding blocks. As another example, a mapping relationship of the first block error rate, the number of coded blocks included in the transport block, and the throughput rate of the memory may be established, and the throughput rate of the memory in the first time unit may be determined based on the mapping relationship. As another example, the throughput rate of the memory may be estimated based on an empirical formula, provided that the first block error rate is determined. The memory of the terminal may be used to store data of an encoded block comprised by a first transport block transmitted within a first time unit.
According to the embodiment of the application, the actual throughput rate of the memory is accurately predicted, so that the voltage and/or frequency of the memory in each time unit are/is set more accurately, and the purpose of saving power consumption and electric quantity is achieved.
One possible implementation of step S230 is given below in conjunction with fig. 3. As shown in fig. 3, step S230 includes step S232 and step S234.
In step S232, a first value and a second value are determined according to the first block error rate and the number of coding blocks included in the first transmission block transmitted in the first time unit. The first value indicates the number of encoded blocks of decoding errors in the first transport block. The second number represents the number of correctly decoded coded blocks in the first transport block. Decoding is correct or incorrect, and may be determined based on Cyclic Redundancy Check (CRC) information.
The number of coding blocks included in the first transmission block may be determined according to factors such as the bandwidth of the communication system, the subcarrier spacing, the modulation scheme of the data, the number of layers to be transmitted, and the like. Taking the highest throughput rate scenario of NR FR1 as an example, in this scenario, the subcarrier spacing is 30KHz, the bandwidth is 100MHz, the modulation scheme is 256QAM, and the number of layers transmitted is 4, and then one transmission block corresponds to 152 coding blocks.
After the first block error rate is obtained and the number of the coding blocks contained in the first transmission block is obtained, the number of the coding blocks with decoding errors and the number of the coding blocks with correct decoding can be determined.
For example, if the first transport block includes 152 code blocks and the block error rate of the code block is P, the number of code blocks for checking errors is 152 × P, and the number of code blocks for checking correctness is 152 × P (1-P).
In step S234, the throughput rate of the memory in the first time unit is determined according to the first value and the second value. The throughput of the on-chip memory may be different in the first pass and retransmission scenarios. Therefore, in some embodiments, the type corresponding to the first transport block (indicating whether the first transport block performs initial transmission or retransmission) may be determined, and then the throughput rate of the memory in the first time unit may be determined according to the type corresponding to the first transport block, the first value, and the second value.
Taking the memory as DDR as an example, during the downlink receiving process, the following types of data need to perform read and write operations on DDR:
1. DDR writing of the soft bits of the physical layer (when the decoding of the coding block is wrong, the soft bits corresponding to the coding block are written into the DDR);
2. and reading DDR (in retransmission, soft bits corresponding to retransmitted data need to be read from DDR to an on-chip memory for soft bit combination).
3. And writing DDR (the data surface decrypts the correctly decoded coding block submitted by the physical layer, and writes the decrypted data into DDR) of the data after decryption.
4. A Packet Traffic Accelerator (PTA) reads the decrypted data from the DDR and sends the data to a higher layer.
5. And writing DDR (if a coding block is decoded incorrectly, the data plane temporarily stores the coding block which is decoded correctly and is behind the coding block to the DDR).
6. And DDR (the data plane reads the correctly decoded code blocks temporarily stored in the DDR to perform decryption operation, writes the decrypted data into the DDR and waits for PTA reading) is read by the data plane.
Of the above-mentioned six types of data, the data amount of the data of types 1, 2, 3, 5, and 6 may be statistically obtained by the physical layer, and the data amount of the data of type 4 may be statistically obtained by the data plane.
Referring to fig. 4 and 5, how to determine the actual throughput of the memory in the first time unit according to the first value and the second value in the initial transmission and the retransmission process will be described by taking the first transport block as TB0 and the memory as DDR as an example.
Fig. 4 is an exemplary diagram of an implementation of the method shown in fig. 2 in an initial transmission scenario. Timing 0 in fig. 4 represents the decoding timing. Timing 1 in fig. 4 represents the timing for writing data decrypted by the encoding block to the DDR. Timing 2 in fig. 4 represents the timing of data decrypted from the DDR read encode block. Timing 3 in fig. 4 represents the timing of soft bit write DDR of the encoding block. Timing 4 in fig. 4 represents the timing of the hard bit write DDR of the encoding block. T in FIG. 40Indicating the starting decoding time of TB 0.
Referring to fig. 4, when TB0 is initially transmitted, CB0, CB2 and CB3 check correctly, and the rest of the coding blocks check errors. CB0 decodes correctly, so at timing 1, the physical layer submits CB0 data to the data plane. The data plane decrypts CB0 and writes the decrypted data to the DDR. At timing 2, the data decrypted by PTA from DDR read CB0 is passed to higher layers. Due to the decoding error of the CB1, at the time sequence 3, the physical layer writes soft bits of the CB1 and CB4 to CB9 into DDR and waits for retransmission and combination.
The CB2 and the CB3 decode correctly, but the data plane does not perform decryption operations because of CB1 decoding errors. At timing 4, the data plane writes the hard bits of CB2 and CB3 to the DDR.
As can be seen from fig. 4, the correctly decoded encoded blocks are typically stored in the form of decrypted data or hard bit data, and the incorrectly decoded encoded blocks are typically stored in the form of soft bits. In order to facilitate HARQ merging, the coding blocks with decoding errors can be stored in an on-chip memory preferentially, and when the on-chip memory is full, the coding blocks with decoding errors left are written into the DDR. Of course, the coded block with decoding error can be directly written into the DDR. The present application does not limit the specific storage rule of the coding block with decoding error.
When data is initially transmitted, the data access amount of the DDR can be obtained by the following three formulas:
Minitial＝max(0，Nerror*n-Rleft)+Ncorrect*CBsize
wherein M isinitialData access amount of DDR at initial transmission, NerrorNumber of coding blocks for decoding errors, n for each codingNumber of bits, R, corresponding to soft bits of a code blockleftFor the remaining memory space of the on-chip memory, NcorrectFor decoding correct number of code blocks, CBsizeIs the coding block size.
Figure BDA0003354759100000131
Wherein n iscbIs the number of bits of the coding block, R is the code rate, nsoftThe number of bits per soft bit.
Rleft＝Rtotal*rmov-Roccupy
Wherein R istotalIs the total size of the on-chip memory storage space, rmovRepresenting the percentage of on-chip memory space that can be occupied (e.g., the remaining data may be stored in memory after 80% of on-chip memory is occupied, when rmovValue of (b) 80%), RoccupyIs the size of the storage space of the on-chip memory that has been occupied.
Fig. 5 is an exemplary diagram of an implementation of the method shown in fig. 2 in a retransmission scenario. Timing 5 in fig. 5 represents the decoding timing. Timing 6 in fig. 5 represents the timing of the encoded block soft bit write DDR. Timing 7 in fig. 5 represents the timing for writing data decrypted by the encoding block to the DDR. Timing 8 in fig. 5 represents the timing of the data decrypted from the DDR read encode block. Timing 9 in fig. 5 represents the timing of the hard bit write DDR of the encoding block. Timing 10 in fig. 5 represents the timing of the soft bits of the encoded block being read from the DDR to the on-chip memory. Timing 11 in fig. 5 represents the timing at which the hard bits of the encoded block are read out from the DDR. T in FIG. 51Indicating the starting decoding time of TB0 at the time of retransmission.
Referring to fig. 5, at timing 10, when the terminal receives the retransmitted TB0 data, it will be earlier than the decoding time t1The encoded blocks (for example, CB1 and CB4 to CB9) stored in DDR and decoded in error last time are read into an on-chip memory. After the coding block with decoding error is read into the on-chip memory, the coding block is merged with the received data of the retransmitted coding block(e.g., the data of CB1 with decoding errors is merged with the data of CB1 with retransmission).
The CB0, the CB2 and the CB3 are correctly decoded at the initial transmission, so that the decoding operation of the CB0, the CB2 and the CB3 is not needed after the retransmission.
During retransmission, the decoding of CB1 and CB4 is correct. The terminal hands CB1 and CB4 data from the physical layer to the data plane. After the data plane receives the data of CB1 and CB4, the data plane reads the data of CB2 and CB3 from the DDR at timing 11.
At timing 7, the data plane decrypts the data of CB1 to CB4, and writes the decrypted data into the DDR.
At timing 8, the data decrypted by PTA from DDR reading CB 1-CB 4 is transmitted to the upper layer. Wherein, the specific time for the PTA to read the data of CB 1-CB 4 from the DDR is uncertain.
The retransmitted CB5, CB6 and CB8 have decoded errors again. At timing 6, the physical layer writes the soft bits of CB5, CB6, CB8 to the DDR, waiting for retransmission combining.
The retransmitted CB7 and CB9 decode correctly. However, the data plane does not perform the decryption operation because the previous coding block decoded in error. The data plane writes the hard bits of CB7 and CB9 to the DDR at timing 9.
As can be seen from fig. 5, the hard bits stored in the form of data in the DDR code block need to be read from the DDR to the on-chip memory. And after the on-chip memory carries out decryption operation, the decrypted data is stored in the DDR. In this process, this portion of data needs to be read from and written to the DDR twice.
In the HARQ retransmission process, the data access amount of the DDR can be obtained by the following formula.
Mre＝nharq+Nerror*n+(Nsoft+Nhard*2-Nerror)*CBsize
Wherein M isreDDR data access for retransmission, nharqFor soft bit data volume moved from DDR to on-chip memory, NhardThe number of coded blocks stored as hard bits.
The throughput of the DDR is the ratio of the total amount of data read and written by the DDR to the time unit within a time unit (e.g., the duration of a time slot). The throughput rate of the DDR can be calculated according to the following formula:
C＝Mtotal/T
where C denotes DDR throughput, MtotalDenotes the total amount of data accessed to the DDR, and T denotes one time unit. The amount of data accessed to the DDR includes the amount of data read from the DDR and the amount of data written to the DDR.
After the current transmission type is determined, a predicted value of the DDR throughput rate can be obtained according to the formula.
Method embodiments of the present disclosure are described in detail above in conjunction with fig. 1-5, and apparatus embodiments of the present disclosure are described in detail below in conjunction with fig. 6-7. It is to be understood that the description of the method embodiments corresponds to the description of the apparatus embodiments, and therefore reference may be made to the preceding method embodiments for parts not described in detail.
Fig. 6 is a schematic structural diagram of an apparatus for configuring a memory according to an embodiment of the present application. The apparatus 600 of fig. 6 includes a prediction module 610 and a processing module 620.
The prediction module 610 is configured to predict a first channel condition parameter. The first channel condition parameter is used to indicate a channel condition of the terminal for a first time unit after a current time unit.
The processing module 620 is configured to determine a first block error rate of a coding block corresponding to the first channel condition parameter and the first modulation and coding strategy according to the first channel condition parameter, the first modulation and coding strategy configured by the terminal, and pre-stored mapping relationship information, where the mapping relationship information is used to indicate a mapping relationship among the channel condition parameter, the modulation and coding strategy, and the block error rate of the coding block; and determining the actual throughput rate of a memory of the terminal in the first time unit according to the first block error rate, wherein the memory is used for storing the data of the coding block contained in the first transmission block transmitted in the first time unit.
Optionally, the processing module 620 is configured to determine a first numerical value and a second numerical value according to the first block error rate and the number of coding blocks included in a first transmission block transmitted in the first time unit, where the first numerical value represents the number of coding blocks with decoding errors in the first transmission block, and the second numerical value represents the number of coding blocks with correct decoding in the first transmission block; and determining the throughput rate of the memory in the first time unit according to the first value and the second value.
Optionally, the processing module 620 is configured to determine a type corresponding to the first transport block, where the type corresponding to the first transport block indicates that the first transport block performs initial transmission or retransmission; and determining the throughput rate of the memory in the first time unit according to the type corresponding to the first transmission block, the first numerical value and the second numerical value.
Optionally, the predicting module 610 is configured to predict the first channel condition parameter according to a second channel condition parameter, where the second channel condition parameter is a channel condition parameter of the terminal in the current time unit.
Optionally, the processing module 620 is further configured to obtain the first modulation and coding strategy configured by the network device for the terminal from downlink control information before determining the first block error rate according to the first channel condition parameter, the first modulation and coding strategy configured by the terminal, and pre-stored mapping relationship information.
Optionally, the memory is DDR.
Optionally, the first channel condition parameter is SNR.
Optionally, the current time unit and the first time unit are two adjacent time slots.
Fig. 7 is a schematic structural diagram of a terminal according to an embodiment of the present application. The terminal of fig. 7 comprises a memory 710 and a processor 720, wherein the memory 710 is operable to store codes, and the processor 720 is operable to execute the codes stored in the memory 710 to perform the prediction method described in any of the previous embodiments.
It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be read by a computer or a data storage device including one or more available media integrated servers, data centers, and the like. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a Digital Versatile Disk (DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), among others.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (18)

1. A method for configuring a memory, comprising:
predicting a first channel condition parameter, wherein the first channel condition parameter is used for indicating the channel condition of the terminal in a first time unit after the current time unit;
determining a first block error rate of a coding block corresponding to the first channel condition parameter and a first modulation and coding strategy according to the first channel condition parameter, the first modulation and coding strategy configured by the terminal, and pre-stored mapping relationship information, wherein the mapping relationship information is used for indicating a mapping relationship among the channel condition parameter, the modulation and coding strategy, and the block error rate of the coding block;
and determining the throughput rate of a memory of the terminal in the first time unit according to the first block error rate, wherein the memory is used for storing the data of the coding block contained in the first transmission block transmitted in the first time unit.
2. The method of claim 1, wherein the determining the throughput rate of the memory of the terminal in the first time unit according to the first block error rate comprises:
determining a first numerical value and a second numerical value according to the first block error rate and the number of coding blocks contained in a first transmission block transmitted in the first time unit, wherein the first numerical value represents the number of coding blocks with decoding errors in the first transmission block, and the second numerical value represents the number of coding blocks with correct decoding in the first transmission block;
and determining the throughput rate of the memory in the first time unit according to the first value and the second value.
3. The method of claim 2, wherein determining the throughput rate of the memory at the first time unit based on the first value and the second value comprises:
determining a type corresponding to the first transport block, wherein the type corresponding to the first transport block indicates that the first transport block is subjected to initial transmission or retransmission;
and determining the throughput rate of the memory in the first time unit according to the type corresponding to the first transmission block, the first numerical value and the second numerical value.
4. The method of claim 1, wherein predicting the first channel condition parameter comprises:
and predicting the first channel condition parameters according to second channel condition parameters, wherein the second channel condition parameters are the channel condition parameters of the terminal in the current time unit.
5. The method of claim 1, wherein before determining the first block error rate according to the first channel condition parameter, the first modulation and coding scheme configured by the terminal, and the pre-stored mapping relation information, the method further comprises:
receiving downlink control information;
and acquiring the first modulation and coding strategy configured for the terminal by the network equipment from the downlink control information.
6. The method of claim 1, wherein the memory is a DDR.
7. The method of claim 1, wherein the first channel condition parameter is SNR.
8. The method of claim 1, wherein the current time unit and the first time unit are two adjacent time slots.
9. An apparatus for configuring a memory, comprising:
a prediction module configured to predict a first channel condition parameter, wherein the first channel condition parameter is used for indicating a channel condition of a terminal in a first time unit after a current time unit;
the processing module is configured to determine a first block error rate of a coding block corresponding to the first channel condition parameter and a first modulation and coding strategy configured by the terminal according to the first channel condition parameter, the first modulation and coding strategy configured by the terminal, and pre-stored mapping relationship information, where the mapping relationship information is used to indicate a mapping relationship among the channel condition parameter, the modulation and coding strategy, and the block error rate of the coding block; and determining the throughput rate of a memory of the terminal in the first time unit according to the first block error rate, wherein the memory is used for storing the data of the coding block contained in the first transmission block transmitted in the first time unit.
10. The apparatus according to claim 9, wherein the processing module is configured to determine a first value and a second value according to the first block error rate and a number of coded blocks included in a first transport block transmitted in the first time unit, wherein the first value represents a number of coded blocks with decoding errors in the first transport block, and the second value represents a number of coded blocks with decoding errors in the first transport block; and determining the throughput rate of the memory in the first time unit according to the first value and the second value.
11. The apparatus of claim 10, wherein the processing module is configured to determine a type corresponding to the first transport block, and wherein the type corresponding to the first transport block indicates whether the first transport block is initially transmitted or retransmitted; and determining the throughput rate of the memory in the first time unit according to the type corresponding to the first transmission block, the first numerical value and the second numerical value.
12. The apparatus of claim 9, wherein the prediction module is configured to predict the first channel condition parameter according to a second channel condition parameter, wherein the second channel condition parameter is a channel condition parameter of the terminal in the current time unit.
13. The apparatus of claim 9, wherein the processing module is further configured to obtain the first modulation and coding strategy configured by the network device for the terminal from downlink control information before determining the first block error rate according to the first channel condition parameter, the first modulation and coding strategy configured by the terminal, and pre-stored mapping relationship information.
14. The apparatus of claim 9, wherein the memory is a DDR.
15. The apparatus of claim 9, wherein the first channel condition parameter is SNR.
16. The apparatus of claim 9, wherein the current time unit and the first time unit are two adjacent time slots.
17. A terminal comprising a memory for storing code and a processor for executing the code stored in the memory to perform the method of any one of claims 1-8.
18. A computer-readable storage medium, characterized in that the computer-readable storage medium stores program code, which when executed, is configured to implement the method of any of claims 1-8.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116131997A (en) * 2022-12-30 2023-05-16 哲库科技(北京)有限公司 Method, device, chip, terminal and storage medium for wireless communication
WO2023082872A1 (en) * 2021-11-15 2023-05-19 Oppo广东移动通信有限公司 Memory configuration method and apparatus, and terminal

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100086088A1 (en) * 2008-10-02 2010-04-08 Qualcomm Incorporated Optimized finger assignment for improved multicarrier throughput
CN108599966A (en) * 2018-03-13 2018-09-28 山东超越数控电子股份有限公司 A kind of net peace equipment power dissipation dynamic debugging system and method
WO2018228579A1 (en) * 2017-06-16 2018-12-20 华为技术有限公司 Method and apparatus for determining transport block size

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101207553B (en) * 2006-12-18 2010-12-08 中兴通讯股份有限公司 Method for determining transmission block size in high speed downlink grouping switch-in business
WO2012149781A1 (en) * 2011-09-29 2012-11-08 华为技术有限公司 Method and apparatus for controlling block error rate
EP3783985B1 (en) * 2018-05-16 2023-08-02 Huawei Technologies Co., Ltd. Data transmission method and device
CN113472480B (en) * 2020-03-31 2022-09-27 维沃移动通信有限公司 Transmission processing method and equipment
CN114138099A (en) * 2021-11-15 2022-03-04 Oppo广东移动通信有限公司 Method, device and terminal for configuring memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100086088A1 (en) * 2008-10-02 2010-04-08 Qualcomm Incorporated Optimized finger assignment for improved multicarrier throughput
WO2018228579A1 (en) * 2017-06-16 2018-12-20 华为技术有限公司 Method and apparatus for determining transport block size
CN108599966A (en) * 2018-03-13 2018-09-28 山东超越数控电子股份有限公司 A kind of net peace equipment power dissipation dynamic debugging system and method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023082872A1 (en) * 2021-11-15 2023-05-19 Oppo广东移动通信有限公司 Memory configuration method and apparatus, and terminal
CN116131997A (en) * 2022-12-30 2023-05-16 哲库科技(北京)有限公司 Method, device, chip, terminal and storage medium for wireless communication

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