CN109412607B - Decoding method and device - Google Patents
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- CN109412607B CN109412607B CN201710700352.1A CN201710700352A CN109412607B CN 109412607 B CN109412607 B CN 109412607B CN 201710700352 A CN201710700352 A CN 201710700352A CN 109412607 B CN109412607 B CN 109412607B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
- H04L1/0063—Single parity check
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Abstract
The disclosure provides a decoding method and a decoding device, and belongs to the technical field of decoding. The method comprises the following steps: when the current decoded bit is a PC-freezing bit and the decoding result of the bit in any decoding path does not pass the verification, determining at least one decoded target information bit in the decoding path; turning over the decoding result of the target information bit from the first target information bit, and retreating to the target information bit in the decoding path for re-decoding, wherein the decoding result obtained by the bit re-decoding is checked every time the turning over and the retreating decoding are carried out once, and when the checking is not passed, the turning over and the retreating decoding are continuously carried out on the next target information bit; and when at least one target information bit is subjected to the turning and backspacing decoding and the decoding result of the bit re-decoding does not pass the check, increasing the number of decoding paths and continuing to decode. The number of decoding paths is adjusted in the decoding process, and the decoding time delay is greatly shortened.
Description
Technical Field
The present disclosure relates to the field of decoding technologies, and in particular, to a decoding method and apparatus.
Background
Polar (Polar) codes are a coding method that has been theoretically proven to achieve channel capacity, and Polar codes can be decoded by a Sequential Cancellation List (SCL) decoding algorithm. The number of decoding paths (number of LIST) is an important parameter of the SCL decoding algorithm, and the decoding performance of the SCL decoding algorithm is improved as the number of LIST increases, however, the improvement of the number of LIST leads to the increase of the decoding complexity. Therefore, in the actual decoding process, the number of LIST needs to be adjusted for decoding, so as to obtain a trade-off between complexity and performance.
At present, the following scheme is adopted to adjust the number of LIST for decoding:
1. setting an upper limit L of the number L of LISTs max ；
2. Initializing L-1;
3. decoding by using an SCL decoding algorithm, and performing Cyclic Redundancy Check (CRC) on L decoding paths with the maximum Path Metric (PM) value after decoding is completed;
4. if at least one decoding path passes the CRC check, outputting a path hard value (bit sequence) of the decoding path with the minimum PM value in the at least one decoding path, and ending decoding; otherwise, executing the step 5;
5. increasing L by two times, if L is less than or equal to L max If yes, executing step 3; otherwise, outputting the path hard value of the decoding path with the minimum PM value in all the decoding paths, and ending the decoding.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
according to the scheme, CRC check can be carried out only after one-time decoding is finished, whether the number of the LISTs is adjusted or not is determined according to a check result, so that the adjusting period of the number of the LISTs is longer, the number of the LISTs meeting the expected performance can be achieved only in a longer time, and the decoding time is prolonged.
Disclosure of Invention
In order to solve the problems in the prior art, the embodiments of the present disclosure provide a decoding method and apparatus. The technical scheme is as follows:
in a first aspect, a decoding method is provided, and the method includes:
when the currently decoded bits are Parity-Check (PC) -frozen bits and the decoding result of the bits in any decoding path does not pass the Check, determining at least one decoded target information bit in the decoding path, wherein the target information bit is an information bit which has a difference of a specified bit from the bit position, and the specified bit is an integral multiple of the shift period of the cyclic shift register;
starting from the first target information bit in the at least one target information bit, turning over the decoding result of the target information bit, and retreating to the target information bit in the decoding path for decoding again, checking the decoding result obtained by the bit through decoding again every time the turning over and retreating decoding is carried out, and continuing to turn over and retreat for decoding the next target information bit when the checking is not passed;
and when the at least one target information bit is subjected to the turning-over and backspacing decoding and the decoding result of the bit passing the re-decoding does not pass the check, increasing the number of decoding paths and continuing decoding.
The PC-freeze bit is a bit used for checking the bit error rate, for example, when the decoding result of the PC-freeze bit does not pass the check, it indicates that the bit error rate is high, and if the decoding result passes the check, it indicates that the bit error rate is low.
In the method provided by the embodiment of the disclosure, in the decoding process, if the currently decoded bit is the PC-frozen bit and the decoding result of the PC-frozen bit does not pass the verification, the decoding result of the PC-frozen bit re-decoding is verified after each time of the back-off decoding by turning over and back-off decoding one information bit influencing the PC-frozen bit verification result, and if the verification does not pass each time, the current error rate is higher. Compared with the prior art that the number of the decoding paths can be adjusted only after all bits are decoded, the number of the decoding paths is adjusted in a shorter period in the present disclosure, so that the number of the decoding paths meeting the expected performance can be achieved in a shorter time, and the decoding time delay is greatly shortened.
In a first possible implementation manner of the first aspect, the determining at least one target information bit coded in the coding path includes:
determining a plurality of information bits between the bit and a PC-freeze bit preceding the bit;
and acquiring information bits meeting a specified relational expression from the plurality of information bits as the at least one target information bit.
The method provided by the embodiment of the disclosure acquires the information bit satisfying the specified relation between the current PC-freeze bit and the previous PC-freeze bit as at least one target information bit related to the current PC-freeze bit, and provides a way to acquire the target information bit.
In a second possible implementation manner of the first aspect, the increasing the number of the decoding paths and continuing decoding includes:
adjusting the number of current decoding paths to a smaller value of a first path number and a second path number, wherein the first path number is twice of the current decoding paths, and the second path number is a preset maximum path number;
all decoding paths are returned to the first target information bit in the at least one target information bit for decoding again.
According to the method provided by the embodiment of the disclosure, when the check passing rate of the PC-freezing bit is low, the bit error rate is high, and the decoding performance is poor, at the moment, the number of the decoding paths is increased, so that the number of the decoding paths approaches to the maximum value, and the decoding performance can be ensured.
In a third possible implementation manner of the first aspect, the method further includes:
when the decoding result obtained by the bit re-decoding passes the verification after each time of the turning and the rollback decoding, ending the turning and the rollback decoding process;
and taking the overturning result of the overturned target information bit as the decoding result of the overturned target information bit.
The inversion result is obtained by inverting the decoding result of the target information bit, and if the decoding result of the target information bit is 0, the inversion result is 1.
In the method provided by the embodiment of the present disclosure, if a decoding result of the re-decoding of the PC-frozen bit passes verification after performing the flipping and rollback decoding on one target information bit of the at least one target information bit, the electronic device may end the flipping and rollback decoding process, and use the flipped result as the decoding result of the target information bit, thereby providing a timing for ending the flipping and rollback decoding process.
In a fourth possible implementation manner of the first aspect, the method further includes:
when the decoding results of the bits in all the decoding paths pass the verification, adjusting the number of the current decoding paths to be the larger value of the number of the third paths and the number of the fourth paths, and continuing decoding, wherein the number of the third paths is half of the number of the current decoding paths, and the number of the fourth paths is the preset minimum value of the number of the paths.
According to the method provided by the embodiment of the disclosure, when the check pass rate of the PC-freezing bit is high, the bit error rate is low, and at the moment, the number of decoding paths is reduced to be close to the minimum value, so that the decoding complexity can be reduced, and the decoding speed is ensured.
In a second aspect, a decoding apparatus is provided, which includes a plurality of functional modules, and the functional modules are configured to execute the decoding method provided in the first aspect and any possible implementation manner thereof.
In a third aspect, an electronic device is provided, which includes a processor and a memory, where at least one instruction, at least one program, a set of codes, or a set of instructions is stored in the memory, and the at least one instruction, the at least one program, the set of codes, or the set of instructions is loaded and executed by the processor to implement the decoding method provided in the first aspect or any one of the possible implementation manners of the first aspect.
In a fourth aspect, a computer-readable storage medium is provided, in which at least one instruction, at least one program, code set, or instruction set is stored, and the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the decoding method provided in the first aspect or any one of the possible implementation manners of the first aspect.
Drawings
Fig. 1 is a schematic structural diagram of an electronic device 100 according to an embodiment of the present disclosure.
Fig. 2 is a flowchart of a decoding method according to an embodiment of the disclosure.
Fig. 3 is a schematic diagram illustrating path selection of an SCL decoding algorithm according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of a decoding apparatus according to an embodiment of the disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
In the method provided by the embodiment of the present disclosure, the execution subject of each step may be an electronic device, such as a receiving end of information in a communication system. For example, the electronic device may be a base station, a mobile terminal, or other devices with decoding functions. For convenience of description, in the following embodiments, only the execution subject of each step is taken as an example of an electronic device.
When a sending end in a communication system needs to send information to an electronic device, the information can be encoded by a polarization code to generate a bit sequence, the bit sequence is composed of a plurality of bits, and the value of each bit is 0 or 1. The bits may be of three types, such as an information bit, a freeze bit, and a PC-freeze bit, wherein the information bit is a bit having an information amount, and the freeze bit and the PC-freeze bit are bits having no information amount.
There are multiple channels between the transmitting end and the electronic device, and each bit in a bit sequence corresponds to a channel. When a transmitting end transmits a bit sequence to an electronic device, each bit in the bit sequence is respectively input to a channel corresponding to each bit. The electronic device may receive the bits from the channels, where the bits are bit sequences to be decoded of the electronic device, and the electronic device may decode the bits to obtain the bit sequences sent by the sending end on the channels, that is, obtain decoding results of the bit sequences to be decoded. The embodiment of the disclosure aims at the problems of long regulation period of the number of decoding paths and prolonged decoding time in the prior art, and the technical scheme provided by the disclosure is to verify the decoding result of the PC-frozen bits in the decoding process and regulate the number of the decoding paths according to the verification result without regulating after all bits are completely decoded.
Fig. 1 is a schematic structural diagram of an electronic device 100 according to an embodiment of the present disclosure. Referring to fig. 1, the electronic device 100 includes a processor and a memory, wherein at least one instruction, at least one program, a set of codes, or a set of instructions is stored in the memory, and the at least one instruction, the at least one program, the set of codes, or the set of instructions is loaded and executed by the processor to implement the decoding method in the embodiment of fig. 2. The system also comprises a communication interface, a bus, an input/output interface and a display device, wherein the processor, the memory, the input/output interface, the display device and the communication interface are communicated with each other through the bus.
The memory may include high-speed random access memory (as a cache) and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory may also include a memory controller to provide the processor and the input output interface access to the memory. A bus is a circuit that connects the described elements and enables transmission between these elements. For example, the processor receives commands from other elements through the bus, decodes the received commands, and performs calculations or data processing according to the decoded commands. The memory may include program modules such as a kernel (kernel), middleware (middleware), an Application Programming Interface (API), and applications. The program modules may be comprised of software, firmware or hardware, or at least two of the same. The input-output interface forwards commands or data input by a user through an input-output device (e.g., a sensor, a keyboard, a touch screen). The display device displays various information to a user. The communication interface connects the electronic device 100 with other network devices, user devices, networks. For example, the communication interface may be connected to the network by wire or wirelessly to connect to external other network devices or user equipment. The wireless communication may include at least one of: wireless Fidelity (WiFi), Bluetooth (BT), Near Field Communication (NFC), Global Positioning System (GPS) and cellular Communication (cellular Communication) (e.g., Long Term Evolution (LTE)), Long Term Evolution (Long Term Evolution) followed by Long Term Evolution (LTE-Advanced), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (CDMA, WCDMA), Universal Mobile telecommunications System (Universal Mobile telecommunications System, UMTS), Wireless Broadband Access (Wireless Broadband bro) and Global System for Mobile communications (GSM) may include at least one of the following Wireless Communication systems (WiFi), Wireless Multimedia Communication (Bluetooth, BT), Wireless Broadband Communication (GSM), Wireless Serial Communication (GSM), Wireless Multimedia Communication (HDMI, GSM), RS-232), and Plain Old Telephone Service (POTS). The network may be a telecommunications network and a communications network. The communication network may be a computer network, the internet of things, a telephone network. The electronic device 100 may be connected to a network through a communication Interface, and a protocol used for the electronic device 100 to communicate with other network devices may be supported by at least one of an Application, an Application Programming Interface (API), middleware, a kernel, and a communication Interface.
In an exemplary embodiment, a computer readable storage medium is also provided, such as a memory including at least one instruction, at least one program, set of codes, or set of instructions that may be loaded and executed by a processor to perform the decoding method in the fig. 2 embodiment described below. For example, the computer-readable storage medium may be a Read-Only Memory (ROM), a Random-Access Memory (RAM), a Compact Disc Read-Only Memory (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, and the like.
Fig. 2 is a flowchart illustrating a decoding method according to an embodiment of the disclosure. The decoding method is applied to the electronic device, and referring to fig. 2, the decoding method may include:
201. and setting the maximum value and the minimum value of the number of decoding paths in the SCL decoding algorithm.
For the SCL decoding algorithm, the larger the number of decoding paths, the higher the decoding performance of the SCL decoding algorithm, but at the same time, the decoding complexity will increase and the decoding delay will increase; the smaller the number of decoding paths, the lower the complexity of the SCL decoding algorithm and the shorter the decoding delay, but at the same time, the decoding performance may be degraded. To achieve a tradeoff between complexity and performance, the electronic device may dynamically adjust the number of decoding paths during the decoding process.
In the embodiment of the disclosure, in order to avoid two extreme cases that the decoding complexity is too high due to too large number of decoding paths or the decoding performance is too low due to too small number of decoding paths, before the electronic device starts decoding, for the number L of decoding paths, the maximum value of L may be set to L max Minimum value of L min . When the electronic device starts decoding, L can be set to be equal to 1, and the value of L is adjusted according to the actual decoding condition in the decoding process. The value of L is less than L min In time, the electronic device may continue to split, i.e., all decoding paths are retained in the decoding process until the number of decoding paths reaches L min Thereafter, the decoding is continued according to the subsequent steps 202 to 206.
202. And decoding the bit sequence to be decoded by using an SCL decoding algorithm to obtain a decoding result of the currently decoded bit.
The bit sequence to be decoded comprises a plurality of bits to be decoded, the electronic device can decode one of the plurality of bits to be decoded, and each pair of bits is decoded, so that the bit is the currently decoded bit. The currently decoded bit may be any one of an information bit, a freeze bit or a PC-freeze bit, the decoding result of each bit may be a value of the bit decided by the SCL decoding algorithm, and the decoding result of each bit may be 0 or 1.
In this embodiment of the present disclosure, for each bit in a bit sequence sent by a sending end, an electronic device may decode by using an SCL decoding algorithm, and after each decoding, the electronic device may select, according to the number of current decoding paths, a decoding path that retains the largest PM value from all the decoding paths, where the number of the decoding paths is the same as the number of the current decoding paths. The PM value may be used to indicate the probability that the decoding results of the decoded bits on the decoding path are all correct, and the PM value may be calculated by using an SCL decoding algorithm.
Referring to fig. 3, a schematic diagram of the path selection of the SCL decoding algorithm is provided. The decoder of the electronic device firstly decodes from a root node, expands the root node according to the bit of 0 or 1, sequences the decoding paths after expansion according to the size of the PM value, then reserves the L decoding paths with the maximum PM value, and deletes other decoding paths. As shown in fig. 2, when decoding proceeds to the second layer, two decoding paths, i.e., a left decoding path having a PM value of 0.60 and indicating that the probability of the true value of the first bit is 0.60, and a right decoding path having a PM value of 0.40 and indicating that the probability of the true value of the first bit is 1 is 0.40, occur, and if L is 2, the two decoding paths are retained. When the decoding is performed to the third layer, four decoding paths appear, and the PM values from left to right are 0.33, 0.27, 0.30 and 0.20 respectively, two decoding paths with PM values of 0.33 and 0.30 are reserved for continuing the decoding, as shown by the solid line in the figure, two decoding paths with PM values of 0.27 and 0.20 are deleted, and the subsequent decoding process is not continued, as shown by the dotted line in the figure.
203. When the current decoded bit is a PC-freezing bit and the decoding result of the bit in any decoding path does not pass the check, determining at least one decoded target information bit in the decoding path, wherein the target information bit is an information bit which has a difference of a specified bit from the bit position, and the specified bit is an integral multiple of the shift period of the cyclic shift register.
In the embodiment of the present disclosure, in the process of decoding, the electronic device may adopt different processing strategies for different types of currently decoded bits, for example, when the currently decoded bits are information bits or frozen bits, the electronic device may not adjust the number of paths, that is, keep the current number of paths L unchanged; when the current decoded bit is a PC-freeze bit, the electronic device may check the decoding result of the PC-freeze bit, and adjust the number of decoding paths in the decoding process according to the check result, where the specific adjustment process may include steps 203 to 206. In step 203 to step 205, there is a case that the PC-freeze bit in at least one decoding path does not pass the check, and in step 206, the PC-freeze bit in all decoding paths passes the check.
When the currently decoded bit is a PC-freeze bit, the electronic device may check the decoding result of the PC-freeze bit, such as a PC check, after decoding the PC-freeze bit in each decoding path to obtain a decoding result. The verification result may include passing and failing to pass the verification, and in the PC verification, the verification result may be represented by numbers 0 and 1, for example, when the verification result is 0, it represents passing, and when the verification result is 1, it represents failing to pass. The process of PC verification may include: inputting the decoding result of the information bit decoded before the PC-freezing bit into the PC circuit for calculation to obtain a check result output by the PC circuit, namely the check result of the PC-freezing bit, then comparing the check result of the PC-freezing bit with the decoding result of the PC-freezing bit, and if the check result is the same as the decoding result of the PC-freezing bit, passing the check.
According to the working principle of the PC circuit, when the current decoded bit is a frozen bit, the cyclic shift circuit only shifts; when the bit is a PC-freezing bit, the cyclic shift circuit outputs the value of the first bit register as a check value and shifts; when the information bit is used, the value of the first bit register is updated by using the decoding result of the information bit. It can be considered that when the length of the circular shift register is S (S is a prime number, corresponding to the shift period of the circular shift register), a certain PC-freeze bit only checks the information bit which is different from the PC-freeze bit by nS bits in position among the previous information bits, i.e., the target information bit, where n is a positive integer.
In step 203, if the decoding result of the PC-freeze bit in any one of the decoding paths does not pass the check, the electronic device may determine at least one target information bit related to the PC-freeze bit in the decoding path. In one possible implementation, the electronic device determining the decoded at least one target information bit in the decoding path may include: determining a plurality of information bits between the PC-freeze bit and a previous PC-freeze bit; and acquiring information bits meeting a specified relational expression from the plurality of information bits as the at least one target information bit. All bits between the PC-freeze bit and the previous PC-freeze bit may include an information bit, a freeze bit, and a PC-freeze bit, from which the electronic device may sift out at least one target information bit by definition of a bit type and a specified relationship.
Wherein the specified relation may be formula (1):
wherein, I i Refers to the index value of the information bit; s is the length of the circular shift register (S is a prime number); i is an index value of a bit, and the value is 1 to N; in p Index value (In) referring to the current PC-freeze bit p Values 1 to N, p is the index value of the current PC-freeze bit starting from 1 among all PC-freeze bits).
204. And starting from the first target information bit in the at least one target information bit, turning over the decoding result of the target information bit, and retreating to the target information bit in the decoding path for decoding again, checking the decoding result obtained by the bit after decoding again every time the turning over and the retreating decoding are carried out, and continuing to turn over and retreat for decoding the next target information bit when the checking is not passed.
In the embodiment of the present disclosure, the decoding result of the decoded target information bit may affect the decoding result of the currently decoded PC-frozen bit, thereby affecting the checking result of the PC-frozen bit. The check result of the PC-freeze bit and the decoding result of the at least one target information bit may satisfy equation (2):
wherein, P p The check result (e.g., 0 or 1) for the p-th PC-freeze bit; p p-1 The check result for the p-1 st PC-freeze bit; u. of m ，u m+1 ，……，u n For the decoding result (e.g., 0 or 1) of the information bit satisfying equation (1) between the two PC-freeze bits.
As can be seen from equation (2), if the PC-freeze bit immediately preceding the PC-freeze bit passes the check, but the PC-freeze bit does not pass the check, the bit that results in the PC-freeze bit not passing the check exists only in u m ，u m+1 ，……，u n Independent of the information bit preceding the previous PC-freeze bit, only the information bit between these two PC-freeze bits. Since S is always an odd number, u can be considered m ，u m+1 ，……，u n Most likely to have 1 bit decoding error. Therefore, the electronic device may try to flip the decoding results of the at least one target information bit one by one, and fall back to the currently flipped target information bit for re-decoding, obtain the decoding result of the PC-freeze bit re-decoding, and check the decoding result.
It should be noted that, in step 204, when the decoding result obtained by re-decoding the bit fails to pass the verification after each time of decoding is turned and backed off, the electronic device continues the process of turning over and backing off the decoding. In a possible implementation manner, when the decoding result obtained by re-decoding the bit passes verification after each time of the flipping and rollback decoding, the electronic device may end the flipping and rollback decoding process, and use the flipping result of the flipped target information bit as the decoding result of the flipped target information bit.
In the embodiment of the present disclosure, the process of the electronic device performing the flipping and rolling-back decoding on the at least one target information bit may be as follows: the electronic device may first flip the existing decoding result of the first target information bit, for example, if the existing decoding result of the first target information bit is 0, the electronic device may flip the decoding result to 1. Then, the electronic device may fall back to the first target information bit in the decoding path of step 203 to decode again, that is, decode bits after the first target information bit again, so as to obtain the decoding result of the PC-freeze bit re-decoding in step 203. At this time, the electronic device may check the decoding result of the PC-freeze bit re-decoding, and if the check is passed, the electronic device may end the flipping and fallback decoding process, that is, the electronic device does not perform the flipping and fallback decoding on the target information bit subsequent to the first target information bit any more, and at this time, the electronic device may use the flipping result (e.g., 1) of the first target information bit as the decoding result of the first target information bit; if the check is not passed, the electronic device may perform the same process on the second target information bit as the first target information bit, and so on, and the electronic device may perform the same process on the other target information bits.
As can be seen from the above procedure of the roll-over and rollback decoding, the following two situations may exist when the electronic device finishes the roll-over and rollback decoding procedure:
in the first case, after the electronic device performs the flipping and rollback decoding on one target information bit of the at least one target information bit, the decoding result of the PC-freeze bit re-decoding passes the verification, and then the electronic device may end the flipping and rollback decoding process. In this case, the electronic device may end the flipping and rollback process without flipping all the target information bits, and may use the flipped result of the target information bits flipped before the end as the decoding result of the target information bits without adjusting the number of decoding paths.
In a second case, after the electronic device performs the roll-over and roll-back decoding on all of the at least one target information bit, the decoding result of the PC-frozen bit re-decoding still does not pass the check, and the electronic device may end the roll-over and roll-back decoding process and perform the following step 205. This situation provides another opportunity to end the flipping and rolling-back decoding process, in this case, in the flipping and rolling-back decoding process of the at least one target information bit, it may not pass the check each time, that is, after all the at least one target information bit are flipped and rolled back for decoding, the decoding result of the PC-frozen bit still cannot pass the check.
205. And when the at least one target information bit is subjected to the turnover and backspacing decoding and the decoding result of the bit passing the re-decoding does not pass the check, increasing the number of decoding paths and continuing to decode.
The step 205 is directed to the second situation in the step 204, if the electronic device ends the flipping and rollback decoding process in this situation, which indicates that the current error rate is high, the check pass rate of the PC-frozen bits is low, and the decoding performance is poor. At this time, the electronic device may adjust the number of decoding paths to improve decoding performance and improve the check pass rate of the PC-freeze bit.
In one possible implementation, the electronic device adjusting the number of decoding paths may include: and adjusting the number of the current decoding paths to be a smaller value of a first path number and a second path number, wherein the first path number is twice of the current decoding paths, and the second path number is a preset maximum path number. The number of the first paths and the number of the second paths are both larger than the number of the current decoding paths, and the adjustment also increases the number of the decoding paths. When the check passing rate of the PC-freezing bit is low, the error rate is high, the decoding performance is poor, and at the moment, the number of the decoding paths approaches to the maximum value by adjusting the number of the decoding paths to be large, so that the decoding performance can be ensured.
Since the number of decoding paths changes, and the number of decoding paths reserved after each bit is decoded changes, the electronic device needs to decode again according to the number of decoding paths after changing. As can be seen from step 204, the bit that caused the PC-freeze bit to fail the check is only present in the at least one target information bit, so the electronic device can retrace all decoding paths to the first target information bit in the at least one target information bit. When the number of decoding paths changes, only the target information bit affecting the PC-freezing bit check result is returned for decoding again, and the decoding result of the decoded bit before the target information bit is kept unchanged, so that the whole decoding process can be prevented from being performed again, and unnecessary decoding time delay is avoided. When the error rate is higher, the number of decoding paths can be quickly adjusted through the feedback of the check result, the decoding is not required to be repeated from the beginning, and the decoding is repeated only by returning to the first target information bit related to the PC-freezing bit, so that the convergence speed of the algorithm is increased, and the problem of overlong decoding delay is solved.
The above steps 203 to 205 are processes of the electronic device performing the flipping and the rollback decoding on at least one target information bit affecting the PC-frozen bit check result when the currently decoded bit is the PC-frozen bit and the decoding result of the PC-frozen bit in any decoding path does not pass the check. In fact, when the currently decoded bit is the PC-freeze bit, it is possible that the decoding results of the PC-freeze bit in all decoding paths pass the verification, and then the electronic device may perform the subsequent step 206.
206. When the decoding results of the bits in all decoding paths pass the check, the number of the decoding paths is adjusted and the decoding is continued.
In the embodiment of the disclosure, if the decoding results of the PC-frozen bits in all decoding paths pass the verification, it indicates that the current bit error rate is low, the verification pass rate of the PC-frozen bits is high, the decoding performance is high, but the decoding complexity is high, and the decoding time is prolonged. At this time, the electronic device may adjust the number of decoding paths to reduce the decoding complexity and shorten the decoding delay.
In one possible implementation, the electronic device adjusting the number of decoding paths may include: and adjusting the number of the current decoding paths to be a larger value of a third path number and a fourth path number, wherein the third path number is half of the number of the current decoding paths, and the fourth path number is a preset minimum value of the path number. The number of the third paths and the number of the fourth paths are both smaller than the number of the current decoding paths, and the adjustment reduces the number of the decoding paths. When the check pass rate of the PC-freezing bit is high, the error rate is low, and at the moment, the number of the decoding paths is reduced to enable the number of the decoding paths to be close to the minimum value, so that the decoding complexity can be reduced, and the decoding speed is ensured.
Because the number of decoding paths changes, and the number of decoding paths reserved after each bit is decoded changes, the electronic equipment can continue decoding from the PC-freezing bit according to the number of the adjusted decoding paths. After all bits in the bit sequence are decoded, the electronic device can sequence the L decoding paths, select one decoding path with the maximum PM value as a correct decoding path, and combine the decoding results of each bit in the decoding path into a bit sequence to be output, thereby completing the decoding process.
Of course, when the currently decoded bit is a PC-freeze bit, it is also possible that the decoding results of the PC-freeze bit in all decoding paths do not pass the verification, and each decoding path ends the flipping and rollback process in the second situation in step 204, which indicates that the error rate is too high and the decoding performance is too low, and at this time, the electronic device may consider that the decoding fails and directly end the SCL decoding algorithm.
In the method provided by the embodiment of the disclosure, in the decoding process, if the currently decoded bit is the PC-frozen bit and the decoding result of the PC-frozen bit does not pass the verification, the decoding result of the PC-frozen bit re-decoding is verified after each time of the back-off decoding by turning over and back-off decoding one information bit influencing the PC-frozen bit verification result, and if the verification does not pass each time, the current error rate is higher. Compared with the prior art that the number of the decoding paths can be adjusted only after all bits are decoded, the number of the decoding paths is adjusted in a shorter period in the present disclosure, so that the number of the decoding paths meeting the expected performance can be achieved in a shorter time, and the decoding time delay is greatly shortened.
In addition, the number of the decoding paths is provided with a maximum value and a minimum value, when the error rate is low, the PC-frozen bit check pass rate is high, and the number of the decoding paths is close to the minimum value by reducing the number of the decoding paths, so that the decoding complexity is reduced, and the decoding speed is ensured; when the error rate is high and the check passing rate of the PC-freezing bit is low, the number of the decoding paths is increased to approach the maximum value so as to ensure the decoding performance.
In addition, in the decoding process, the currently decoded bits are checked, the number of decoding paths is adjusted according to the check result, when the error rate is high, the number of decoding paths can be quickly adjusted through feedback of the check result, repeated re-decoding is not needed, and only the first target information bit related to the PC-freezing bit needs to be returned for re-decoding, so that the convergence speed of the algorithm is increased, and the problem of overlong decoding delay is solved.
Fig. 4 is a schematic structural diagram of a decoding apparatus according to an embodiment of the disclosure. Referring to fig. 4, the apparatus includes a determination module 401, a decoding module 402, and an adjustment module 403.
A determining module 401, configured to determine at least one decoded target information bit in a decoding path when a currently decoded bit is a PC-freeze bit and a decoding result of the bit in any decoding path does not pass verification, where the target information bit is an information bit that differs from the bit position by a specified bit, and the specified bit is an integer multiple of a shift period of a cyclic shift register;
a decoding module 402, configured to turn over a decoding result of a target information bit from a first target information bit in the at least one target information bit, and perform decoding again after going back to the target information bit in the decoding path, check a decoding result obtained by the bit through re-decoding each time the turning-over and back-back decoding is performed, and continue to turn over and back-back decode a next target information bit when the bit does not pass the checking;
an adjusting module 403, configured to adjust the number of decoding paths and continue decoding when all the at least one target information bit is subjected to the inverse and fallback decoding and a decoding result of the bit passing the re-decoding fails to pass the check.
In a possible implementation manner, the determining module 401 is configured to perform the process of acquiring, as the at least one target information bit, an information bit satisfying a specified relation from among a plurality of information bits between the PC-freeze bit and a previous PC-freeze bit in step 203.
In a possible implementation manner, the adjusting module 403 is configured to perform a process of rewinding all decoding paths to the first target information bit of the at least one target information bit for re-decoding after adjusting the number of current decoding paths in step 205.
In a possible implementation manner, the decoding module 402 is further configured to execute the process of ending the rolling-over and rolling-back decoding when a decoding result obtained by the PC-frozen bit re-decoding passes verification after any rolling-over and rolling-back decoding in step 204.
In a possible implementation manner, the adjusting module 403 is further configured to perform a process of adjusting the number of current decoding paths in step 206 when the decoding results of the PC-freeze bits in all decoding paths pass the check.
In the embodiment of the disclosure, in the decoding process, if the currently decoded bit is a PC-frozen bit and the decoding result of the PC-frozen bit does not pass the verification, the decoding result of the PC-frozen bit re-decoding is verified after each time of the back-off decoding by turning over and back-off decoding one by one information bit affecting the PC-frozen bit verification result, and if the verification does not pass each time, the current error rate is high. Compared with the prior art that the number of the decoding paths can be adjusted only after all bits are decoded, the number of the decoding paths in the method is adjusted in a shorter period, so that the number of the decoding paths meeting the expected performance can be achieved in a shorter time, and the decoding time delay is greatly shortened.
It should be noted that: in the decoding apparatus provided in the above embodiment, only the division of the above functional modules is used for illustration when decoding, and in practical applications, the above functions may be distributed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the above described functions. In addition, the decoding apparatus and the decoding method provided in the above embodiments belong to the same concept, and specific implementation processes thereof are described in the method embodiments and are not described herein again.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The above description is intended only to illustrate the preferred embodiments of the present disclosure, and should not be taken as limiting the disclosure, as any modifications, equivalents, improvements and the like which are within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (12)
1. A method of decoding, the method comprising:
when the currently decoded bit is a parity check PC-freezing bit and the decoding result of the bit in any decoding path does not pass the check, determining at least one decoded target information bit in the decoding path, wherein the target information bit is an information bit which has a difference of a specified bit from the bit position, and the specified bit is an integral multiple of the shift period of the cyclic shift register;
starting from the first target information bit in the at least one target information bit, turning over the decoding result of the target information bit, and retreating to the target information bit in the decoding path for decoding again, checking the decoding result obtained by the bit through decoding again every time the turning over and retreating decoding is carried out, and continuing to turn over and retreat for decoding the next target information bit when the checking is not passed;
and when the at least one target information bit is subjected to the turning and backspacing decoding and the decoding result of the bit passing the re-decoding does not pass the check, increasing the number of decoding paths and continuing decoding.
2. The method of claim 1, wherein the determining at least one target information bit coded in the coding path comprises:
determining at least one information bit between the bit and a previous parity PC-freeze bit of the bit;
acquiring information bits meeting a specified relational expression from the at least one information bit as the at least one target information bit;
the specified relation is
Wherein, I i Is the index value of the information bit, S is the length of the circular shift register, I is the index value of the bit, In p Refers to the index value of the current PC-freeze bit.
3. The method of claim 1, wherein increasing the number of decoding paths and continuing decoding comprises:
adjusting the number of current decoding paths to a smaller value of a first path number and a second path number, wherein the first path number is twice of the current decoding paths, and the second path number is a preset maximum path number;
and all decoding paths are retreated to the first target information bit in the at least one target information bit for decoding again.
4. The method of claim 1, further comprising:
when the decoding result obtained by the bit re-decoding passes the verification after each time of the turning and the rollback decoding, ending the turning and the rollback decoding process;
and taking the overturning result of the overturned target information bit as the decoding result of the overturned target information bit.
5. The method of claim 1, further comprising:
when the decoding results of the bits in all the decoding paths pass the verification, adjusting the number of the current decoding paths to be the larger value of the number of the third paths and the number of the fourth paths, and continuing to decode, wherein the number of the third paths is half of the number of the current decoding paths, and the number of the fourth paths is the preset minimum value of the number of the paths.
6. An apparatus for decoding, the apparatus comprising:
a determining module, configured to determine at least one decoded target information bit in any decoding path when a currently decoded bit is a parity check PC-freeze bit and a decoding result of the bit in the decoding path does not pass a check, where the target information bit is an information bit that differs from the bit position by a specified bit, and the specified bit is an integer multiple of a shift period of a cyclic shift register;
a decoding module, configured to turn over a decoding result of a target information bit from a first target information bit in the at least one target information bit, and to perform decoding again after going back to the target information bit in the decoding path, check a decoding result obtained by the bit through decoding again every time the bit is turned over and decoded backwards, and continue to turn over and decode backwards a next target information bit when the bit does not pass the check;
and the adjusting module is used for increasing the number of decoding paths and continuing decoding when the at least one target information bit is subjected to the turnover and backspacing decoding and the decoding result of the bit passing the re-decoding does not pass the check.
7. The apparatus of claim 6, wherein the determining module is configured to determine a plurality of information bits between the bit and a previous parity PC-freeze bit of the bit; acquiring information bits meeting a specified relational expression from the plurality of information bits as the at least one target information bit;
the specified relation is
Wherein, I i Is the index value of the information bit, S is the length of the circular shift register, I is the index value of the bit, In p Refers to the index value of the current PC-freeze bit.
8. The apparatus of claim 6, wherein the adjusting module is configured to adjust the number of current decoding paths to a smaller value of a first number of paths and a second number of paths, the first number of paths being twice the number of current decoding paths, the second number of paths being a preset maximum number of paths; and all decoding paths are retreated to the first target information bit in the at least one target information bit for decoding again.
9. The apparatus according to claim 6, wherein the decoding module is further configured to end the roll-over and roll-back decoding process when a decoding result obtained by the bit re-decoding passes verification after each roll-over and roll-back decoding; and taking the overturning result of the overturned target information bit as the decoding result of the overturned target information bit.
10. The apparatus according to claim 6, wherein the adjusting module is further configured to adjust the number of current decoding paths to a larger value of a third number of paths and a fourth number of paths when the decoding results of the bits in all decoding paths pass the check, and continue the decoding, where the third number of paths is half of the number of current decoding paths, and the fourth number of paths is a preset minimum number of paths.
11. An electronic device, comprising a processor and a memory, wherein at least one instruction, at least one program, set of codes, or set of instructions is stored in the memory, and wherein the at least one instruction, the at least one program, the set of codes, or the set of instructions is loaded and executed by the processor to implement the decoding method according to any one of claims 1 to 5.
12. A computer readable storage medium having stored therein at least one instruction, at least one program, a set of codes, or a set of instructions, which is loaded and executed by a processor to implement the method of decoding as claimed in any one of claims 1 to 5.
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