CN109411482A - 玻璃芯片接合封装组件 - Google Patents
玻璃芯片接合封装组件 Download PDFInfo
- Publication number
- CN109411482A CN109411482A CN201710940684.7A CN201710940684A CN109411482A CN 109411482 A CN109411482 A CN 109411482A CN 201710940684 A CN201710940684 A CN 201710940684A CN 109411482 A CN109411482 A CN 109411482A
- Authority
- CN
- China
- Prior art keywords
- chip
- glass
- class
- package component
- bond package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5387—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05012—Shape in top view
- H01L2224/05014—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13015—Shape in top view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
- H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/81122—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors by detecting inherent features of, or outside, the semiconductor or solid-state body
- H01L2224/81129—Shape or position of the other item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/8113—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/1426—Driver
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/148—Arrangements of two or more hingeably connected rigid printed circuit boards, i.e. connected by flexible means
Abstract
本发明公开一种玻璃芯片接合封装组件,包括玻璃衬底、第一类芯片、第二类芯片和多个连接线。玻璃衬底包括有源区域和与有源区域连接的周边区域。第一类芯片设置于周边区域上,且包括处理器。第二类芯片设置于周边区域上,且位于第一类芯片的一侧上,其中,第二类芯片不同于第一类芯片。连接线配置于周边区域上,且连接第一类芯片和第二类芯片。
Description
技术领域
本发明涉及一种芯片封装体,且特别是涉及一种玻璃芯片接合(Chip on glass,COG)封装组件。
背景技术
近年来,触控显示技术广泛地用于各种多媒体电子产品中,尤其是携带式移动产品,如移动电话、电子书(E-books)、平板计算机,等等。通过将触摸显示技术作为输入方式使用,可有效地替代使用键盘或鼠标的输入方式。除了方便性之外,由于还具有直觉式操作特性,触控输入技术更已成为人机接口和多媒体之间广为使用的互动方式。
一般而言,触控显示面板通过电路板与驱动装置电连接,由此可将触控显示面板的信号传送给驱动装置。除此之外,其上设置柔性电路板,其具有电子装置(例入:闪存芯片(Flash memory chip)、电阻、电容器,等等),且此柔性电路板(Flexible printed circuitboard,FPC board)电连接于感测阵列(Sensing array),由此可输入驱动信号并输出感测信号。然而,此种柔性电路板的设计和布局复杂,且对柔性电路板的电子装置进行电性测试所需的成本昂贵,导致触控显示器的成本增加。
发明内容
基于上述,本发明的目的在于提供一种玻璃芯片接合(Chip on glass,COG)封装组件,可降低生产成本。
本发明提出一种玻璃芯片接合封装组件,包括玻璃衬底、第一类芯片、第二类芯片和多个连接线。所述玻璃衬底包括有源区域和连接至所述有源区域的周边区域。所述第一类芯片设置于所述周边区域上,且包括处理器。所述第二类芯片设置于所述周边区域上,且位于所述第一类芯片的一侧上,其中所述第二类芯片不同于所述第一类芯片。所述多个连接线配置于所述周边区域上,且将所述第一类芯片与所述第二类芯片连接。
根据本发明的一实施例,所述第一类芯片还包括控制器,用以对所述第二类芯片进行存取。
根据本发明的一实施例,所述玻璃衬底还包括像素阵列和多个扇出(Fan-out)线路,其中所述像素阵列配置于所述有源区域上,且所述扇出线路将所述像素阵列与所述第一类芯片连接。
根据本发明的一实施例,所述第一类芯片是驱动芯片(Driver chip)。
根据本发明的一实施例,所述第二类芯片是闪存芯片(Flash memory chip)。
根据本发明的一实施例,包括第一类芯片区,配置有所述第一类芯片,和延伸区,自所述第一类芯片区沿着所述第一类芯片的长轴延伸,且所述第二类芯片配置于所述延伸区内。
根据本发明的一实施例,所述第一类芯片和所述第二类芯片是以并排方式排列,且所述第二类芯片的宽度等于或小于所述第一类芯片的宽度。
根据本发明的一实施例,所述第二类芯片包括多个接垫和多个导电凸块,所述多个接垫配置于所述第二类芯片的有源面上,所述多个导电凸块配置于所述多个接垫上,且所述第二类芯片通过所述导电凸块设置于所述周边区域上。
根据本发明的一实施例,所述第二类芯片还包括对位标记,其配置于所述有源面上。
根据本发明的一实施例,所述多个连接线完全位于所述玻璃衬底的周边区域上。
根据本发明的一实施例,所述玻璃芯片接合封装组件还包括柔性电路板(Flexible printed circuit board,FPC board)连接于所述玻璃衬底和主板之间。
根据本发明的一实施例,所述多个连接线包括第一部分和第二部分,所述第一部分连接至所述第一类芯片并延伸至所述柔性电路板,且所述第二部分连接所述第一部分并自所述柔性电路板延伸至所述玻璃衬底,以连接至所述第二类芯片。
根据本发明的一实施例,所述柔性电路板上无配置任何电子装置。
根据本发明的一实施例,所述玻璃芯片接合封装组件还包括多个主焊垫、多个延伸焊垫和多个延伸线路,其中所述多个主焊垫分别连接至所述多个连接线,所述延伸线路将所述多个主焊垫分别与所述多个延伸焊垫连接。
基于上述,在本发明的玻璃芯片接合封装组件中,无源组件被整合到第一类芯片中,且例如为闪存芯片的第二类芯片配置于玻璃衬底上。因此,柔性电路板可仅用以电连接玻璃衬底,以简化柔性电路板的布局和设计,并且由于省略用以将电子装置设置到柔性电路板上的表面安装工艺,由此可降低玻璃芯片接合封装组件的生产成本,并且省去对柔性电路板的电子装置进行电性测试所需的成本。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。
附图说明
下面的附图是本发明的说明书的一部分,示出了本发明的示例实施例,附图与说明书的描述一起说明本发明的原理。
图1为一示范性实施例所绘示的玻璃芯片接合(Chip on glass,COG)封装组件的部分俯视图;
图2为一示范性实施例所绘示的玻璃芯片接合封装组件的方块图;
图3为一示范性实施例所绘示的玻璃芯片接合封装组件的部分俯视图;
图4为一示范性实施例所绘示的第二类芯片的部分剖视图;
图5为一示范性实施例所绘示的第二类芯片的仰视图;
图6为一示范性实施例所绘示的玻璃衬底布局的部分俯视图。
附图标记说明:
100:玻璃芯片接合封装组件;
110:玻璃衬底;
112:有源区域;
112a:像素阵列;
114:周边区域;
114a:第一类芯片区;
114b:延伸区;
116:扇出线路;
120:第一类芯片;
122:处理器;
124:控制器;
130:第二类芯片;
132:有源面;
134:接垫;
136:导电凸块;
138:对位标记
140:连接线;
A1:长轴;
A2:短轴;
W1、W2:宽度;
150:柔性电路板;
162:主焊垫;
164:延伸线路;
166:延伸焊垫;
170:主板;
具体实施方式
现将详细参考本发明的示范性实施例,在附图中说明所述示范性实施例的实例。另外,凡可能之处,在附图及实施方式中相同标号代表相同或类似部分。
图1是依照一示范性实施例所绘示的玻璃芯片接合(Chip on glass,COG)封装组件的部分俯视图。图2是依照一示范性实施例所绘示的玻璃芯片接合封装组件的方块图。请参照图1和图2,在本实施例中,玻璃芯片接合封装组件100可为触控显示面板。所述玻璃芯片接合封装组件100包括玻璃衬底110、第一类芯片120、第二类芯片130和多个连接线140。所述玻璃衬底110包括有源区域112和连接至有源区域112的周边区域114。在本实施例中,所述玻璃衬底110可还包括像素阵列112a和多个扇出(Fan-out)线路116。所述像素阵列112a是由多个以阵列方式排列于有源区域112上的像素电极所构成。所述周边区域114可配置于有源区域112的一侧上,且所述扇出线路116配置于周边区域114上以如图1中所绘示地连接像素阵列112a与第一类芯片120。
在本实施例中,所述第一类芯片120设置于周边区域114上且包括处理器122。所述第二类芯片130也设置于周边区域114上,且位于第一类芯片120的一侧上。在本实施例中,所述第一类芯片120可还包括控制器124,用以对所述第二类芯片130进行存取,如图2中所绘示。第二类芯片130不同于第一类芯片120。举例来说,第一类芯片120可为驱动芯片(Driver chip),而第二类芯片130可为闪存芯片(Flash memory chip)。第一类芯片120的控制器124可对存储于第二类芯片130中的数据进行存取。在本实施例中,所述第一类芯片120可与至少一无源组件,例如电阻、电容器、电感器或其任意组合进行整合。然而,本实施例仅作为说明之用,且本发明并不限定所述第一类芯片120和所述第二类芯片130的类型。所述多个连接线140配置于周边区域114上,以连接第一类芯片120与第二类芯片130,如图1中所绘示。
在本实施例中,所述周边区域114包括第一类芯片区114a和延伸区114b。第一类芯片120配置于在所述第一类芯片区114a之内。延伸区114b自第一类芯片区114a沿着所述第一类芯片120的长轴A1延伸,且第二类芯片130配置于所述延伸区114b之内。举例来说,所述第一类芯片120可配置于周边区域114的中央区域上,如此一来,第一类芯片120所配置的中央区域,即为上述第一类芯片区114a。基此,所述延伸区114b可沿着所述的长轴A1自所述第一类芯片区114a(即,上述周边区域114的中央区域)的相对两侧朝着所述玻璃衬底110的边缘延伸,且所述第二类芯片130可配置于延伸区114b上,例如,位于第一类芯片区114a的左侧上。
在本实施例中,所述第一类芯片120和所述第二类芯片130以并排方式排列,且第二类芯片的宽度W2等于或小于所述第一类芯片的宽度W1,如此一来,所述第二类芯片的宽度W2就不会额外占用玻璃衬底110上沿着第一类芯片120的短轴A2方向上的空间。在本实施例中,所述多个连接线140完全位于玻璃衬底110的周边区域114上,如图1中所绘示,但是本发明并不限定连接线140的布局。
图3是依照一示范性实施例所绘示的玻璃芯片接合封装组件的部分俯视图。需注意的是,图3中所示的玻璃芯片接合封装组件100包含许多与上述图1和图2中绘示的玻璃芯片接合封装组件100相同或相似的元件。为了清楚及简化起见,说明中省略相同或相似元件的相关描述,且相同或相似的标号代表相同或相似的组件。图3中所示的玻璃芯片接合封装组件100与图1和图2所示的玻璃芯片接合封装组件100间的主要差异将描述如下。
请参照图3,在本实施例中,所述玻璃芯片接合封装组件100还包括柔性电路板(Flexible printed circuit,FPC)150,其连接于所述玻璃衬底110和主板170之间。所述玻璃衬底110通过柔性电路板150与所述主板170电连接。在本实施例中,所述多个连接线140可包括第一部分和第二部分,其互相连接。所述第一部分连接于所述第一类芯片120,并延伸至柔性电路板150,且所述第二部分自柔性电路板150延伸至玻璃衬底110,以连接于第二类芯片130。因此,在图1中所示的实施例中,通过完全位于玻璃衬底110上的连接线140,第一类芯片120电连接于第二类芯片130。然而,在图3中所示的本实施例中,通过柔性电路板150,且通过将所述多个连接线140延伸至柔性电路板150,第一类芯片120电连接于第二类芯片130。
在本实施例中,由于无源组件与第一类芯片120整合,且第二类芯片130(例如:闪存芯片)设置于玻璃衬底上,柔性电路板150因而可仅用以电连接玻璃衬底110与主板170,由此,柔性电路板150无须配置电子装置。基此,柔性电路板150的布局和设计可简化,且用以将电子装置设置到柔性电路板150的表面安装工艺(Surface mount process)也可省略,由此可降低玻璃芯片接合封装组件100的生产成本,并省去对柔性电路板150上的电子装置进行电性测试所需的成本。
图4是依照一示范性实施例所绘示的第二类芯片的部分剖视图。图5是依照一示范性实施例所绘示的第二类芯片的仰视图。请参照图4和图5,所述第二类芯片130包括多个接垫134和多个导电凸块136,如图4中所绘示。所述接垫134配置于所述第二类芯片130的有源面132上,且所述导电凸块136分别配置于接垫134上。通过此配置,所述第二类芯片130可通过所述导电凸块136设置于周边区域114上。在本实施例中,所述导电凸块136的材质包括金(Au)或其他适用的材质,且导电凸块136可利用诸如光刻工艺、电镀工艺等等来形成。基此,可利用倒装焊(Flip-chip bonding)技术,将所述第二类芯片130设置于所述玻璃衬底110的周边区域114上。
请参照图5,在本实施例中,所述第二类芯片130还包括至少一对位标记(Alignment mark)138(图中绘示了两个对位标记138),配置于所述有源面132上,如图5所示。对位标记138可配置于所述第二类芯片130的周围,如此一来,利用倒装焊技术,并借助所述对位标记138将所述第二类芯片130与所述玻璃衬底110对位,可将第二类芯片130设置于玻璃衬底110上。
图6是依照一示范性实施例所绘示的玻璃衬底布局的部分俯视图。请参照图6,在本实施例中,各种焊垫布局可形成于玻璃衬底110上,以将各种类型芯片适配以设置于所述玻璃衬底110上。基此,所述玻璃衬底110可还包括多个主焊垫16、多个延伸线路164和多个延伸焊垫166。主焊垫162分别连接于所述多个连接线140,延伸线路164将主焊垫162分别与延伸焊垫166连接。
举例来说,连接于所述多个连接线140的主焊垫162可为适于与所述第二类芯片130的导电凸块136进行接合的焊垫。通过延伸线路164与主焊垫162连接的延伸焊垫166可为适于与第三类芯片的导电凸块进行接合的焊垫。第二类芯片130的导电凸块136的布局可不同于第三类芯片的导电凸块的布局,如此一来,主焊垫162的位置即不同于延伸焊垫166的位置,且延伸线路164经配置以电连接于主焊垫162和延伸焊垫166之间。通过此配置,玻璃衬底110适于设置有具有各种导电凸块布局的各种芯片。由此,可提升玻璃芯片接合封装组件100的应用灵活度。
需注意的是,本实施例本实施例仅作为说明之用,且本发明并不限定玻璃衬底110的布局和数量及主焊垫162、延伸线路164与延伸焊垫166的数量。
总而言之,在本发明的玻璃芯片接合封装组件中,无源组件被整合到第一类芯片中,且例如为闪存芯片的第二类芯片配置于玻璃衬底上。因此,柔性电路板可仅用以电连接玻璃衬底,以简化柔性电路板的布局和设计,并且由于省略用以将电子装置安装到柔性电路板上的表面安装工艺,因而可降低玻璃芯片接合封装组件的生产成本,并且省去对柔性电路板的电子装置进行电性测试所需的成本。
此外,各种焊垫布局可形成于玻璃衬底上,以将各种类型芯片适配以设置于所述玻璃衬底上,因此,所述玻璃衬底适于设置有具有各种导电凸块布局的各种芯片。由此,可提升玻璃芯片接合封装组件的应用灵活度。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。
Claims (14)
1.一种玻璃芯片接合封装组件,其特征在于,包括:
玻璃衬底,包括有源区域和连接至所述有源区域的周边区域;
第一类芯片,设置于所述周边区域上,且包括处理器;
第二类芯片,设置于所述周边区域上,且位于所述第一类芯片的一侧上,其中所述第二类芯片不同于所述第一类芯片;及
多个连接线,配置于所述周边区域上,且连接所述第一类芯片与所述第二类芯片。
2.根据权利要求1所述的玻璃芯片接合封装组件,其中所述第一类芯片还包括控制器,用以对所述第二类芯片进行存取。
3.根据权利要求1所述的玻璃芯片接合封装组件,其中所述玻璃衬底还包括像素阵列和多个扇出线路,其中所述像素阵列配置于所述有源区域上,且所述扇出线路将所述像素阵列与所述第一类芯片连接。
4.根据权利要求1所述的玻璃芯片接合封装组件,其中所述第一类芯片是驱动芯片。
5.根据权利要求1所述的玻璃芯片接合封装组件,其中所述第二类芯片是闪存芯片。
6.根据权利要求1所述的玻璃芯片接合封装组件,其中所述周边区域包括第一类芯片区和延伸区,所述第一类芯片配置于所述第一类芯片区,所述延伸区自所述第一类芯片区沿着所述第一类芯片的长轴延伸,且所述第二类芯片配置于所述延伸区内。
7.根据权利要求1所述的玻璃芯片接合封装组件,其中所述第一类芯片和所述第二类芯片是以并排方式排列,且所述第二类芯片的宽度等于或小于所述第一类芯片的宽度。
8.根据权利要求1所述的玻璃芯片接合封装组件,其中所述第二类芯片包括多个接垫和多个导电凸块,所述多个接垫配置于所述第二类芯片的有源面上,所述多个导电凸块配置于所述多个接垫上,且所述第二类芯片通过所述导电凸块设置于所述周边区域上。
9.根据权利要求8所述的玻璃芯片接合封装组件,其中所述第二类芯片还包括对位标记,其配置于所述有源面上。
10.根据权利要求1所述的玻璃芯片接合封装组件,其中所述多个连接线完全位于所述玻璃衬底的周边区域上。
11.根据权利要求1所述的玻璃芯片接合封装组件,还包括柔性电路板连接于所述玻璃衬底和主板之间。
12.根据权利要求11所述的玻璃芯片接合封装组件,其中所述多个连接线包括第一部分和第二部分,所述第一部分连接至所述第一类芯片并延伸至所述柔性电路板,且所述第二部分连接所述第一部分并自所述柔性电路板延伸至所述玻璃衬底,以连接至所述第二类芯片。
13.根据权利要求11所述的玻璃芯片接合封装组件,其中所述柔性电路板上无配置电子装置。
14.根据权利要求1所述的玻璃芯片接合封装组件,其中所述玻璃衬底还包括多个主焊垫、多个延伸焊垫和多个延伸线路,其中所述多个主焊垫分别连接至所述多个连接线,所述延伸线路分别将所述多个主焊垫与所述多个延伸焊垫连接。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/680,202 US10692815B2 (en) | 2017-08-17 | 2017-08-17 | Chip on glass package assembly |
US15/680,202 | 2017-08-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109411482A true CN109411482A (zh) | 2019-03-01 |
CN109411482B CN109411482B (zh) | 2021-04-13 |
Family
ID=65361376
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710940684.7A Active CN109411482B (zh) | 2017-08-17 | 2017-10-11 | 玻璃芯片接合封装组件 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10692815B2 (zh) |
CN (1) | CN109411482B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11430818B2 (en) | 2019-04-24 | 2022-08-30 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Method of manufacturing light emitting panel, light emitting panel, and display device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101211043A (zh) * | 2006-12-27 | 2008-07-02 | Lg.菲利浦Lcd株式会社 | 液晶显示装置及其制造方法 |
CN102254523A (zh) * | 2010-05-18 | 2011-11-23 | 硅工厂股份有限公司 | 玻璃覆晶型液晶显示装置 |
CN102819132A (zh) * | 2011-06-07 | 2012-12-12 | 冈谷电机产业株式会社 | 液晶模块 |
US20140138123A1 (en) * | 2012-11-21 | 2014-05-22 | Hannstar Display Corporation | Circuit stack structure |
US20170047313A1 (en) * | 2012-09-26 | 2017-02-16 | Ping-Jung Yang | Method for fabricating glass substrate package |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7012799B2 (en) * | 2004-04-19 | 2006-03-14 | Wilson Greatbatch Technologies, Inc. | Flat back case for an electrolytic capacitor |
US7663728B2 (en) * | 2006-03-28 | 2010-02-16 | Tpo Displays Corp. | Systems for providing conducting pad and fabrication method thereof |
US9360302B2 (en) * | 2011-12-15 | 2016-06-07 | Kla-Tencor Corporation | Film thickness monitor |
EP2947692B1 (en) * | 2013-12-20 | 2020-09-23 | Analog Devices, Inc. | Integrated device die and package with stress reduction features |
TWI585910B (zh) * | 2016-02-05 | 2017-06-01 | 力成科技股份有限公司 | 扇出型背對背晶片堆疊封裝構造及其製造方法 |
-
2017
- 2017-08-17 US US15/680,202 patent/US10692815B2/en active Active
- 2017-10-11 CN CN201710940684.7A patent/CN109411482B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101211043A (zh) * | 2006-12-27 | 2008-07-02 | Lg.菲利浦Lcd株式会社 | 液晶显示装置及其制造方法 |
CN102254523A (zh) * | 2010-05-18 | 2011-11-23 | 硅工厂股份有限公司 | 玻璃覆晶型液晶显示装置 |
CN102819132A (zh) * | 2011-06-07 | 2012-12-12 | 冈谷电机产业株式会社 | 液晶模块 |
US20170047313A1 (en) * | 2012-09-26 | 2017-02-16 | Ping-Jung Yang | Method for fabricating glass substrate package |
US20140138123A1 (en) * | 2012-11-21 | 2014-05-22 | Hannstar Display Corporation | Circuit stack structure |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11430818B2 (en) | 2019-04-24 | 2022-08-30 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Method of manufacturing light emitting panel, light emitting panel, and display device |
Also Published As
Publication number | Publication date |
---|---|
CN109411482B (zh) | 2021-04-13 |
US20190057938A1 (en) | 2019-02-21 |
US10692815B2 (en) | 2020-06-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11048132B2 (en) | Display panel and display apparatus | |
CN107180594B (zh) | 一种显示面板和显示装置 | |
CN108628488B (zh) | 内嵌式触控显示装置以及相关测试系统与测试方法 | |
US7763986B2 (en) | Semiconductor chip, film substrate, and related semiconductor chip package | |
TWI769500B (zh) | 具有窄下邊框的顯示面板及電子設備 | |
US8537091B2 (en) | Flat panel display | |
KR20080001975A (ko) | 표시 기판 및 이를 구비한 표시 장치 | |
KR100632257B1 (ko) | 액정 디스플레이 구동용 탭 패키지의 배선 패턴 구조 | |
CN106686879A (zh) | 柔性印刷电路板以及具有其的显示设备 | |
US20150253897A1 (en) | Bonding pad structure and touch panel | |
CN100464236C (zh) | 半导体芯片的结构和利用其的显示设备 | |
US20240019962A1 (en) | Touch display panel and display device | |
CN106201106A (zh) | 一种触控显示面板 | |
US11934606B2 (en) | Flexible circuit board and manufacturing method, display device, circuit board structure and display panel thereof | |
CN112201155A (zh) | 显示面板 | |
CN111290662A (zh) | 触控基板、显示基板及显示装置 | |
US10747038B2 (en) | Display device | |
CN109411482A (zh) | 玻璃芯片接合封装组件 | |
CN112954888A (zh) | 一种覆晶薄膜、覆晶薄膜组及显示装置 | |
CN114677987B (zh) | 一种显示面板及显示装置 | |
CN115019677B (zh) | 显示面板及其制备方法、显示装置的制备方法 | |
US10256174B2 (en) | Film type semiconductor package | |
KR20110114444A (ko) | 드라이버 집적회로 칩의 전원연결 구조 | |
CN101477970B (zh) | 电路基板及其应用 | |
CN112702837A (zh) | 柔性电路膜和具有柔性电路膜的显示装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |