CN109411467A - A method of reducing ESD protective device trigger voltage - Google Patents
A method of reducing ESD protective device trigger voltage Download PDFInfo
- Publication number
- CN109411467A CN109411467A CN201810989048.8A CN201810989048A CN109411467A CN 109411467 A CN109411467 A CN 109411467A CN 201810989048 A CN201810989048 A CN 201810989048A CN 109411467 A CN109411467 A CN 109411467A
- Authority
- CN
- China
- Prior art keywords
- esd
- protective device
- esd protective
- port
- nmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001681 protective effect Effects 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 230000003071 parasitic effect Effects 0.000 claims abstract description 18
- 230000015556 catabolic process Effects 0.000 claims abstract description 10
- 238000013461 design Methods 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 4
- 230000003068 static effect Effects 0.000 claims 1
- 238000002347 injection Methods 0.000 abstract description 9
- 239000007924 injection Substances 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 239000002184 metal Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 8
- 238000012360 testing method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of methods for reducing ESD protective device trigger voltage; the improved properties of ESD protection device suitable for integrated circuit; wherein the ESD protective device includes the multiple NMOS tubes being arranged in parallel; the drain electrode of the multiple NMOS tube is connected to the port I/O or power port by metal connecting line, and grid, source electrode and the substrate of multiple NMOS tubes are connected to ground potential jointly.It is characterized in that: in the ESD protective device, the drain electrode of NMOS tube eliminates LDD injection (Light Dope Drain, low doped drain region).When there is positive esd pulse in the port I/O or power port; because drain region eliminates LDD injection; the breakdown voltage of drain region parasitic diode reduces; reduce the trigger voltage of ESD protective device; so that the multiple metal-oxide-semiconductors being arranged in parallel simultaneously turn on electric discharge; and it is lower than the failure voltage of protected device, can preferably protects internal circuit, the ESD protective capability of integrated circuit is improved.
Description
Technical field
The present invention relates to a kind of design method of ESD protective device more particularly to a kind of reduction ESD protective device triggering electricity
The method of pressure is suitable for IC design.
Background technique
With increasingly advanced made of semiconductor technology, process, transport in technique, test, the ESD occurred in application process
Problem is increasingly taken seriously, and in ESD protective device design, generally uses resistance, diode, triode, metal-oxide-semiconductor and controllable
Silicone tube etc., metal-oxide-semiconductor is most widely used in these ESD protective devices.
ESD protective device based on metal-oxide-semiconductor is all to refer to MOS design mostly more, by identical multiple metal-oxide-semiconductor units and townhouse
Column are constituted, circuit diagram as shown in Figure 1, domain schematic diagram as shown in Fig. 2, illustrate so that four NMOS tubes are in parallel as an example here,
But it is not limited to four NMOS tubes to be arranged in parallel, can be 6,8,10 ..., but cannot be that odd number NMOS tube is in parallel
Arrangement.As shown in Figure 1, the grid of NMOS tube, source electrode and Substrate ground, drain electrode connects the port I/O or power port.As shown in Fig. 2,
Peripheral annular is substrate contact (1), and black square is contact hole (2), altogether four NMOS parallel connections, their grid difference
It is 3a, 3b, 3c, 3d.The drain electrode of the drain electrode NMOS pipe corresponding with 3b of the corresponding NMOS tube of 3a shares (4a), and 3c corresponds to NMOS
Drain electrode correspond to the drain electrode of NMOS tube with 3d and share (4b), the source electrode of the corresponding NMOS tube of 3b and the source electrode of the corresponding NMOS tube of 3c
It shares (5b), the drain electrode of this four NMOS is connected to the port I/O or power port by metal (6), the grid of this four NMOS
Pole, source electrode are connected to ground by metal.
It is its sectional view as shown in Figure 3,5a and 4a are respectively formed the emitter and collector of parasitic transistor T1, T1's
Base stage is connected to substrate contact by R1 (substrate parasitics resistance), and 5b and 4a are respectively formed the emitter and current collection of parasitic transistor T2
The base stage of pole, T2 is connected to substrate contact by R2 (substrate parasitics resistance), and 5b and 4b are respectively formed the transmitting of parasitic transistor T3
The base stage of pole and collector, T3 is connected to substrate contact by R3 (substrate parasitics resistance), and 5c and 4b are respectively formed parasitic transistor
The base stage of the emitter and collector of T4, T4 is connected to substrate contact by R4 (substrate parasitics resistance), the grid of this four NMOS tubes
Pole, drain electrode, source electrode and substrate contact are all covered by silicide (7), in some esd protection circuits, in order to improve ESD protection energy
Power can remove the silicide of drain electrode.
It is the amplification sectional view of piece NMOS in the leftmost side in Fig. 3 as shown in Figure 4, is labelled with the position of LDD injection in detail.?
In the manufacture processing of integrated circuit, the purpose of LDD injection is to inhibit hot carrier's effect, and LDD injection improves device suppression
Heat the reliability in terms of carrier, but the breakdown voltage due to improving device, and different LDD implant angles also table
Reveal different characteristics, be unfavorable for the design of esd protection circuit, increases the difficulty of esd protection circuit design.
When positive esd pulse occur in the port I/O or power port, drain electrode and the breakdown of substrate parasitics diode avalanche are generated
Electron hole, hole flow to substrate, form substrate current, and the emitter and collector of T1~T4 all, flows to the electricity of substrate
All, so the unlatching of T1~T4 is mainly influenced by resistance substrate, T2 and T3 connect closer to centre far from substrate stream
Touching, resistance substrate is bigger, this causes T2 and T3 first to open, and opens after T1 and T4, as the increase of ESD electric current is likely to occur T2
It has been burnt out with T3, the phenomenon that T1 and T4 are not turned on, it is this to open non-uniform phenomenon and cause under ESD protective device ability
Drop.
Even if very big metal-oxide-semiconductor, if not solving the problems, such as conducting homogeneity, its ESD protection capability will not be
It improves.The method for solving finger-like MOS uniform conducting has very much, for example is mentioned using GCNMOS (Gate Coupled NMOS) structure
High grid voltage, or the substrate current of ESD protective device is improved, reduce trigger voltage etc..
Summary of the invention
Primary and foremost purpose of the invention is to provide a kind of method for reducing ESD protective device trigger voltage, to increase it
ESD protective capability.
ESD protective device is made of the multiple NMOS tubes being arranged in parallel, and the grid of the NMOS tube, source electrode and substrate connect
Ground, drain electrode connect the port I/O or power port, and the drain electrode of the NMOS tube is covered by the barrier layer LDD, inject without LDD.Work as I/
When positive esd pulse occur in O port or power port, due to no LDD injection that drains, the breakdown potential pressure drop of parasitic diode
Low, the trigger voltage of ESD protective device reduces, and allows and refers to that NMOS tube simultaneously turns on electric discharge more, and compares protected device
Failure voltage it is low, can preferably protect internal components.
Compared with prior art, the present invention has the following advantages:
1. the processing is simple for technique, it is only necessary to increase by one layer of barrier layer LDD, LDD is hindered to be injected into drain electrode.
2. relatively other methods for reducing ESD trigger voltage, do not need other devices auxiliary, can preferably save chip face
Product.
3. drain electrode can connect the signal of upper frequency because of the grounded-grid of ESD protective device, ESD protection will not be triggered
Device and leak electricity.
4. because the grounded-grid of ESD protective device does not require the power-on time of power supply when drain electrode is connected to power supply,
There will not be the problem of false triggering.
Detailed description of the invention
With reference to the accompanying drawing, the present invention will be described in detail
The existing ESD protective device schematic diagram based on NMOS tube of Fig. 1；
The existing ESD protective device domain schematic diagram based on NMOS tube of Fig. 2；
The existing ESD protective device domain cross-sectional view based on NMOS tube of Fig. 3；
The ESD protective device domain cross-sectional view that Fig. 4 is injected with LDD；
ESD protective device voltage-to-current test chart of the Fig. 5 based on NMOS tube；
The ESD protective device domain schematic diagram based on NMOS tube of Fig. 6 this patent description；
ESD protective device domain cross-sectional view without LDD injection of the Fig. 7 based on this patent；
Specific embodiment
It is readily understood to enable above-mentioned purpose of the invention, features and advantages to become apparent from, hereafter especially exemplified by preferred embodiment, and
The appended diagram of cooperation, is described below in detail:
ESD protective device voltage-to-current test chart based on NMOS tube is as shown in figure 5, black curve is existing is based on
The voltage-to-current test curve of the ESD protective device of NMOS tube, when there is positive esd pulse in the port I/O or power port,
Before Vt1, ESD protective device is not turned on, only small electric leakage, with the increase of ESD energy, the drain electrode of NMOS and
Avalanche breakdown occurs for substrate parasitics PN junction, generates electron hole, and hole flows to substrate, parasitic since there are substrate parasitics resistance
Transistor is triggered, and negative resistance phenomenon then occurs in trigger voltage Vt1, and the voltage in ESD protective device drops to Vh, with
ESD energy continues growing, and ESD protective device starts ESD charge of releasing, until (Vt2, It2) fails, if Vt2 is equal to
Vt1 or Vt2 is less than Vt1, with regard to will appear conducting homogeneity problem.If Vt1 is greater than the failure voltage of protected device, ESD is protected
Shield device cannot play the role of protection.
Method provided in this embodiment so that Vt1 is reduced to Vt1 ', and is lower than the failure voltage of protected device, such as
Black dotted lines in Fig. 5 can be good at protecting protected device so that the multiple NMOS being arranged in parallel can be connected.Such as figure
It is that the ESD protective device schematic diagram based on NMOS tube of this patent description and the existing ESD based on NMOS tube are protected shown in 1
It is the same to protect device principle figure, does not have to additional device, this device can inherently treat as an esd protection circuit.
It is the ESD protective device domain schematic diagram based on NMOS tube of this patent description as shown in Figure 6, with four NMOS
For be illustrated, the grid of this four NMOS is 3a, 3b, 3c, 3d respectively.3a corresponds to the drain electrode of NMOS and 3b corresponds to NMOS
Drain electrode share (4a), the drain electrode that the drain electrode that 3c correspond to NMOS corresponds to NMOS with 3d is shared (4b), 3b correspond to the source electrode of NMOS with
The source electrode that 3c corresponds to NMOS shares (5b), the drain electrode of this four NMOS is connected to the port I/O or power port by metal (6),
Key is that the drain electrode of this four NMOS is covered by the barrier layer LDD (8).
It is the ESD protective device domain cross-sectional view without LDD injection of this patent as shown in Figure 7, with the leftmost side in Fig. 6
A MOS for.5a and 4a is respectively formed the emitter and collector of parasitic transistor T1, and the base stage of T1 passes through R1 (substrate
Dead resistance) it is connected to substrate contact, it is important to and the collector of T1 does not have LDD injection.Because of the breakdown voltage and doping of diode
Concentration is related, and doping concentration is higher, and the lower NMOS with existing band LDD of breakdown voltage is compared, and after removing LDD, drain electrode is mixed
Miscellaneous concentration is got higher, and reduces the breakdown voltage of diode, general to reduce 2V or so, so ESD device can be effectively improved in ESD thing
Uniform conducting in part is opened, ESD charge of having released before protected device fails.
Note that any term used in this document should not be considered as limiting the scope of the invention.The skill of this field
Art personnel will be understood that the present invention is not limited to the above embodiments, and not depart from this hair being defined by the appended claims
Bright range can make many modifications and increase.
Claims (1)
1. a kind of method for reducing ESD protective device trigger voltage, static discharge (ESD) protective device suitable for integrated circuit
Design, it is characterised in that: the ESD protective device is multiple NMOS tubes being arranged in parallel in p-well, the multiple NMOS
Drain electrode be connected to the port I/O or power port, grid, source electrode and substrate are connected to ground potential jointly, in the ESD protective device
In, the drain electrode of NMOS tube is covered by the barrier layer LDD, is injected without LDD；
When positive esd pulse occur in the port I/O or power port, drain parasitic diode is breakdown, because being injected without LDD,
Breakdown voltage reduces, and reduces the trigger voltage of parasitic NPN, the multiple NMOS tubes being arranged in parallel are simultaneously turned on and are put
Electricity improves the performance of esd protection circuit；
When negative esd pulse occur in the port I/O or power port, NMOS drain electrode and p-well parasitic diode are opened, and are played protection and are made
With.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810989048.8A CN109411467A (en) | 2018-08-28 | 2018-08-28 | A method of reducing ESD protective device trigger voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810989048.8A CN109411467A (en) | 2018-08-28 | 2018-08-28 | A method of reducing ESD protective device trigger voltage |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109411467A true CN109411467A (en) | 2019-03-01 |
Family
ID=65463646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810989048.8A Pending CN109411467A (en) | 2018-08-28 | 2018-08-28 | A method of reducing ESD protective device trigger voltage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109411467A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112366202A (en) * | 2020-10-23 | 2021-02-12 | 长江存储科技有限责任公司 | Electrostatic discharge protection structure and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104733536A (en) * | 2013-12-20 | 2015-06-24 | 昆山工研院新型平板显示技术中心有限公司 | Thin film transistor and manufacturing method thereof |
| CN105097550A (en) * | 2015-08-04 | 2015-11-25 | 深圳市华星光电技术有限公司 | Low-temperature polycrystalline silicon thin film transistor (TFT) and manufacture method thereof |
| CN105931965A (en) * | 2016-04-28 | 2016-09-07 | 厦门天马微电子有限公司 | Semiconductor device and manufacturing method thereof |
| CN107017249A (en) * | 2017-03-30 | 2017-08-04 | 北京中电华大电子设计有限责任公司 | It is a kind of to improve the method for ESD protective device uniform conducting |
-
2018
- 2018-08-28 CN CN201810989048.8A patent/CN109411467A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104733536A (en) * | 2013-12-20 | 2015-06-24 | 昆山工研院新型平板显示技术中心有限公司 | Thin film transistor and manufacturing method thereof |
| CN105097550A (en) * | 2015-08-04 | 2015-11-25 | 深圳市华星光电技术有限公司 | Low-temperature polycrystalline silicon thin film transistor (TFT) and manufacture method thereof |
| CN105931965A (en) * | 2016-04-28 | 2016-09-07 | 厦门天马微电子有限公司 | Semiconductor device and manufacturing method thereof |
| CN107017249A (en) * | 2017-03-30 | 2017-08-04 | 北京中电华大电子设计有限责任公司 | It is a kind of to improve the method for ESD protective device uniform conducting |
Non-Patent Citations (1)
| Title |
|---|
| 周刚，张雷: "FPGA输入输出模块ESD设计", 《微处理机》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112366202A (en) * | 2020-10-23 | 2021-02-12 | 长江存储科技有限责任公司 | Electrostatic discharge protection structure and manufacturing method thereof |
| CN112366202B (en) * | 2020-10-23 | 2024-06-07 | 长江存储科技有限责任公司 | Electrostatic discharge protection structure and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101211968B (en) | Manufacture method for thyristor for electro-static discharge | |
| CN102655149B (en) | PD SOI (partially-depleted silicon on insulator) technology-based body grid coupling ESD (electro-static discharge) protection structure | |
| CN102263102B (en) | Backward diode-triggered thyristor for electrostatic protection | |
| CN103646945A (en) | Integrated circuit power supply esd protection circuit | |
| CN102025135B (en) | ESD protective device | |
| CN103178058B (en) | A kind of diode auxiliary triggering esd protection circuit based on PD SOI | |
| CN102569360A (en) | Bidirectional triode thyristor based on diode auxiliary triggering | |
| US20210313421A1 (en) | Signal isolation apparatus and signal isolation method | |
| CN108122904A (en) | A kind of esd protection structure | |
| CN101937917A (en) | Electrostatic discharge safeguard structure in integrated circuit | |
| CN100474578C (en) | Electrostatic-proof protection structure using NMOS | |
| CN103165600A (en) | Electro-static discharge (ESD) protective circuit | |
| CN100452398C (en) | Electrostatic prevention protection structure of grids coupling used for high voltage drain spreading NMOS | |
| CN109411467A (en) | A method of reducing ESD protective device trigger voltage | |
| CN101789428A (en) | Embedded PMOS auxiliary trigger SCR structure | |
| CN102544068B (en) | Bidirectional controllable silicon device based on assistant triggering of PNP-type triodes | |
| CN102270658B (en) | Low-trigger-voltage and low-parasitic-capacitance silicon controlled structure | |
| Liu et al. | A novel latch-up free SCR-LDMOS for power-rail ESD clamp in half-bridge driver IC | |
| CN103839942B (en) | High pressure esd protection structure | |
| CN107546223B (en) | Waffle-shaped island type diode-triggered silicon controlled electrostatic protection device | |
| CN102544067B (en) | Bidirectional controllable silicon device based on assistant triggering of N-channel metal oxide semiconductor (NMOS) tubes | |
| CN102569295B (en) | Bidirectional thyristor device based on capacitor-assisted trigger | |
| CN102544066B (en) | Bidirectional controllable silicon device based on assistant triggering of NPN-type triodes | |
| CN109742070A (en) | A kind of silicon-controlled electrostatic protection device of FDSOI | |
| CN104143549A (en) | Electrostatic discharge protective circuit layout and integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190301 |
|
| WD01 | Invention patent application deemed withdrawn after publication |