CN109411335B - Pixel structure and manufacturing method thereof - Google Patents

Pixel structure and manufacturing method thereof Download PDF

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CN109411335B
CN109411335B CN201811203556.5A CN201811203556A CN109411335B CN 109411335 B CN109411335 B CN 109411335B CN 201811203556 A CN201811203556 A CN 201811203556A CN 109411335 B CN109411335 B CN 109411335B
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layer
electrode
heavily doped
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CN109411335A (en
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金利波
朱翀煜
岳欢
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Shanghai Yirui Optoelectronics Technology Co ltd
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Shanghai Yirui Optoelectronics Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
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    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
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    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
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    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L31/115—Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation
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Abstract

The invention provides a pixel structure and a manufacturing method thereof, wherein the method comprises the following steps: forming a first metal layer and an N-type heavily doped layer on a substrate; etching the two layers based on a first mask plate to form a data line, a drain electrode, a source electrode and a bottom electrode; then forming an active material layer, etching the active material layer and the N-type heavily doped layer based on a second mask plate to form a first contact area, a second contact area and an N-type area, and simultaneously forming an active area and an intrinsic area; then forming a P-type heavily doped layer and a top electrode material layer, and etching the two layers based on a third mask plate to form a P-type region and a top electrode; then, an insulating layer is formed and is etched on the basis of a fourth mask plate, and a through hole exposing the top electrode is formed; and then forming a second metal layer, and etching the second metal layer based on a fifth mask plate to form a gate electrode, a common electrode and a scanning line. The invention solves the problem of higher production cost caused by more photoetching times in the existing manufacturing method.

Description

Pixel structure and manufacturing method thereof
Technical Field
The invention relates to the fields of medical radiation imaging, industrial flaw detection, security inspection and the like, in particular to a pixel structure and a manufacturing method thereof.
Background
Flat panel image sensors, particularly large-sized flat panel image sensors, are typically tens of centimeters, millions to tens of millions of pixels in area. The method is generally applied to the fields of medical radiation imaging, industrial flaw detection, security inspection and the like. In the application of an X-ray image detector, the area is generally required to reach 43cm by 43cm, so that the amorphous silicon technology is the mainstream at present.
As shown in fig. 1, a conventional large flat panel image sensor of amorphous silicon technology generally includes: a substrate 1 (which may be glass or plastic material), all sensors being disposed on the substrate 1; pixel units 2, each pixel unit 2 being arranged on the substrate 1 in a two-dimensional array, each pixel unit 2 generally including a photodiode PD (photodiode) and a switching element TFT, the photodiode PD being connected to the switching element TFT through a pixel electrode; a scanning line 3 and a data line 4 for controlling each pixel unit 2; and a common electrode 5 for supplying a voltage of each photodiode PD. The basic principle is that a negative voltage (for example, -8V) is applied to the common electrode 5 to place the photodiode PD in a reverse bias state, the data line 4 is connected to about 0V, and the scan line 3 is connected to about-10V to turn off the switching element TFT; when light is irradiated, the photodiode PD generates optical charges, the scanning line 3 is connected with a voltage of about 15V to turn on the switching element TFT, and the optical charges generated by the photodiode PD flow to an external circuit through the data line 4 to complete a row of data reading; then, the switching element TFT is turned off, and the next line scanning is performed.
The conventional pixel structure generally adopts an amorphous silicon TFT/amorphous silicon diode structure, a top view of which is shown in fig. 2, and a cross-sectional view of fig. 2 along the AA' direction is shown in fig. 3; as can be seen from fig. 3, in the conventional pixel structure, 7 times of photolithography (i.e., 7 masks) are required to form the gate 102, the active region 104, the source/drain 105, the second passivation layer 106, the diode 107, the via 109, and the common electrode 110, respectively; also, in the fabrication process, two times of fabrication of amorphous silicon are required to form the active region of the switching element and the intrinsic region of the diode, respectively. Therefore, the manufacturing method of the conventional pixel structure has high production cost due to more photoetching times.
Therefore, a new pixel structure and a method for fabricating the same are needed to solve the above-mentioned problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a pixel structure and a manufacturing method thereof, which are used to solve the problem of high production cost caused by a large number of photolithography processes in the conventional manufacturing method.
To achieve the above and other related objects, the present invention provides a method for fabricating a pixel structure, the method comprising:
s1: providing a substrate, and sequentially forming a first metal layer and an N-type heavily doped layer on the upper surface of the substrate from bottom to top;
s2: based on a first mask plate, etching the N-type heavily doped layer and the first metal layer to enable the first metal layer to form a data line, a drain electrode, a source electrode and a bottom electrode on the substrate; the drain electrode is electrically connected with the data line, and the source electrode is electrically connected with the bottom electrode;
s3: forming an active material layer on the upper surface of the structure obtained in the step S2, and etching the active material layer and the N-type heavily doped layer based on a second mask plate, so that the N-type heavily doped layer forms a first contact region and a second contact region in the switch tube region, and forms an N-type region in the diode region, and at the same time, the active material layer forms an active region in the switch tube region, and forms an intrinsic region in the diode region;
s4: sequentially forming a P-type heavily doped layer and a top electrode material layer on the upper surface of the structure obtained in the step S3 from bottom to top, etching the top electrode material layer and the P-type heavily doped layer based on a third mask plate, enabling the P-type heavily doped layer to form a P-type region in the diode region, and enabling the top electrode material layer to form a top electrode in the diode region; wherein the N-type region, the intrinsic region and the P-type region form a PIN junction;
s5: forming an insulating layer on the upper surface of the structure obtained in the step S4, and etching the insulating layer based on a fourth mask plate to form a via hole exposing the top electrode above the diode region; and
s6: forming a second metal layer on the upper surface of the structure obtained in the step S5, and etching the second metal layer based on a fifth mask plate, so that the second metal layer forms a gate electrode in the switch tube region to form a top gate structure switch tube, forms a common electrode filling the via hole above the diode region, and forms a scan line electrically connected to the gate electrode outside the switch tube region; wherein the common electrode and the top electrode are electrically connected.
Optionally, the manufacturing method further includes S7: and forming a protective layer on the upper surface of the structure obtained in step S6.
Optionally, the protective layer is formed using a coating process.
Optionally, a specific method for forming the data line, the drain electrode, the source electrode and the bottom electrode in S2 includes:
s2-1 a: spin-coating a photoresist on the upper surface of the N-type heavily doped layer, and exposing and developing the photoresist based on the first mask plate to form a patterned photoresist layer;
s2-2 a: sequentially etching the N-type heavily doped layer and the first metal layer by taking the patterned photoresist layer as a mask, so that the first metal layer forms a data line, a drain electrode, a source electrode and a bottom electrode on the substrate; and
s2-3 a: and removing the patterned photoresist layer.
Optionally, a specific method for forming the data line, the drain electrode, the source electrode and the bottom electrode in S2 includes:
s2-1 b: spin-coating a photoresist on the upper surface of the N-type heavily doped layer, and exposing and developing the photoresist based on the first mask plate to form a patterned photoresist layer;
s2-2 b: etching the N-type heavily doped layer by taking the patterned photoresist layer as a mask so as to transfer the photoetching pattern in the patterned photoresist layer into the N-type heavily doped layer;
s2-3 b: removing the patterned photoresist layer;
s2-4 b: and etching the first metal layer by taking the etched N-type heavily doped layer as a mask, so that the first metal layer forms a data line, a drain electrode, a source electrode and a bottom electrode on the substrate.
Optionally, a specific method of forming the first contact region, the second contact region, the N-type region, the active region and the intrinsic region in S3 includes:
s3-1 a: spin-coating a photoresist on the upper surface of the active material layer, and exposing and developing the photoresist based on the second mask plate to form a patterned photoresist layer;
s3-2 a: sequentially etching the active material layer and the N-type heavily doped layer by taking the patterned photoresist layer as a mask, so that the N-type heavily doped layer forms a first contact region and a second contact region in the switch tube region and an N-type region in the diode region, and simultaneously the active material layer forms an active region in the switch tube region and an intrinsic region in the diode region; and
s3-3 a: and removing the patterned photoresist layer.
Optionally, a specific method of forming the first contact region, the second contact region, the N-type region, the active region and the intrinsic region in S3 includes:
s3-1 b: spin-coating a photoresist on the upper surface of the active material layer, and exposing and developing the photoresist based on the second mask plate to form a patterned photoresist layer;
s3-2 b: etching the active material layer by taking the patterned photoresist layer as a mask so as to transfer a photoetching pattern in the patterned photoresist layer into the active material layer, so that the active material layer forms an active region in the switch tube region and an intrinsic region in the diode region;
s3-3 b: removing the patterned photoresist layer;
s3-4 b: and etching the N-type heavily doped layer by taking the etched active material layer as a mask, so that the N-type heavily doped layer forms a first contact region and a second contact region in the switch tube region and forms an N-type region in the diode region.
Optionally, the first contact region and the drain electrode form an ohmic contact, and the second contact region and the source electrode form an ohmic contact.
Optionally, a specific method for forming the P-type region and the top electrode in S4 includes:
s4-1 a: spin-coating a photoresist on the upper surface of the top electrode material layer, and exposing and developing the photoresist based on the third mask plate to form a patterned photoresist layer;
s4-2 a: taking the patterned photoresist layer as a mask, sequentially etching the top electrode material layer and the P-type heavily doped layer to enable the P-type heavily doped layer to form a P-type region in the diode region, and enabling the top electrode material layer to form a top electrode in the diode region; and
s4-3 a: and removing the patterned photoresist layer.
Optionally, a specific method for forming the P-type region and the top electrode in S4 includes:
s4-1 b: spin-coating a photoresist on the upper surface of the top electrode material layer, and exposing and developing the photoresist based on the third mask plate to form a patterned photoresist layer;
s4-2 b: etching the top electrode material layer by taking the patterned photoresist layer as a mask so as to transfer the photoetching pattern in the patterned photoresist layer into the top electrode material layer, and enabling the top electrode material layer to form a top electrode in the diode region;
s4-3 b: removing the patterned photoresist layer;
s4-4 b: and etching the P-type heavily doped layer by taking the etched top electrode material layer as a mask, so that the P-type heavily doped layer forms a P-type region in the diode region.
Optionally, when the P-type heavily doped layer is etched in S4, the method further includes a step of thinning the active region.
Optionally, thinning the active region is achieved by setting the actual etching time of the P-type heavily doped layer to be longer than the etching time required for removing the P-type heavily doped layer.
Optionally, the ratio of the thickness of the thinned active region to the thickness of the original active region is 1/20-1/2.
Optionally, the specific method for forming the via hole in S5 includes:
s5-1: spin-coating a photoresist on the upper surface of the insulating layer, and exposing and developing the photoresist based on the fourth mask plate to form a patterned photoresist layer;
s5-2: etching the insulating layer by taking the patterned photoresist layer as a mask so as to form a via hole exposing the top electrode above the diode region; and
s5-3: and removing the patterned photoresist layer.
Optionally, a specific method for forming the gate electrode, the common electrode, and the scan line in S6 includes:
s6-1: spin-coating a photoresist on the upper surface of the second metal layer, and exposing and developing the photoresist based on the fifth mask plate to form a patterned photoresist layer;
s6-2: etching the second metal layer by taking the patterned photoresist layer as a mask, so that the second metal layer forms a gate electrode in the switch tube area, forms a common electrode for filling the via hole above the diode area, and forms a scanning line electrically connected with the gate electrode outside the switch tube area; and
s6-3: and removing the patterned photoresist layer.
The present invention also provides a pixel structure, comprising:
a substrate, a first electrode and a second electrode,
the data line, the drain electrode, the source electrode and the bottom electrode are formed on the upper surface of the substrate, the area where the drain electrode and the source electrode are located is a switching tube area, the area where the bottom electrode is located is a diode area, the drain electrode is electrically connected with the data line, and the source electrode is electrically connected with the bottom electrode;
the first contact area and the second contact area are formed in the switch tube area, and the N-type area is formed in the diode area; the first contact region is positioned on the upper surface of the drain electrode, the second contact region is positioned on the upper surface of the source electrode, and the N-type region is positioned on the upper surface of the bottom electrode;
an active region formed in the switching tube region, and an intrinsic region formed in the diode region; the active region is positioned on the upper surface of the substrate among the upper surface of the first contact region, the upper surface of the second contact region, the upper surface of the substrate between the first contact region and the second contact region, and the intrinsic region is positioned on the upper surface of the N-type region;
the P-type region and the top electrode are formed in the diode region; the P-type region is positioned on the upper surface of the intrinsic region, the top electrode is positioned on the upper surface of the P-type region, and the N-type region, the intrinsic region and the P-type region form a PIN junction;
the insulating layer is formed on the switching tube region and the outer side of the switching tube region as well as on the diode region and the outer side of the diode region, and the insulating layer forms a through hole exposing the top electrode above the diode region;
the gate electrode is formed in the switch tube area and is positioned on the upper surface of the insulating layer, so that the switch tube forms a switch tube with a top gate structure;
the common electrode is formed above the diode region, is positioned on the upper surface of the insulating layer and in the via hole, and is electrically connected with the top electrode; and
and the scanning line is formed outside the switch tube region, is positioned on the upper surface of the insulating layer and is electrically connected with the gate electrode.
Optionally, the pixel structure further includes: and the protective layer is formed above and outside the switch tube region and above and outside the diode region.
Optionally, the ratio of the thickness of the active region to the thickness of the intrinsic region is 1/20-1/2.
Optionally, the first contact region forms an ohmic contact with the drain electrode, and the second contact region forms an ohmic contact with the source electrode.
As described above, the pixel structure and the manufacturing method thereof of the present invention have the following advantages: according to the invention, the top gate structure TFT and the PIN structure PD are used, in the manufacturing process, the data line, the source electrode and the drain electrode of the TFT and the bottom electrode of the PD are in the same layer (namely manufactured by the same photoetching plate), the active area of the TFT and the intrinsic area of the PD are in the same layer (namely manufactured by the same photoetching plate), the scanning line, the common electrode and the gate electrode of the TFT are in the same layer (namely manufactured by the same photoetching plate), the pixel structure can be manufactured by only 5 photoetching processes (namely 5 mask plates), and the process difficulty and the production cost are greatly reduced; the invention also realizes that the active region of the TFT and the intrinsic region of the PD are on the same layer of amorphous silicon, thereby greatly improving the yield of the pixel structure; meanwhile, the shapes of the first contact area, the second contact area and the N-type area are defined by defining the bottom electrode and the mask plate of the active area without an additional mask plate, so that the photoetching times are further reduced, and the process difficulty and the production cost are further reduced.
Drawings
Fig. 1 is a schematic structural diagram of a large flat panel image sensor in the prior art.
Fig. 2 is a top view of a pixel unit in the prior art.
Fig. 3 is a cross-sectional view of the pixel cell shown in fig. 2 along direction AA'.
Fig. 4 is a flow chart of a method for fabricating a pixel structure according to the present invention.
Fig. 5 to 16 are schematic structural diagrams illustrating steps of fabricating a pixel structure according to the present invention.
Fig. 17 is a top view of the pixel structure of the present invention, wherein fig. 16 is a cross-sectional view of the pixel structure of fig. 17 along the BB' direction.
Description of the element reference numerals
1 substrate 2 pixel unit
3 scanning lines and 4 data lines
5 common electrode
101 substrate 102 gate
103 first passivation layer 104 active region
105 source drain 106 second passivation layer
107 diode 108 insulating layer
109 via 110 common electrode
201 substrate 202 first metal layer
203N type heavily doped layer 204 data line
205 drain 206 source
207 bottom electrode 208 active material layer
209 first contact region 210 second contact region
211N type region 212 active region
213 intrinsic region 214P-type heavily doped layer
215 top electrode material layer 216P-type region
217 top electrode 218 insulating layer
219 Via 220 second Metal layer
221 gate electrode 222 common electrode
223 scan line 224 protection layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 4 to 17. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 4, the present embodiment provides a method for manufacturing a pixel structure, where the method includes:
s1: providing a substrate 201, and sequentially forming a first metal layer 202 and an N-type heavily doped layer 203 on the upper surface of the substrate 201 from bottom to top;
s2: based on a first mask plate, etching the N-type heavily doped layer 203 and the first metal layer 202, so that the first metal layer 202 forms a data line 204, a drain 205, a source 206 and a bottom electrode 207 on the substrate 201; the region where the drain 205 and the source 206 are located is a switching tube region, the region where the bottom electrode 207 is located is a diode region, the drain 205 is electrically connected with the data line 204, and the source 206 is electrically connected with the bottom electrode 207;
s3: forming an active material layer 208 on the upper surface of the structure obtained in S2, and etching the active material layer 208 and the N-type heavily doped layer 203 based on a second mask, so that the N-type heavily doped layer 203 forms a first contact region 209 and a second contact region 210 in the switch tube region, and an N-type region 211 in the diode region, and at the same time, the active material layer 208 forms an active region 212 in the switch tube region, and an intrinsic region 213 in the diode region;
s4: sequentially forming a P-type heavily doped layer 214 and a top electrode material layer 215 on the upper surface of the structure obtained in step S3 from bottom to top, and etching the top electrode material layer 215 and the P-type heavily doped layer 214 based on a third mask plate, so that the P-type heavily doped layer 214 forms a P-type region 216 in the diode region, and the top electrode material layer 215 forms a top electrode 217 in the diode region; wherein the N-type region 211, the intrinsic region 213, and the P-type region 216 form a PIN junction;
s5: forming an insulating layer 218 on the upper surface of the structure obtained in S4, and etching the insulating layer 218 based on a fourth mask, so as to form a via hole 219 above the diode region and exposing the top electrode 217; and
s6: forming a second metal layer 220 on the upper surface of the structure obtained in S5, and etching the second metal layer 220 based on a fifth mask plate, so that the second metal layer 220 forms a gate electrode 221 in the switch tube region to form a top gate switch tube, a common electrode 222 filling the via hole 219 is formed above the diode region, and a scan line 223 electrically connected to the gate electrode 221 is formed outside the switch tube region; wherein the common electrode 222 and the top electrode 217 are electrically connected.
Therefore, in the embodiment, the top gate TFT and the PIN PD are used, and in the manufacturing process, the data line, the source and the drain of the TFT, and the bottom electrode of the PD are in the same layer (i.e., manufactured by the same photolithography mask), the active region of the TFT and the intrinsic region of the PD are in the same layer (i.e., manufactured by the same photolithography mask), and the scan line, the common electrode, and the gate electrode of the TFT are in the same layer (i.e., manufactured by the same photolithography mask), so that the pixel structure can be manufactured by only 5 photolithography processes (i.e., 5 mask plates), thereby greatly reducing the process difficulty and the production cost; in the embodiment, the active region of the TFT and the intrinsic region of the PD are realized on the same layer of amorphous silicon, so that the yield of the pixel structure is greatly improved; meanwhile, the shapes of the first contact area, the second contact area and the N-type area are further defined by the bottom electrode and the mask plate of the active area, and an additional mask plate is not needed, so that the photoetching times are further reduced, and the process difficulty and the production cost are further reduced.
Referring to fig. 5 to 17, a method for fabricating the pixel structure according to the present embodiment will be described in detail with reference to fig. 4.
As shown in fig. 5 and 6, S1: a substrate 201 is provided, and a first metal layer 202 and an N-type heavily doped layer 203 are sequentially formed on the upper surface of the substrate 201 from bottom to top.
As an example, the first metal layer 202 is formed by a semiconductor process such as chemical vapor deposition or sputtering, and the first metal layer 202 may be a single-layer metal structure or a multi-layer metal stack structure, such as an aluminum layer metal structure, a silver layer metal structure, an aluminum/molybdenum metal stack structure, or a molybdenum/aluminum/molybdenum metal stack structure, and the thickness thereof is generally 10nm to 1000 nm.
As an example, a specific forming method of the N-type heavily doped layer 203 includes: forming an amorphous silicon layer on the upper surface of the first metal layer 202, and then performing N-type ion implantation on the amorphous silicon layer to form an N-type heavily doped layer 203; wherein the implanted ions are phosphorus ions. Specifically, the thickness of the N-type heavily doped layer 203 is generally 10nm to 200 nm.
As shown in fig. 7, S2: based on a first mask, etching the N-type heavily doped layer 203 and the first metal layer 202, so that the first metal layer 202 forms a data line 204, a drain 205, a source 206, and a bottom electrode 207 on the substrate 201 (specifically, as shown by a dashed line frame in fig. 7); the region where the drain 205 and the source 206 are located is a switching tube region (specifically, shown in fig. 16 as a dashed line frame marked as a TFT), the region where the bottom electrode 207 is located is a diode region (specifically, shown in fig. 16 as a dashed line frame marked as a PD), the drain 205 is electrically connected to the data line 204, and the source 206 is electrically connected to the bottom electrode 207.
As an example, a specific method of forming the data line, the drain electrode, the source electrode, and the bottom electrode includes:
s2-1 a: spin-coating a photoresist on the upper surface of the N-type heavily doped layer 203, and exposing and developing the photoresist based on the first mask plate to form a patterned photoresist layer;
s2-2 a: sequentially etching the N-type heavily doped layer 203 and the first metal layer 202 by using the patterned photoresist layer as a mask, so that the first metal layer 202 forms a data line 204, a drain 205, a source 206 and a bottom electrode 207 on the substrate 201; and
s2-3 a: and removing the patterned photoresist layer.
As another example, a specific method of forming the data line, the drain electrode, the source electrode, and the bottom electrode includes:
s2-1 b: spin-coating a photoresist on the upper surface of the N-type heavily doped layer 203, and exposing and developing the photoresist based on the first mask plate to form a patterned photoresist layer;
s2-2 b: etching the N-type heavily doped layer 203 by using the patterned photoresist layer as a mask so as to transfer the photoresist pattern in the patterned photoresist layer to the N-type heavily doped layer 203;
s2-3 b: removing the patterned photoresist layer;
s2-4 b: and etching the first metal layer 202 by using the etched N-type heavily doped layer as a mask, so that the first metal layer 202 forms a data line 204, a drain 205, a source 206 and a bottom electrode 207 on the substrate 201.
As shown in fig. 8 and 9, S3: forming an active material layer 208 on the upper surface of the structure obtained in S2, etching the active material layer 208 and the N-type heavily doped layer 203 based on a second mask, so that the N-type heavily doped layer 203 forms a first contact region 209 and a second contact region 210 in the switch tube region, and forms an N-type region 211 in the diode region, and at the same time, the active material layer 208 forms an active region 212 in the switch tube region, and forms an intrinsic region 213 in the diode region.
As an example, the active material layer 208 is formed by a semiconductor process such as chemical vapor deposition, and the material of the active material layer 208 is amorphous silicon, and the thickness of the active material layer is generally 300nm to 3000 nm.
As an example, a specific method of forming the first contact region, the second contact region, the N-type region, the active region, and the intrinsic region includes:
s3-1 a: spin-coating a photoresist on the upper surface of the active material layer 208, and exposing and developing the photoresist based on the second mask plate to form a patterned photoresist layer;
s3-2 a: sequentially etching the active material layer 208 and the N-type heavily doped layer 203 by using the patterned photoresist layer as a mask, so that the N-type heavily doped layer 203 forms a first contact region 209 and a second contact region 210 in the switch tube region, an N-type region 211 in the diode region, and simultaneously the active material layer 208 forms an active region 212 in the switch tube region and an intrinsic region 213 in the diode region; and
s3-3 a: and removing the patterned photoresist layer.
As another example, a specific method of forming the first contact region, the second contact region, the N-type region, the active region, and the intrinsic region includes:
s3-1 b: spin-coating a photoresist on the upper surface of the active material layer 208, and exposing and developing the photoresist based on the second mask plate to form a patterned photoresist layer;
s3-2 b: taking the patterned photoresist layer as a mask, etching the active material layer 208 to transfer the photoresist pattern in the patterned photoresist layer to the active material layer 208, so that the active material layer 208 forms an active region 212 in the switch tube region and an intrinsic region 213 in the diode region;
s3-3 b: removing the patterned photoresist layer;
s3-4 b: and etching the N-type heavily doped layer 203 by using the etched active material layer as a mask, so that the N-type heavily doped layer 203 forms a first contact region 209 and a second contact region 210 in the switch tube region, and forms an N-type region 211 in the diode region.
As an example, the first contact region 209 forms an ohmic contact with the drain electrode 205, and the second contact region 210 forms an ohmic contact with the source electrode 206.
As shown in fig. 10 and 11, S4: sequentially forming a P-type heavily doped layer 214 and a top electrode material layer 215 on the upper surface of the structure obtained in step S3 from bottom to top, and etching the top electrode material layer 215 and the P-type heavily doped layer 214 based on a third mask plate, so that the P-type heavily doped layer 214 forms a P-type region 216 in the diode region, and the top electrode material layer 215 forms a top electrode 217 in the diode region; wherein the N-type region 211, the intrinsic region 213, and the P-type region 216 form a PIN junction.
As an example, a specific forming method of the P-type heavily doped layer 214 includes: forming an amorphous silicon layer on the upper surface of the structure obtained in step S3, and then performing P-type ion implantation on the amorphous silicon layer to form a P-type heavily doped layer 214; wherein the implanted ions are boron ions. Specifically, the thickness of the P-type heavily doped layer 214 is generally 5nm to 50nm, so as to ensure that the formed PN junction has better performance and reduce the attenuation of light.
As an example, the top electrode material layer 215 is formed by a semiconductor process such as chemical vapor deposition or sputtering, and the material of the top electrode material layer 215 may be indium tin oxide or other transparent conductive materials (such as indium oxide or silver nanotube film), and the thickness thereof is generally 20nm to 100 nm.
As an example, a specific method of forming the P-type region and the top electrode includes:
s4-1 a: spin-coating a photoresist on the upper surface of the top electrode material layer 215, and exposing and developing the photoresist based on the third mask plate to form a patterned photoresist layer;
s4-2 a: sequentially etching the top electrode material layer 215 and the P-type heavily doped layer 214 by using the patterned photoresist layer as a mask, so that the P-type heavily doped layer 214 forms a P-type region 216 in the diode region, and the top electrode material layer 215 forms a top electrode 217 in the diode region; and
s4-3 a: and removing the patterned photoresist layer.
As another example, a specific method of forming the P-type region and the top electrode includes:
s4-1 b: spin-coating a photoresist on the upper surface of the top electrode material layer 215, and exposing and developing the photoresist based on the third mask plate to form a patterned photoresist layer;
s4-2 b: etching the top electrode material layer 215 by using the patterned photoresist layer as a mask to transfer the photoresist pattern in the patterned photoresist layer to the top electrode material layer 215, so that the top electrode material layer 215 forms a top electrode 217 in the diode region;
s4-3 b: removing the patterned photoresist layer;
s4-4 b: and etching the P-type heavily doped layer 214 by using the etched top electrode material layer as a mask, so that the P-type heavily doped layer 214 forms a P-type region 216 in the diode region.
As an example, when the P-type heavily doped layer 214 is etched in S4, the method further includes a step of thinning the active region 212 to reduce dark current and improve the controllability of the gate electrode on the active region. Specifically, in this embodiment, since the P-type heavily doped layer and the active region are both made of amorphous silicon, the active region can be thinned by setting the actual etching time of the P-type heavily doped layer 214 to be longer than the etching time required for removing the P-type heavily doped layer; if the etching time required for removing the P-type heavily doped layer is m seconds, in order to thin the thickness of the active region, only the actual etching time needs to be set to be longer than m seconds, and the specific actual etching time needs to be set according to the thickness to be thinned. It should be noted that, when the active region is thinned, the first metal layer and the top electrode have different etching selection ratios to the amorphous silicon material, so that the actual etching time is increased, and no influence is caused on other structural layers. Optionally, in this embodiment, a ratio of the thinned active region thickness to the original active region thickness is 1/20 to 1/2, that is, a ratio of the thinned active region thickness to the active material layer thickness is 1/20 to 1/2.
As shown in fig. 12 and 13, S5: an insulating layer 218 is formed on the upper surface of the structure obtained in S4, and based on a fourth mask, the insulating layer 218 is etched to form a via hole 219 above the diode region, which exposes the top electrode 217.
By way of example, the insulating layer 218 is formed by a semiconductor process such as chemical vapor deposition, and is made of silicon nitride or silicon oxide, and the thickness thereof is typically 50nm to 200 nm.
As an example, a specific method of forming the via hole includes:
s5-1: spin-coating a photoresist on the upper surface of the insulating layer 218, and exposing and developing the photoresist based on the fourth mask plate to form a patterned photoresist layer;
s5-2: etching the insulating layer 218 by using the patterned photoresist layer as a mask to form a via hole 219 above the diode region and exposing the top electrode 217; and
s5-3: and removing the patterned photoresist layer.
As shown in fig. 14 and 15, S6: forming a second metal layer 220 on the upper surface of the structure obtained in S5, and etching the second metal layer 220 based on a fifth mask plate, so that the second metal layer 220 forms a gate electrode 221 in the switch tube region to form a top gate switch tube, a common electrode 222 filling the via hole 219 is formed above the diode region, and a scan line 223 electrically connected to the gate electrode 221 is formed outside the switch tube region; wherein the common electrode 222 and the top electrode 217 are electrically connected.
As an example, the second metal layer 220 is formed by a semiconductor process such as chemical vapor deposition or sputtering, and the second metal layer 220 may be a single-layer metal structure or a multi-layer metal stacked structure, such as an aluminum layer metal structure, a silver layer metal structure, an aluminum/molybdenum metal stacked structure, or a molybdenum/aluminum/molybdenum metal stacked structure, and the thickness of the second metal layer is generally 10nm to 1000 nm.
As an example, a specific method of forming the gate electrode, the common electrode, and the scan line includes:
s6-1: spin-coating a photoresist on the upper surface of the second metal layer 220, and exposing and developing the photoresist based on the fifth mask plate to form a patterned photoresist layer;
s6-2: etching the second metal layer 220 by using the patterned photoresist layer as a mask, so that the second metal layer 220 forms a gate electrode 221 in the switch tube region, forms a common electrode 222 filling the via hole 219 above the diode region, and forms a scan line 223 electrically connected with the gate electrode 221 outside the switch tube region; and
s6-3: and removing the patterned photoresist layer.
As an example, as shown in fig. 16, the manufacturing method further includes S7: and a step of forming a protection layer 224 on the upper surface of the structure obtained in step S6. Specifically, the protective layer 224 is formed by a coating process.
As shown in fig. 16 and 17, the present embodiment further provides a pixel structure manufactured based on the above manufacturing method, where the pixel structure includes:
the substrate 201 is provided with a plurality of grooves,
a data line 204, a drain 205, a source 206 and a bottom electrode 207 formed on the upper surface of the substrate 201, wherein the region where the drain 205 and the source 206 are located is a switching tube region, the region where the bottom electrode 207 is located is a diode region, the drain 205 is electrically connected with the data line 204, and the source 206 is electrically connected with the bottom electrode 207;
a first contact region 209 and a second contact region 210 formed in the switching tube region, and an N-type region 211 formed in the diode region; the first contact region 209 is located on the upper surface of the drain 205, the second contact region 210 is located on the upper surface of the source 206, and the N-type region 211 is located on the upper surface of the bottom electrode 207;
an active region 212 formed in the switching tube region, and an intrinsic region 213 formed in the diode region; the active region 212 is located on the upper surface of the first contact region 209, the upper surface of the second contact region 210, the upper surface of the substrate 201 between the first contact region 209 and the second contact region 210, and the intrinsic region 213 is located on the upper surface of the N-type region 211;
a P-type region 216 and a top electrode 217 formed in the diode region; wherein the P-type region 216 is located on the upper surface of the intrinsic region 213, the top electrode 217 is located on the upper surface of the P-type region 216, and the N-type region 211, the intrinsic region 213 and the P-type region 216 form a PIN junction;
an insulating layer 218 formed on and outside the switching tube region and on and outside the diode region, the insulating layer 218 forming a via 219 over the diode region exposing the top electrode 217;
a gate electrode 221 formed in the switching tube region, wherein the gate electrode 221 is located on the upper surface of the insulating layer 218, so that the switching tube constitutes a top-gate switching tube;
a common electrode 222 formed over the diode region, the common electrode 222 being located on an upper surface of the insulating layer 218 and in the via 219 and electrically connected to the top electrode 217; and
and the scanning line 223 is formed outside the switching tube region, and the scanning line 223 is positioned on the upper surface of the insulating layer 218 and is electrically connected with the gate electrode 221.
As an example, the first contact region 209 forms an ohmic contact with the drain electrode 205, and the second contact region 210 forms an ohmic contact with the source electrode 206.
For example, the data line 204, the drain electrode 205, the source electrode 206, and the bottom electrode 207 may have the same material and thickness, and may have a single-layer metal structure or a multi-layer metal stacked structure, such as an aluminum layer metal structure, a silver layer metal structure, an aluminum/molybdenum metal stacked structure, or a molybdenum/aluminum/molybdenum metal stacked structure, and the thickness is generally 10nm to 1000 nm.
For example, the first contact region 209, the second contact region 210 and the N-type region 211 are made of the same material and have the same thickness, and are all made of a phosphorus-doped amorphous silicon material, and the thickness is generally 10nm to 200 nm.
As an example, the active region 212 and the intrinsic region 213 are made of the same material and are both amorphous silicon material; the thicknesses of the active region 212 and the intrinsic region 213 may be the same or different. Optionally, in this embodiment, the thicknesses of the active region 212 and the intrinsic region 213 are different; further optionally, the ratio of the thickness of the active region to the thickness of the intrinsic region is 1/20-1/2; wherein the thickness of the intrinsic region 213 is generally 300nm to 3000 nm.
As an example, the P-type region 216 is made of a boron-doped amorphous silicon material, and the thickness thereof is generally 5nm to 50nm, so as to ensure that the formed PN junction has better performance and can reduce the attenuation of light.
For example, the top electrode 217 is made of indium tin oxide or other transparent conductive materials (such as indium oxide or silver nanotube film), and the thickness thereof is generally 20nm to 100 nm.
The insulating layer 218 is made of silicon nitride or silicon oxide, and the thickness thereof is typically 50nm to 200 nm.
As an example, the gate electrode 221, the common electrode 222, and the scan line 223 are made of the same material, and may be a single-layer metal structure or a multi-layer metal stacked structure, such as an aluminum layer metal structure, a silver layer metal structure, an aluminum/molybdenum metal stacked structure, or a molybdenum/aluminum/molybdenum metal stacked structure; the thicknesses of the gate electrode 221, the common electrode 222 and the scan line on the upper surface of the insulating layer are also the same, and are generally 10nm to 1000 nm.
As an example, the pixel structure further includes: and the protective layer 224 is formed above and outside the switch tube region, above and outside the diode region.
In summary, the pixel structure and the manufacturing method thereof of the invention have the following beneficial effects: according to the invention, the top gate structure TFT and the PIN structure PD are used, in the manufacturing process, the data line, the source electrode and the drain electrode of the TFT and the bottom electrode of the PD are in the same layer (namely manufactured by the same photoetching plate), the active area of the TFT and the intrinsic area of the PD are in the same layer (namely manufactured by the same photoetching plate), the scanning line, the common electrode and the gate electrode of the TFT are in the same layer (namely manufactured by the same photoetching plate), the pixel structure can be manufactured by only 5 photoetching processes (namely 5 mask plates), and the process difficulty and the production cost are greatly reduced; the invention also realizes that the active region of the TFT and the intrinsic region of the PD are on the same layer of amorphous silicon, thereby greatly improving the yield of the pixel structure; meanwhile, the shapes of the first contact area, the second contact area and the N-type area are defined by defining the bottom electrode and the mask plate of the active area without an additional mask plate, so that the photoetching times are further reduced, and the process difficulty and the production cost are further reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (19)

1. A manufacturing method of a pixel structure is characterized by comprising the following steps:
s1: providing a substrate, and sequentially forming a first metal layer and an N-type heavily doped layer on the upper surface of the substrate from bottom to top;
s2: based on a first mask plate, etching the N-type heavily doped layer and the first metal layer to enable the first metal layer to form a data line, a drain electrode, a source electrode and a bottom electrode on the substrate; the drain electrode is electrically connected with the data line, and the source electrode is electrically connected with the bottom electrode;
s3: forming an active material layer on the upper surface of the structure obtained in the step S2, and etching the active material layer and the N-type heavily doped layer based on a second mask plate, so that the N-type heavily doped layer forms a first contact region and a second contact region in the switch tube region, and forms an N-type region in the diode region, and at the same time, the active material layer forms an active region in the switch tube region, and forms an intrinsic region in the diode region;
s4: sequentially forming a P-type heavily doped layer and a top electrode material layer on the upper surface of the structure obtained in the step S3 from bottom to top, etching the top electrode material layer and the P-type heavily doped layer based on a third mask plate, enabling the P-type heavily doped layer to form a P-type region in the diode region, and enabling the top electrode material layer to form a top electrode in the diode region; wherein the N-type region, the intrinsic region and the P-type region form a PIN junction;
s5: forming an insulating layer on the upper surface of the structure obtained in the step S4, and etching the insulating layer based on a fourth mask plate to form a via hole exposing the top electrode above the diode region; and
s6: forming a second metal layer on the upper surface of the structure obtained in the step S5, and etching the second metal layer based on a fifth mask plate, so that the second metal layer forms a gate electrode in the switch tube region to form a top gate structure switch tube, forms a common electrode filling the via hole above the diode region, and forms a scan line electrically connected to the gate electrode outside the switch tube region; wherein the common electrode and the top electrode are electrically connected.
2. The method for fabricating the pixel structure according to claim 1, further comprising S7: and forming a protective layer on the upper surface of the structure obtained in step S6.
3. The method of claim 2, wherein the protective layer is formed by a coating process.
4. The method for manufacturing the pixel structure according to claim 1, wherein the specific method for forming the data line, the drain electrode, the source electrode and the bottom electrode in S2 includes:
s2-1 a: spin-coating a photoresist on the upper surface of the N-type heavily doped layer, and exposing and developing the photoresist based on the first mask plate to form a patterned photoresist layer;
s2-2 a: sequentially etching the N-type heavily doped layer and the first metal layer by taking the patterned photoresist layer as a mask, so that the first metal layer forms a data line, a drain electrode, a source electrode and a bottom electrode on the substrate; and
s2-3 a: and removing the patterned photoresist layer.
5. The method for manufacturing the pixel structure according to claim 1, wherein the specific method for forming the data line, the drain electrode, the source electrode and the bottom electrode in S2 includes:
s2-1 b: spin-coating a photoresist on the upper surface of the N-type heavily doped layer, and exposing and developing the photoresist based on the first mask plate to form a patterned photoresist layer;
s2-2 b: etching the N-type heavily doped layer by taking the patterned photoresist layer as a mask so as to transfer the photoetching pattern in the patterned photoresist layer into the N-type heavily doped layer;
s2-3 b: removing the patterned photoresist layer;
s2-4 b: and etching the first metal layer by taking the etched N-type heavily doped layer as a mask, so that the first metal layer forms a data line, a drain electrode, a source electrode and a bottom electrode on the substrate.
6. The method of claim 1, wherein the specific method of forming the first contact region, the second contact region, the N-type region, the active region and the intrinsic region in S3 comprises:
s3-1 a: spin-coating a photoresist on the upper surface of the active material layer, and exposing and developing the photoresist based on the second mask plate to form a patterned photoresist layer;
s3-2 a: sequentially etching the active material layer and the N-type heavily doped layer by taking the patterned photoresist layer as a mask, so that the N-type heavily doped layer forms a first contact region and a second contact region in the switch tube region and an N-type region in the diode region, and simultaneously the active material layer forms an active region in the switch tube region and an intrinsic region in the diode region; and
s3-3 a: and removing the patterned photoresist layer.
7. The method of claim 1, wherein the specific method of forming the first contact region, the second contact region, the N-type region, the active region and the intrinsic region in S3 comprises:
s3-1 b: spin-coating a photoresist on the upper surface of the active material layer, and exposing and developing the photoresist based on the second mask plate to form a patterned photoresist layer;
s3-2 b: etching the active material layer by taking the patterned photoresist layer as a mask so as to transfer a photoetching pattern in the patterned photoresist layer into the active material layer, so that the active material layer forms an active region in the switch tube region and an intrinsic region in the diode region;
s3-3 b: removing the patterned photoresist layer;
s3-4 b: and etching the N-type heavily doped layer by taking the etched active material layer as a mask, so that the N-type heavily doped layer forms a first contact region and a second contact region in the switch tube region and forms an N-type region in the diode region.
8. The method as claimed in claim 1, 6 or 7, wherein the first contact region forms an ohmic contact with the drain electrode, and the second contact region forms an ohmic contact with the source electrode.
9. The method of claim 1, wherein the specific method for forming the P-type region and the top electrode in S4 comprises:
s4-1 a: spin-coating a photoresist on the upper surface of the top electrode material layer, and exposing and developing the photoresist based on the third mask plate to form a patterned photoresist layer;
s4-2 a: taking the patterned photoresist layer as a mask, sequentially etching the top electrode material layer and the P-type heavily doped layer to enable the P-type heavily doped layer to form a P-type region in the diode region, and enabling the top electrode material layer to form a top electrode in the diode region; and
s4-3 a: and removing the patterned photoresist layer.
10. The method of claim 1, wherein the specific method for forming the P-type region and the top electrode in S4 comprises:
s4-1 b: spin-coating a photoresist on the upper surface of the top electrode material layer, and exposing and developing the photoresist based on the third mask plate to form a patterned photoresist layer;
s4-2 b: etching the top electrode material layer by taking the patterned photoresist layer as a mask so as to transfer the photoetching pattern in the patterned photoresist layer into the top electrode material layer, and enabling the top electrode material layer to form a top electrode in the diode region;
s4-3 b: removing the patterned photoresist layer;
s4-4 b: and etching the P-type heavily doped layer by taking the etched top electrode material layer as a mask, so that the P-type heavily doped layer forms a P-type region in the diode region.
11. The method for manufacturing the pixel structure according to claim 1, 9 or 10, wherein the step of thinning the active region when etching the P-type heavily doped layer in S4 is further included.
12. The method according to claim 11, wherein the thinning of the active region is performed by setting an actual etching time of the P-type heavily doped layer to be longer than an etching time required for removing the P-type heavily doped layer.
13. The method as claimed in claim 11, wherein the ratio of the thinned thickness of the active region to the original thickness of the active region is 1/20-1/2.
14. The method for manufacturing the pixel structure according to claim 1, wherein the specific method for forming the via hole in the step S5 includes:
s5-1: spin-coating a photoresist on the upper surface of the insulating layer, and exposing and developing the photoresist based on the fourth mask plate to form a patterned photoresist layer;
s5-2: etching the insulating layer by taking the patterned photoresist layer as a mask so as to form a via hole exposing the top electrode above the diode region; and
s5-3: and removing the patterned photoresist layer.
15. The method for manufacturing the pixel structure according to claim 1, wherein the specific method for forming the gate electrode, the common electrode and the scan line in S6 includes:
s6-1: spin-coating a photoresist on the upper surface of the second metal layer, and exposing and developing the photoresist based on the fifth mask plate to form a patterned photoresist layer;
s6-2: etching the second metal layer by taking the patterned photoresist layer as a mask, so that the second metal layer forms a gate electrode in the switch tube area, forms a common electrode for filling the via hole above the diode area, and forms a scanning line electrically connected with the gate electrode outside the switch tube area; and
s6-3: and removing the patterned photoresist layer.
16. A pixel structure fabricated by the fabrication method according to any one of claims 1 to 15, wherein the pixel structure comprises:
a substrate, a first electrode and a second electrode,
the data line, the drain electrode, the source electrode and the bottom electrode are formed on the upper surface of the substrate, the area where the drain electrode and the source electrode are located is a switching tube area, the area where the bottom electrode is located is a diode area, the drain electrode is electrically connected with the data line, and the source electrode is electrically connected with the bottom electrode;
the first contact area and the second contact area are formed in the switch tube area, and the N-type area is formed in the diode area; the first contact region is positioned on the upper surface of the drain electrode, the second contact region is positioned on the upper surface of the source electrode, and the N-type region is positioned on the upper surface of the bottom electrode;
an active region formed in the switching tube region, and an intrinsic region formed in the diode region; the active region is positioned on the upper surface of the substrate among the upper surface of the first contact region, the upper surface of the second contact region, the upper surface of the substrate between the first contact region and the second contact region, and the intrinsic region is positioned on the upper surface of the N-type region;
the P-type region and the top electrode are formed in the diode region; the P-type region is positioned on the upper surface of the intrinsic region, the top electrode is positioned on the upper surface of the P-type region, and the N-type region, the intrinsic region and the P-type region form a PIN junction;
the insulating layer is formed on the switching tube region and the outer side of the switching tube region as well as on the diode region and the outer side of the diode region, and the insulating layer forms a through hole exposing the top electrode above the diode region;
the gate electrode is formed in the switch tube area and is positioned on the upper surface of the insulating layer, so that the switch tube forms a switch tube with a top gate structure;
the common electrode is formed above the diode region, is positioned on the upper surface of the insulating layer and in the via hole, and is electrically connected with the top electrode; and
and the scanning line is formed outside the switch tube region, is positioned on the upper surface of the insulating layer and is electrically connected with the gate electrode.
17. The pixel structure of claim 16, further comprising: and the protective layer is formed above and outside the switch tube region and above and outside the diode region.
18. The pixel structure of claim 16, wherein a ratio of the active region thickness to the intrinsic region thickness is 1/20-1/2.
19. The pixel structure of claim 16, wherein the first contact region forms an ohmic contact with the drain electrode and the second contact region forms an ohmic contact with the source electrode.
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