CN106409846B - Manufacture the method and dot structure of dot structure - Google Patents
Manufacture the method and dot structure of dot structure Download PDFInfo
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- CN106409846B CN106409846B CN201510448218.8A CN201510448218A CN106409846B CN 106409846 B CN106409846 B CN 106409846B CN 201510448218 A CN201510448218 A CN 201510448218A CN 106409846 B CN106409846 B CN 106409846B
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Abstract
The invention discloses a kind of method and dot structure for manufacturing dot structure, it includes: form source electrode, drain electrode and first capacitor electrode；Form a part of semiconductor layer contact source electrode and a part of drain electrode；It forms grid and the second capacitance electrode, the second capacitance electrode is substantially aligned with first capacitor electrode；Form the gate dielectric layer between semiconductor layer, source electrode, drain electrode and first capacitor electrode, with grid and the second capacitance electrode；Protective layer is formed in the top of source electrode, drain electrode, first capacitor electrode, semiconductor layer, grid and the second capacitance electrode；And rectangular pixel electrode, pixel electrode are substantially aligned with first capacitor electrode on the protection layer.The method can be used to manufacture the dot structure comprising bottom gate thin film transistor or the dot structure comprising top gate type thin film transistor in the case where not changing perimeter circuit, and be formed by both dot structures all to have enough capacitors.
Description
Technical field
The invention relates to a kind of methods and dot structure for manufacturing dot structure.
Background technique
Electronic Paper is a kind of equally ultra-thin light, flexible and low power consumption the display technology of sensitive paper, at present with electrophoresis showed
Technology (electrophoretic display；EPD) and based on the research of cholesterol liquid crystal display technology.Wherein electrophoresis-type is aobvious
Show that technology is most widely adopted, in 2009, global 90% or more Electronic Paper was all made of electrophoretic display technology.
Electric paper display (or electronic ink display) generally comprises the first transparent substrate, common electrode layer, electronics
Ink layer, pixel array and the second transparent substrate.Pixel array includes multiple dot structures.Each dot structure includes at least
One membrane transistor.Membrane transistor includes grid, gate dielectric layer, semiconductor layer, source electrode and drain electrode.
The position of grid according to membrane transistor, can be divided into bottom gate thin film transistor and top gate type thin film transistor.
But in general, if dot structure there will be a good device property, such as with enough capacitances, include one of type
The dot structure of state (such as bottom gate type) membrane transistor and its circuit layout of perimeter circuit, which can not directly cover, to be used in comprising another
A kind of dot structure and its perimeter circuit of kenel (such as top gate type) membrane transistor.In this way, in exploitation comprising wherein
After a kind of dot structure of kenel membrane transistor and its circuit layout of perimeter circuit, time design need to be expended again comprising another
A kind of dot structure of kenel membrane transistor and its circuit layout of perimeter circuit.
Summary of the invention
The purpose of the present invention is to provide a kind of methods for manufacturing dot structure, in the case where not changing perimeter circuit,
It can be used to manufacture the dot structure comprising bottom gate thin film transistor or the dot structure comprising top gate type thin film transistor, and institute
Both dot structures formed all have enough capacitors.In this way, brilliant comprising one of kenel thin-film electro in exploitation
After the dot structure of body and its circuit layout of perimeter circuit, just it is not required to expend time design again to include another kenel film
The dot structure of transistor and its circuit layout of perimeter circuit.
The present invention provides a kind of method for manufacturing dot structure, it includes: form source electrode, drain electrode and first capacitor electrode；
Form a part of semiconductor layer contact source electrode and a part of drain electrode；Form grid and the second capacitance electrode, the second capacitor electricity
Pole is substantially aligned with first capacitor electrode；It is formed and is located at semiconductor layer, source electrode, drain electrode and first capacitor electrode, with grid and second
Gate dielectric layer between capacitance electrode；In source electrode, drain electrode, first capacitor electrode, semiconductor layer, grid and the second capacitance electrode
Top forms protective layer；And rectangular pixel electrode, pixel electrode are substantially aligned with first capacitor electrode on the protection layer.
An embodiment according to the present invention, the second capacitance electrode and pixel electrode equipotential.
An embodiment according to the present invention, formed be located at semiconductor layer, source electrode, drain electrode and first capacitor electrode, with grid and
Gate dielectric layer step between second capacitance electrode is carried out after forming source electrode, drain electrode and first capacitor electrode step, side
Method also includes to form the first opening through gate dielectric layer, and form grid and the second capacitance electrode step comprising forming the second capacitor
Electrode is in the first opening.
An embodiment according to the present invention, method also include to form the second opening through protective layer, and the second opening is substantially aligned with
First opening, and forming pixel electrode step includes to form pixel electrode in the second opening, and contact the second capacitance electrode.
An embodiment according to the present invention, method also include to form third opening through drain electrode and be substantially aligned with the first opening,
And grid and the second capacitance electrode step are formed comprising forming the second capacitance electrode in third opening.
The present invention separately provides a kind of dot structure, it includes source electrode, drain electrode and first capacitor electrode, wherein first capacitor
Electrode has common voltage current potential；Semiconductor layer contacts a part of source electrode and a part of drain electrode；Grid and the second capacitor electricity
Pole, grid are located in semiconductor layer, source electrode and drain electrode, and the second capacitance electrode is located on first capacitor electrode, the second capacitance electrode
It is substantially aligned with first capacitor electrode；Gate dielectric layer is located at semiconductor layer, source electrode, drain electrode and first capacitor electrode, with grid and the
Between two capacitance electrodes；Protective layer is located at source electrode, drain electrode, first capacitor electrode, semiconductor layer, grid and the second capacitance electrode
Top；And pixel electrode, it is located above protective layer.
An embodiment according to the present invention, the second capacitance electrode and pixel electrode equipotential.
An embodiment according to the present invention, gate dielectric layer have the first opening, and the second capacitance electrode is located in the first opening.
An embodiment according to the present invention, protective layer is located at the first overthe openings and is substantially aligned with first with the second opening to be opened
Mouthful, pixel electrode is located in the second opening, and contacts the second capacitance electrode.
An embodiment according to the present invention, drain electrode is located at the first opening lower section and is substantially aligned with first with third opening opens
Mouthful, the second capacitance electrode is located in third opening.
According to above-mentioned, the present invention provides a kind of method for manufacturing dot structure can in the case where not changing perimeter circuit
To manufacture the dot structure comprising bottom gate thin film transistor or the dot structure comprising top gate type thin film transistor, and institute's shape
At both dot structures all there is enough capacitors.
Detailed description of the invention
For above and other purpose, feature, advantage and embodiment of the invention can be clearer and more comprehensible, institute's accompanying drawings are said
It is bright as follows:
Figure 1A-Fig. 1 F is method the cuing open in each operation stage for being painted manufacture dot structure according to an embodiment of the invention
Face schematic diagram.
Fig. 2A-Fig. 2 F is to be painted the method for manufacture dot structure according to another embodiment of the present invention in each operation stage
Diagrammatic cross-section.
Specific embodiment
In order to keep the narration of present disclosure more detailed with it is complete, below for state sample implementation of the invention and specific
Embodiment proposes illustrative description；But this not implements or uses the unique forms of the specific embodiment of the invention.Following institute
Disclosed each embodiment can be combined with each other or replace in the case of beneficial, can also add other implementations in one embodiment
Example, and without further record or explanation.
The present invention provides a kind of method for manufacturing dot structure.Figure 1A-Fig. 1 F is painted system according to an embodiment of the invention
Make diagrammatic cross-section of the method in each operation stage of dot structure.As shown in Figure 1A, substrate 110 is provided.Substrate 110 can be
Single or multi-layer structure, material can be glass, quartz, transparent polymer material or other suitable materials.
Please continue to refer to Figure 1A.Source S, drain D and first capacitor electrode C1 are formed on substrate 110, source S, drain D
And first capacitor electrode C1 is separated from each other.In one embodiment, first code-pattern forms conductive layer (not being painted) on substrate 110.
Such as conductive layer is formed on substrate 110 using sputter, evaporation process or other film deposition techniques.Conductive layer can be single layer
Or multilayered structure, it may include metal or alloy, such as molybdenum, chromium, aluminium, neodymium, titanium, copper, silver, gold, zinc, indium, gallium, other are suitable
Metal or combinations of the above.In one embodiment, using the first light shield, the first lithographic and etch process are carried out to conductive layer, with
Form source S, drain D and first capacitor electrode C1.In one embodiment, source S, drain D and first capacitor electrode are being formed
When C1, while data line (not being painted) and common electrode wire (not being painted) are formed on substrate 110, source S, drain D, the first electricity
Hold electrode C1, data line and common electrode wire and belongs to same patterned conductive layer.In one embodiment, first capacitor electrode C1 coupling
Common electrode wire is connect or connects, so first capacitor electrode C1 there can be common voltage current potential.Therefore in the present embodiment, first
Capacitance electrode C1 can claim mutual capacitance electrode again.
Then, as shown in Figure 1B, semiconductor layer SE is formed in the top of source S and drain D, contacts a part of source S
And a part of drain D.In one embodiment, first code-pattern formation is partly led on source S, drain D and first capacitor electrode C1
Body material layer (is not painted).Such as using vacuum coating (such as physical vaporous deposition or chemical vapour deposition technique) or liquid
It is coated with (such as rotary coating or slot coated) and forms semiconductor material layer.Semiconductor material layer may include amorphous silicon, polysilicon,
Microcrystal silicon, monocrystalline silicon, organic semiconductor, oxide semiconductor or other suitable materials.In one embodiment, semiconductor layer SE
Include metal oxide or alloyed oxide, such as indium oxide, indium gallium zinc, indium gallium, indium zinc oxide, zinc oxide, oxygen
Change zinc-tin, chromium oxide tin, gallium oxide tin, titanium oxide tin, copper oxide aluminium, strontium oxide strontia copper, sulphur lanthana copper, other suitable materials
Or combinations of the above.In one embodiment, using the second light shield, the second lithographic and etch process are carried out to semiconductor material layer,
To form semiconductor layer SE.In other embodiments, it is initially formed semiconductor layer, then re-forms source electrode, drain electrode and first capacitor
Electrode.
As shown in Figure 1 C, gate dielectric layer is formed in the top of semiconductor layer SE, source S, drain D and first capacitor electrode C1
120.In one embodiment, code-pattern forms gate dielectric layer on semiconductor layer SE, source S, drain D and first capacitor electrode C1
120.Such as gate dielectric layer 120 is formed using chemical vapour deposition technique or other suitable film deposition techniques.Gate dielectric layer
120 can be single or multi-layer structure, may include organic dielectric material, inorganic dielectric material or combinations of the above.Organic dielectric materials
For example, polyimide (Polyimide, PI), other suitable materials or combinations of the above；Inorganic Dielectric Material is, for example, oxygen
SiClx, silicon nitride, silicon oxynitride, other suitable materials or combinations of the above.
As shown in figure iD, using third light shield, third lithographic and etch process is carried out to gate dielectric layer 120, passed through with being formed
Wear the first opening O1 of the gate dielectric layer 120 and third opening O3 through drain D.Third opening O3 is substantially aligned with the first opening
O1.It is described herein to refer to that an element is completely heavy to the upright projection of substrate 110 to the upright projection of substrate 110 and another element
Repeatedly or part overlaps.That is, third is open, O3 is open O1 to the vertical of substrate 110 with first to the upright projection of substrate 110
Shadow is delivered directly to overlap or partially overlap completely.As shown in figure iD, third opening O3 is located at the first opening to the upright projection of substrate 110
O1 is in the upright projection of substrate 110.
Please continue to refer to Fig. 1 D.After formation first is open O1 and third opening O3, grid are formed on gate dielectric layer 120
Pole G and the second capacitance electrode C2, the second capacitance electrode C2 are substantially aligned with first capacitor electrode C1.Grid G and the second capacitance electrode
C2 is separated from each other.Gate dielectric layer 120 is located at semiconductor layer SE, source S, drain D and first capacitor electrode C1, with grid G and
Between two capacitance electrode C2.In one embodiment, first code-pattern forms conductive layer (not being painted) on gate dielectric layer 120.Such as
Conductive layer is formed on gate dielectric layer 120 using sputter, evaporation process or other film deposition techniques.Conductive layer can be single layer
Or multilayered structure, it may include metal or alloy, such as molybdenum, chromium, aluminium, neodymium, titanium, copper, silver, gold, zinc, indium, gallium, other are suitable
Metal or combinations of the above.Then, in one embodiment, using the 4th light shield, the 4th lithographic and etching work are carried out to conductive layer
Skill, to form grid G and the second capacitance electrode C2 on gate dielectric layer 120.In one embodiment, grid G and second is being formed
Capacitance electrode C2 is formed simultaneously scan line (not being painted) in gate dielectric layer 120 on gate dielectric layer 120, grid G, the second electricity
Hold electrode C2 and scan line belongs to same patterned conductive layer.In one embodiment, as shown in figure iD, grid G, which is formed in, partly leads
Above body layer SE, and it is substantially aligned with semiconductor layer SE.Second capacitance electrode C2 is in addition to being formed in the top first capacitor electrode C1
Outside, it is also formed in the first opening O1 and third opening O3.
Then, as referring to figure 1E, in source S, drain D, first capacitor electrode C1, semiconductor layer SE, grid G and the second electricity
The top for holding electrode C2 forms protective layer 130.In one embodiment, in source S, drain D, first capacitor electrode C1, semiconductor
First code-pattern forms protective layer 130 on layer SE, grid G and the second capacitance electrode C2.Such as using chemical vapour deposition technique or
Other film deposition techniques form protective layer 130.Protective layer 130 can be single or multi-layer structure, may include organic dielectric material,
Inorganic dielectric material or combinations of the above.Then, in one embodiment, using third light shield, the 5th lithographic is carried out to protective layer 130
And etch process exposes the second capacitance electrode C2 to form the second opening O2 through protective layer 130.Second opening O2 is big
Cause the first opening of alignment O1.
As shown in fig. 1F, pixel electrode PE is formed above protective layer 130, pixel electrode PE is substantially aligned with first capacitor electricity
Pole C1 and the second capacitance electrode C2.In one embodiment, first code-pattern forms pixel electrode material layer (not on protective layer 130
It is painted).Such as pixel electrode material layer is formed on protective layer 130 using sputtering process or other film deposition techniques.Picture
Plain electrode material layer can be single or multi-layer structure, and material can be transparent conductive material, such as tin indium oxide, hafnium oxide, oxygen
Change aluminium zinc, aluminium oxide tin, gallium oxide zinc, indium oxide titanium, indium oxide molybdenum or other transparent conductive materials.Then, in an embodiment
In, using the 5th light shield, the 6th lithographic and etch process are carried out to pixel electrode material layer, to form pixel electrode PE.One
In embodiment, as shown in fig. 1F, top of the pixel electrode PE in addition to being formed in first capacitor electrode C1 and the second capacitance electrode C2
Except, it is also formed in the second opening O2, and contact the second capacitance electrode C2.In this way, which pixel electrode PE is through the second electricity
Hold electrode C2 and couple drain D, the second capacitance electrode C2 and pixel electrode PE are equipotential.
As shown in fig. 1F, the made dot structure comprising top gate type thin film transistor has a capacitor, by having
The first capacitor electrode C1 of common voltage current potential, gate dielectric layer 120 and with equipotential second capacitance electrode of pixel electrode PE
C2 is constituted.This includes the dot structure of top gate type thin film transistor with enough capacitances.
Fig. 2A-Fig. 2 F is painted method the cuing open in each operation stage of manufacture dot structure according to another embodiment of the present invention
Face schematic diagram.As shown in Figure 2 A, substrate 110 is provided.Then, grid G and the second capacitance electrode C2 are formed on substrate 110.?
In one embodiment, first code-pattern forms conductive layer (not being painted) on substrate 110, reuses the first light shield, carries out to conductive layer
First lithographic and etch process, to form grid G and the second capacitance electrode C2.
As shown in Figure 2 B, gate dielectric layer 120 is formed in the top of grid G and the second capacitance electrode C2.In one embodiment,
Code-pattern forms gate dielectric layer 120 and covers grid G and the second capacitance electrode C2.
As shown in Figure 2 C, semiconductor layer SE is formed in the top of grid G.In one embodiment, in source S, drain D and
First code-pattern forms semiconductor material layer (not being painted) on one capacitance electrode C1, the second light shield is reused, to semiconductor material layer
The second lithographic and etch process are carried out, to form semiconductor layer SE.
As shown in Figure 2 D, source S, drain D are formed on semiconductor layer SE, and form on the second capacitance electrode C2 the
One capacitance electrode C1.Semiconductor layer SE contacts a part of source S and a part of drain D.In one embodiment, in semiconductor
First code-pattern forms conductive layer (not being painted) on layer SE and gate dielectric layer 120, reuses third light shield, carries out third to conductive layer
Lithographic and etch process, to form source S, drain D and first capacitor electrode C1.In one embodiment, source S, leakage are being formed
When pole D and first capacitor electrode C1, be formed simultaneously data line (not being painted) and common electrode wire (not being painted), source S, drain D,
First capacitor electrode C1, data line and common electrode wire belong to same patterned conductive layer.In one embodiment, first capacitor electricity
Pole C1 coupling or connection common electrode wire, so first capacitor electrode C1 can have common voltage current potential.
As shown in Figure 2 E, in grid G, the second capacitance electrode C2, semiconductor layer SE, source S, drain D and first capacitor electricity
The top of pole C1 forms protective layer 130.In one embodiment, grid G, the second capacitance electrode C2, semiconductor layer SE, source S,
First code-pattern forms protective layer 130 on drain D and first capacitor electrode C1.In one embodiment, using the 4th light shield, to protection
Layer 130 carries out the 4th lithographic and etch process, and to form the second opening O2 through protective layer 130, the third through drain D is opened
It mouthful O3 and is open O1 through the first of gate dielectric layer 120.Second opening O2 is substantially aligned with third opening O3, and third is open O3 substantially
The first opening of alignment O1.
As shown in Figure 2 F, pixel electrode PE is formed above protective layer 130, pixel electrode PE is substantially aligned with first capacitor electricity
Pole C1.In one embodiment, first code-pattern forms pixel electrode material layer (not being painted) on protective layer 130, reuses the 5th
Light shield carries out the 5th lithographic and etch process to pixel electrode material layer, to form pixel electrode PE.In one embodiment, such as
Shown in Fig. 2 F, pixel electrode PE is also formed other than being formed in the top of first capacitor electrode C1 and the second capacitance electrode C2
It is open in O2, the third opening of opening O3 and first O1 second, and contacts the second capacitance electrode C2 and drain D, make the second capacitor
Electrode C2 and pixel electrode PE is equipotential.
As shown in Figure 2 F, the made dot structure comprising bottom gate thin film transistor have two capacitors, by with picture
The equipotential second capacitance electrode C2 of plain electrode PE, gate dielectric layer 120, the first capacitor electrode C1 with common voltage current potential,
Protective layer 130 and pixel electrode PE are constituted.This includes the dot structure of bottom gate thin film transistor with enough capacitors
Value.
If the dot structure comprising bottom gate thin film transistor of F according to fig. 2, will design and include with two capacitors
The dot structure of top gate type thin film transistor then needs the second capacitance electrode C2 for making Fig. 1 F to have common voltage current potential, the first electricity
Hold electrode C1 and does not have common voltage current potential.Thus, it is necessary to substantially modify perimeter circuit.Therefore, the present invention provides above-mentioned
The method of manufacture dot structure can manufacture the pixel comprising top gate type thin film transistor in the case where not changing perimeter circuit
Structure (A- Fig. 1 F referring to Fig.1) or dot structure (referring to Fig. 2A-Fig. 2 F) comprising bottom gate thin film transistor, and both pictures
Plain structure all has enough capacitors.In other words, each composition in the embodiment of Figure 1A-Fig. 1 F and the embodiment of Fig. 2A-Fig. 2 F
The layout of element be it is identical, can be used the manufacture of same group of light shield, and the difference of the two is only that be formed and each constitutes the suitable of element
Sequence is different.In this way, develop the circuit cloth of the dot structure comprising one of kenel membrane transistor and its perimeter circuit
After office, just it is not required to expend the electricity of dot structure of the time design comprising another kenel membrane transistor and its perimeter circuit again
Road layout.
The present invention separately provides a kind of dot structure.The section that Fig. 1 F is painted dot structure according to an embodiment of the invention shows
It is intended to.As shown in fig. 1F, dot structure includes: source S, drain D and first capacitor electrode C1, is located on substrate 110, wherein the
One capacitance electrode C1 has common voltage current potential；Semiconductor layer SE contacts a part of source S and a part of drain D；Grid
G and the second capacitance electrode C2, grid G are located in semiconductor layer SE, source S and drain D, and the second capacitance electrode C2 is located at the first electricity
Hold on electrode C1, the second capacitance electrode C2 is substantially aligned with first capacitor electrode C1；Gate dielectric layer 120 is located at semiconductor layer SE, source
Between pole S, drain D and first capacitor electrode C1, with grid G and the second capacitance electrode C2；Protective layer 130 is located at source S, leakage
The top of pole D, first capacitor electrode C1, semiconductor layer SE, grid G and the second capacitance electrode C2；And pixel electrode PE, it is located at
130 top of protective layer.
In embodiment, the second capacitance electrode C2 and pixel electrode PE equipotential.In one embodiment, gate dielectric layer 120 has
There is the first opening O1 through gate dielectric layer 120, the second capacitance electrode C2 is located in the first opening O1.In one embodiment, it protects
There is layer 130 second opening O2 to run through protective layer 130, and the second opening O2, which is located above the first opening O1 and is substantially aligned with first, to be opened
Mouth O1.Pixel electrode PE is located in the second opening O2, and contacts the second capacitance electrode C2.In one embodiment, drain D has the
Three opening O3 run through drain D, and third opening O3 is located at below the first opening O1 and is substantially aligned with the first opening O1.Second capacitor electricity
Pole C2 is located in third opening O3.Pixel electrode PE is connect through the second capacitance electrode C2 with drain D.
Fig. 2 F is painted the diagrammatic cross-section of dot structure according to another embodiment of the present invention.As shown in Figure 2 F, pixel knot
Structure includes: grid G and the second capacitance electrode C2, is located on substrate 110；Gate dielectric layer 120 is located at grid G and the second capacitor electricity
On the C2 of pole；Semiconductor layer SE is located above gate dielectric layer 120 and grid G；Source S, drain D and first capacitor electrode C1, source electrode
S and drain D are located in grid G, and semiconductor layer SE contacts a part of source S and a part of drain D, first capacitor electrode C1
On the second capacitance electrode C2, first capacitor electrode C1 is substantially aligned with the second capacitance electrode C2, and first capacitor electrode C1 has
Common voltage current potential；Protective layer 130 is located at source S, drain D, first capacitor electrode C1, semiconductor layer SE, grid G and second
The top of capacitance electrode C2；And pixel electrode PE, it is located at 130 top of protective layer.
In one embodiment, the second capacitance electrode C2 and pixel electrode PE equipotential.In one embodiment, protective layer 130
Run through protective layer 130 with the second opening O2, pixel electrode PE is located in the second opening O2, and contacts the second capacitance electrode C2.
In one embodiment, drain D have third opening O3 run through drain D, third be open O3 be located at second opening O2 below and substantially
The second opening of alignment O2.Pixel electrode PE is located in the second opening O2 and third opening O3.In one embodiment, gate dielectric layer
120 there is the first opening O1 to run through gate dielectric layer 120, and the first opening O1, which is located at below third opening O3 and is substantially aligned with third, to be opened
Mouth O3.Pixel electrode PE is located in the first opening O1.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any this field skill
Art personnel, without departing from the spirit and scope of the present invention, when various variations and retouching, therefore protection scope of the present invention can be made
Subject to view as defined in claim.
Claims (8)
1. a kind of method for manufacturing dot structure, which is characterized in that the method for the manufacture dot structure includes:
Form source electrode, drain electrode and first capacitor electrode；
It forms semiconductor layer and contacts a part of the source electrode and a part of the drain electrode；
It forms grid and the second capacitance electrode, second capacitance electrode is substantially aligned with the first capacitor electrode；
It is formed and is located at the semiconductor layer, the source electrode, the drain electrode and the first capacitor electrode, with the grid and described
Gate dielectric layer between second capacitance electrode；
It forms the first opening and runs through the gate dielectric layer, and second capacitance electrode is formed in first opening；
In the source electrode, the drain electrode, the first capacitor electrode, the semiconductor layer, the grid and second capacitor
The top of electrode forms protective layer；And
Pixel electrode is formed above the protective layer, the pixel electrode is substantially aligned with the first capacitor electrode,
Wherein formed be located at the semiconductor layer, the source electrode, it is described drain electrode and the first capacitor electrode, with the grid and
The gate dielectric layer step between second capacitance electrode is forming the source electrode, the drain electrode and first capacitor electricity
It is carried out after the step of pole.
2. the method for manufacture dot structure as described in claim 1, which is characterized in that second capacitance electrode and the picture
Plain electrode equipotential.
3. the method for manufacture dot structure as described in claim 1, which is characterized in that the method for the manufacture dot structure is also
Run through the protective layer comprising forming the second opening, second opening is substantially aligned with first opening, and forms the picture
Plain electrode step includes to form the pixel electrode in second opening, and contact second capacitance electrode.
4. the method for manufacture dot structure as described in claim 1, which is characterized in that the method for the manufacture dot structure is also
Comprising forming third opening through the drain electrode and being substantially aligned with first opening, and form the grid and second electricity
Holding electrode step includes to form second capacitance electrode in third opening.
5. a kind of dot structure, which is characterized in that a kind of dot structure includes:
Source electrode, drain electrode and first capacitor electrode, wherein the first capacitor electrode has common voltage current potential；
Semiconductor layer contacts a part of the source electrode and a part of the drain electrode；
Grid and the second capacitance electrode, the grid are located in the semiconductor layer, the source electrode and the drain electrode, and described second
Capacitance electrode is located on the first capacitor electrode, and second capacitance electrode is substantially aligned with the first capacitor electrode；
Gate dielectric layer is located at the semiconductor layer, the source electrode, the drain electrode and the first capacitor electrode, with the grid
Between pole and second capacitance electrode, wherein the gate dielectric layer has the first opening and second capacitance electrode is located at institute
It states in the first opening；
Protective layer is located at the source electrode, the drain electrode, the first capacitor electrode, the semiconductor layer, the grid and institute
The top of the second capacitance electrode is stated, wherein the protective layer has the second opening；And
Pixel electrode is located above the protective layer,
Wherein the pixel electrode is located in first opening, and contacts second capacitance electrode, or
The pixel electrode is located in second opening, and contacts second capacitance electrode.
6. dot structure as claimed in claim 5, which is characterized in that second capacitance electrode and the pixel electrode etc. are electric
Position.
7. dot structure as claimed in claim 5, which is characterized in that second opening is located at first overthe openings simultaneously
It is substantially aligned with first opening.
8. dot structure as claimed in claim 5, which is characterized in that there is third opening to open positioned at described first for the drain electrode
Below mouthful and it is substantially aligned with first opening, second capacitance electrode is located in third opening.
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| CN201510448218.8A CN106409846B (en) | 2015-07-28 | 2015-07-28 | Manufacture the method and dot structure of dot structure |
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| CN109411335B (en) * | 2018-08-13 | 2021-01-19 | 上海奕瑞光电子科技股份有限公司 | Pixel structure and manufacturing method thereof |
| CN113345322A (en) * | 2020-03-02 | 2021-09-03 | 元太科技工业股份有限公司 | Wiring structure of display panel |
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| JP5604087B2 (en) * | 2009-11-27 | 2014-10-08 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| TWI535034B (en) * | 2014-01-29 | 2016-05-21 | 友達光電股份有限公司 | Pixel structure and method of fabricating the same |
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