CN109390386B - 后栅极硅锗沟道凝结及其制造方法 - Google Patents

后栅极硅锗沟道凝结及其制造方法 Download PDF

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CN109390386B
CN109390386B CN201810861103.5A CN201810861103A CN109390386B CN 109390386 B CN109390386 B CN 109390386B CN 201810861103 A CN201810861103 A CN 201810861103A CN 109390386 B CN109390386 B CN 109390386B
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silicon
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CN109390386A (zh
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乔治·罗伯特·姆芬格
莱恩·史波尔
T·J·麦卡德尔
朱德尚·罗伯特·侯尔特
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GlobalFoundries US Inc
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Abstract

本发明涉及后栅极硅锗沟道凝结及其制造方法，其提供通过后栅极热凝结及氧化高锗百分比沟道层而在FinFET或FDSOI装置中形成分级硅锗百分比PFET沟道的方法及所产生的装置。数个具体实施例包括：形成栅极介电层于形成在衬底上方的多个硅鳍片上方；在各鳍片上方形成栅极；形成HM及间隔体层于各栅极的侧壁上方及各栅极的侧壁上；在各鳍片中形成邻近该栅极及间隔体层的u形空腔；在各u形空腔中且沿着各鳍片的数个侧壁外延成长无掺杂高百分比硅锗层；热凝结该高百分比硅锗层，以在该衬底及数个鳍片底下形成无掺杂低百分比硅锗；以及形成一S/D区于在各u形空腔中的该高百分比硅锗层上方，该S/D区的上表面低于该栅极介电层。

Description

后栅极硅锗沟道凝结及其制造方法
技术领域
本揭示内容是有关于硅锗(SiGe)鳍片场效晶体管(FinFET)半导体装置的制造。特别是，本揭示内容可应用于14纳米(nm)及更先进的技术节点。
背景技术
硅锗提供高于硅(Si)的载子移动率。FinFET的硅锗鳍片降低阈值电压(Vt)，由此增加流动通过沟道的驱动电流。不过，用硅锗鳍片改善有效沟道长度(Leff)效能难以实现，因为(i)硅锗鳍片源于沟道接面(TJ)蚀刻的松弛；(ii)栅极氧化物导致鳍片粗糙度劣化的接口问题；(iii)p型场效晶体管(PFET)栅极诱发的漏极漏电流(GIDL)；(iv)接口缺陷密度(DIT)；以及(v)与制作硅锗鳍片的整合工艺相关的n型场效晶体管(NFET)问题，例如，氮化物衬里造成NFET泄漏。此外，因为高静态随机存取内存(SRAM)泄漏与硅锗鳍片整合限制(例如，低温STI加工及晶体缺陷)，使得良率难以用硅锗鳍片证明。
因此，亟须一种能形成硅锗PFET沟道而没有习知复杂的加工或难题的方法。
发明内容
本揭示内容的一方面为一种通过后栅极热凝结及氧化高锗(Ge)百分比沟道层而在FinFET或全空乏型绝缘体上覆硅(FDSOI)装置中形成分级(graded)硅锗百分比PFET沟道的方法。
本揭示内容的另一方面为一种具有分级硅锗百分比PFET沟道的FinFET或FDSOI装置。
本揭示内容的其他方面及特征会在以下说明中提出以及部分在本领域一般技术人员审查以下内容或学习本揭示内容的实施后会明白。按照随附权利要求中特别提出者，可实现及得到本揭示内容的优点。
根据本揭示内容，某些技术效果部分可用一种方法达成，包括：形成多个硅鳍片于硅衬底上方；形成栅极介电层于该多个硅鳍片上方；形成栅极于该多个硅鳍片中的每一者上方；形成硬掩模(HM)及间隔体层于各栅极的数个侧壁上方及各栅极的数个侧壁上；在该多个硅鳍片中形成邻近该栅极及间隔体层的u形空腔；在各u形空腔中且沿着各硅鳍片的数个侧壁外延成长无掺杂高百分比硅锗层；热凝结该无掺杂高百分比硅锗层，以在该衬底及数个硅鳍片底下形成无掺杂低百分比硅锗；以及形成源极/漏极(S/D)区于在各u形空腔中的该无掺杂高百分比硅锗层上方，该S/D区的上表面低于该栅极介电层。
本揭示内容的数个方面包括含有20至50百分比的锗的该无掺杂高百分比硅锗层。其他数个方面包括含有5至20百分比的锗的该无掺杂低百分比硅锗层。另一方面包括：移除通过该无掺杂高百分比硅锗层的热凝结而形成的氧化物层。附加的数个方面包括：形成掺硼硅锗的S/D区。
本揭示内容的另一方面为一种装置，包括：多个无掺杂低百分比硅锗鳍片，在硅衬底上方具有u形无掺杂低百分比硅锗层在其间；无掺杂高百分比硅锗层，在该u形无掺杂低百分比硅锗层上方且沿着该无掺杂低百分比硅锗鳍片的数个侧壁；S/D区，在该无掺杂高百分比硅锗层上方，该S/D区的上表面与该无掺杂低百分比硅锗鳍片的上表面共面；栅极介电层，在各个无掺杂低百分比硅锗鳍片上方；栅极，在该栅极介电层上方；以及HM及间隔体层，在各栅极的相对侧壁上方及各栅极的相对侧壁上。
该装置的数个方面包括含有5至20百分比的锗的该无掺杂低百分比硅锗鳍片。另一方面包括完全延伸越过短沟道装置的沟道区与在长沟道装置的沟道区下部分延伸的该无掺杂低百分比硅锗层。其他数个方面包括含有20至50百分比的锗的该无掺杂高百分比硅锗层。又一方面包括厚度有4.5纳米至20纳米的该无掺杂高百分比硅锗层。
本揭示内容的又一方面为一种方法，包括：提供埋藏氧化物(BOX)层于具有NFET区及PFET区的硅衬底上方；提供SOI硅层(Si SOI layer)于该BOX层上方；形成浅沟槽隔离(STI)柱体，其在该NFET区与该PFET区之间穿过该SOI硅层及该BOX层和该衬底的一部分；形成栅极堆栈及第一HM于该NFET区与该PFET区中的每一者上面；在位于该NFET区上方的该SOI硅层上方以及沿着在该PFET区上方的该栅极堆栈及该第一HM的数个侧壁，形成第二HM；外延成长无掺杂高百分比硅锗层于在该PFET区上方的该SOI硅层上方；热凝结该无掺杂高百分比硅锗层，以将在该PFET区上方的该SOI硅层转换为无掺杂高百分比硅锗层与形成于该第二HM及该栅极堆栈的一部分底下的无掺杂低百分比硅锗；以及成长掺硼(B)硅锗S/D区于在该PFET区上方的该无掺杂高百分比硅锗层上方。
本揭示内容的数个方面包括：用以下步骤转换在该PFET区上方的该SOI硅层：将锗推进该SOI硅层；以及移除通过该无掺杂高百分比硅锗层的该热凝结而形成的氧化物层。其他数个方面包括：形成厚度有5纳米至10纳米的该SOI硅层。另一方面包括：用以下步骤形成各栅极堆栈：在该NFET区及该PFET区上方的该SOI硅层上方形成氧化铪(HfO2)介电层；形成氮化钛(TiN)功函数(WF)金属层于该HfO2介电层上方；以及形成多晶硅层于该TiN WF金属层上方。附加的数个方面包括：用以下步骤形成该HM：形成该HM于该衬底上方；以及移除在该SOI硅层上方的该HM与在该PFET区上方的该第一HM，留下沿着该第一HM与栅极堆栈的该侧壁的该HM。其他数个方面包括：该无掺杂高百分比硅锗层包括20至50百分比的锗。附加的数个方面包括：该无掺杂低百分比硅锗层包括5至20百分比的锗。
本揭示内容的又一方面为一种装置，包括：BOX层，在具有NFET区及PFET区的硅衬底上方；SOI硅层，在位于该NFET区上方的该BOX层上方；STI柱体，其在该NFET与该PFET区之间穿过该SOI硅层及该BOX层和该硅衬底的一部分；无掺杂高百分比硅锗层及无掺杂低百分比硅锗层，在位于该PFET区上方的该BOX层的数个部分上方；栅极堆栈，在该NFET区与该PFET区中的每一者上方；以及掺硼硅锗S/D，在该栅极堆栈相对两侧上、位于该无掺杂高百分比硅锗层上方。
本揭示内容的数个方面包括在该NFET区上方的该SOI硅层与在该PFET区上方的该无掺杂高百分比硅锗层有5纳米至10纳米的厚度。另一方面包括该无掺杂高百分比硅锗层与该无掺杂低百分比硅锗层分别包括20至50百分比的锗与5至20百分比的锗。
本领域技术人员由以下详细说明可明白本揭示内容的其他方面及技术效果，其中仅以预期可实现本揭示内容的最佳模式举例描述本揭示内容的具体实施例。应了解，本揭示内容能够做出其他及不同的具体实施例，以及在各种明显的方面，能够修改数个细节而不脱离本揭示内容。因此，附图及说明内容本质上应被视为图解说明用而不是用来限定。
附图说明
在此用附图举例说明而不是限定本揭示内容，图中类似的组件用相同的附图标记表示。
图1至图5的横截面图根据一示范具体实施例示意图示用于形成有分级硅锗百分比PFET沟道的FinFET装置的工艺流程；以及
图6至图8的横截面图根据一示范具体实施例示意图示用于形成有分级硅锗百分比PFET沟道的FDSOI装置的工艺流程。
具体实施方式
为了解释，在以下的说明中，提出许多特定细节供彻底了解示范具体实施例。不过，显然没有该特定细节或用等价配置仍可实施示范具体实施例。在其他情况下，众所周知的结构及装置用方块图图标以免不必要地混淆示范具体实施例。此外，除非另有说明，在本专利说明书及权利要求中表示成分、反应状态等等的数量、比例及数值性质的所有数字应被理解为在所有情况下可用措辞“约”来修饰。
本揭示内容针对及解决在后栅极(post gate)硅锗沟道凝结后随之而来的硅锗鳍片Leff效能及良率的当前问题。尤其是，解决该问题通过高锗百分比沟道层之后栅极热凝结及氧化以在FinFET或FDSOI装置中形成分级(graded)硅锗百分比PFET沟道以防止硅锗堆积缺陷(stacking fault)，致能标准高温STI工艺与标准鳍片显露(fin reveal)工艺，且避免形成晶体缺陷，这通常与早期硅锗鳍片形成技术有关。
根据本揭示内容具体实施例的方法包括：形成多个硅鳍片于硅衬底上方。形成栅极介电层于该多个硅鳍片上方。形成栅极于该多个硅鳍片中的每一者上方。形成一HM及间隔体层于各栅极的数个侧壁上方及各栅极的数个侧壁上。在该多个硅鳍片中形成邻近该栅极及间隔体层的一u形空腔。一无掺杂高百分比硅锗层在各u形空腔中沿着各硅鳍片的数个侧壁外延成长。热凝结该无掺杂高百分比硅锗层，这在该衬底及数个硅鳍片底下形成一无掺杂低百分比硅锗，以及形成一S/D区于在各u形空腔中的该无掺杂高百分比硅锗层上方，该S/D区的一上表面低于该栅极介电层。
又在其他方面，本领域技术人员从以下说明可轻易明白特征及技术效果，其中仅通过图解说明考虑的最佳模式来图标及描述较佳具体实施例。本揭示内容能为其他及不同的具体实施例，以及它的数个细节在各种明显方面能够修改。因此，附图及说明应被视为本质上是图解说明用，而非限制。
图1至图5的横截面图根据一示范具体实施例示意图示用于形成具有分级硅锗百分比PFET沟道的FinFET装置的工艺流程。参照图1，在硅衬底103的PFET区上方形成数个硅鳍片101，例如，有100纳米至200纳米的高度，其中有30纳米至50纳米的主动部分，以及宽度有5纳米至12纳米。然后，形成例如厚度有10埃至30埃的栅极介电层105于硅鳍片101上方。在后续加工期间，栅极介电层105可由例如二氧化硅(SiO2)形成，且二氧化硅可换成高k栅极介电质，例如，HfO2(为了便于图解说明而未图示)。接下来，形成例如由多晶硅制成的栅极107于栅极介电层105上方。在取代金属栅极(RMG)加工期间，该多晶硅随后可换成包括TiN及钨(W)的金属堆栈(为了便于图解说明而未图示)。随后，在各栅极107的侧壁上方及侧壁上形成由例如SiN构成的HM及间隔体层，而形成低K间隔体109a与HM 109b。低K间隔体109a及HM 109b防止栅极107上的外延成长，且该低k材料保护互补装置(亦即，NFET)免于外延成长。然后，例如用干蚀刻法蚀刻硅鳍片101与硅衬底103以形成邻近栅极107及低K间隔体109a、有例如40纳米至50纳米的深度的u形空腔113。
接下来，在硅鳍片101的侧壁上与在u形空腔113上方外延成长例如有20至100百分比的锗(例如，20至50百分比)的高百分比无掺杂硅锗层201，如图2所示。参照图3，硅锗层201热凝结而在硅锗层201上方形成例如厚度有10纳米至25纳米的氧化物层301，并且将锗推进到在各栅极107及介电层105下的沟道区303。结果，在无掺杂高百分比硅锗层201、栅极介电层105及衬底103之间形成例如有5至20百分比的锗的无掺杂低百分比硅锗层305，而形成硅锗鳍片307与分级硅锗百分比PFET沟道303(硅锗层201及305)。无掺杂低百分比硅锗层305可在短沟道装置的例如有14纳米至20纳米的沟道区下面完全延伸，以及在长沟道装置的例如有30纳米或更多的沟道区下面部分延伸。
参照图4，移除氧化物层301从而减薄硅锗层201，例如，减薄到4.5纳米至20纳米的厚度，形成硅锗层201’。接下来，在各u形空腔113中，形成在无掺杂高百分比硅锗层201’上方且沿着硅锗鳍片307的侧壁向上达到栅极介电层105的例如掺硼硅锗的S/D区501，如图5所示。结果，热氧化导致在硅锗层305中的锗百分比较低，且在硅锗层305与随后形成的S/D区的界面处的锗百分比较高。
图6至图8的横截面图根据一示范具体实施例示意图示用于形成具有分级硅锗百分比PFET沟道的FDSOI装置的工艺流程。参照图6，形成有NFET区603及PFET区605的硅衬底601。形成BOX层607，例如，厚度有10纳米至25纳米，于硅衬底601上方。然后，形成SOI硅层609，例如，厚度有5纳米至10纳米，于BOX层607上方。接下来，在NFET区与PFET区603及605之间，形成分别穿过SOI硅层609及BOX层607、和硅衬底601的一部分的STI柱体611，例如，深度有10纳米至150纳米。随后，例如，通过栅极图案化，形成栅极堆栈613及615于在NFET区603及PFET区605上方的SOI硅层609的数个部分上方。栅极堆栈613包括在SOI硅层609的数个部分上方形成例如厚度约有15埃的HfO2介电层(为了便于图解说明而未图示)；在HfO2介电层上方形成例如厚度约有10纳米的TiN WF金属层(为了便于图解说明而未图示)；以及在TiNWF金属层上方形成例如厚度有20纳米至50纳米的多晶硅层(为了便于图解说明而未图示)。
接下来，于各栅极堆栈613上方形成例如由氮化硅(SiN)构成的HM层617，且厚度有10纳米至30纳米。之后，以共形(conformally)的方式于衬底601上方形成例如由氮化物构成的HM层，且厚度有3纳米至15纳米，然后回蚀，在NFET区603及STI柱体611的一部分上方以及沿着在PFET区605上方的栅极堆栈615及HM层617的侧壁，形成HM层619。
参照图7，在位于PFET区605上方的SOI硅层609上方，外延成长无掺杂高百分比硅锗层(为了便于图解说明而未图示)，例如，到20纳米至30纳米的厚度。类似以上在说明图3时所述的工艺步骤，该无掺杂高百分比硅锗受到热凝结而产生氧化物层(为了便于图解说明而未图示)，且锗被推进SOI硅层609及在栅极堆栈615下的沟道区，而形成SOI硅层609’，无掺杂高百分比硅锗层701，例如，有20至50百分比的锗，以及无掺杂低百分比硅锗层703，例如，有5至20百分比的锗(亦即，形成分级硅锗百分比PFET沟道)。接下来，移除该氧化物层。
如图8所示，外延成长无缺陷掺硼S/D区801于SOI硅层609’上方。结果，类似图5，在栅极堆栈615下的沟道区有较低百分比的锗且沟道区与S/D区801的界面处有高百分比的锗，亦即，在沟道/S/D界面处形成有较高锗百分比的超陡峭接面(ultra-steep junction)。
本揭示内容的具体实施例可实现数种技术效果，包括避免习知的硅锗鳍片整合限制(低温STI及晶体缺陷，源于高锗百分比的较陡峭接面，以及预期源于热凝结锗的高应力。此外，关于FDSOI装置，技术效果包括致能更好地避免超薄SOI沟道的结块缺陷(agglomerationdefect)，致能超陡峭接面，以及致能具有紧密NFET/PFET空间的SRAM装置的阈值电压偏移(Vt shift)。根据本揭示内容的具体实施例形成的装置在产业上可用于各种工业应用，例如，微处理器、智能型手机、移动电话、手机、机顶盒、DVD刻录机及播放器、汽车导航、打印机及接口设备，网络及电信设备，游戏系统及数字相机。本揭示内容因此在产业上可应用于各种FinFET或FDSOI装置，特别是应用于例如14纳米及更先进的技术节点。
在以上说明中，特别用数个示范具体实施例描述本揭示内容。不过，显然仍可做出各种修改及改变而不脱离本揭示内容更宽广的精神及范畴，如权利要求所述。因此，本专利说明书及附图应被视为图解说明用而非限定。应了解，本揭示内容能够使用各种其他组合及具体实施例以及在如本文所述的本发明概念范畴内能够做出任何改变或修改。

Claims (20)

1.一种制造半导体装置的方法，该方法包含：
形成多个硅鳍片于硅衬底上方；
形成栅极介电层于该多个硅鳍片上方；
形成栅极于该多个硅鳍片中的每一者上方；
形成硬掩模及间隔体层于各栅极的数个侧壁上方及各栅极的数个侧壁上；
在该多个硅鳍片中形成邻近该栅极及间隔体层的一u形空腔；
在各u形空腔中且沿着各硅鳍片的数个侧壁外延成长无掺杂高百分比硅锗层；
热凝结该无掺杂高百分比硅锗层，以在该衬底及数个硅鳍片底下形成无掺杂低百分比硅锗层；以及
形成源极/漏极区于在各u形空腔中的该无掺杂高百分比硅锗层上方，该源极/漏极区的上表面低于该栅极介电层。
2.如权利要求1所述的方法，其中，该无掺杂高百分比硅锗层包含20至50百分比的锗。
3.如权利要求1所述的方法，其中，该无掺杂低百分比硅锗层包含5至20百分比的锗。
4.如权利要求1所述的方法，进一步包含：移除通过该无掺杂高百分比硅锗层的该热凝结而形成的氧化物层。
5.如权利要求1所述的方法，包含：形成有掺硼硅锗的该源极/漏极区。
6.一种半导体装置，包含：
多个无掺杂低百分比硅锗鳍片，在硅衬底上方，具有u形无掺杂低百分比硅锗层在其间；
无掺杂高百分比硅锗层，在该u形无掺杂低百分比硅锗层上方且沿着该无掺杂低百分比硅锗鳍片的数个侧壁；
源极/漏极区，在该无掺杂高百分比硅锗层上方，该源极/漏极区的上表面与该无掺杂低百分比硅锗鳍片的上表面共面；
栅极介电层，在各个无掺杂低百分比硅锗鳍片上方；
栅极，在该栅极介电层上方；以及
硬掩模及间隔体层，在各栅极的相对侧壁上方及各栅极的相对侧壁上。
7.如权利要求6所述的半导体装置，其中，该无掺杂低百分比硅锗鳍片包含5至20百分比的锗。
8.如权利要求6所述的半导体装置，其中，该无掺杂低百分比硅锗层完全延伸越过短沟道装置的沟道区且在长沟道装置的沟道区下部分延伸。
9.如权利要求6所述的半导体装置，其中，该无掺杂高百分比硅锗层包含20至50百分比的锗。
10.如权利要求6所述的半导体装置，其中，该无掺杂高百分比硅锗层有4.5纳米至20纳米的厚度。
11.一种制造半导体装置的方法，该方法包含：
提供埋藏氧化物层于具有n型场效晶体管区及p型场效晶体管区的硅衬底上方；
提供绝缘体上覆硅硅层于该埋藏氧化物层上方；
形成浅沟槽隔离柱体，其在该n型场效晶体管区与该p型场效晶体管区之间穿过该绝缘体上覆硅硅层及该埋藏氧化物层和该衬底的一部分；
形成栅极堆栈及第一硬掩模于该n型场效晶体管区与该p型场效晶体管区中的每一者上方；
在位于该n型场效晶体管区上方的该绝缘体上覆硅硅层上方以及沿着在该p型场效晶体管区上方的该栅极堆栈及该第一硬掩模的数个侧壁，形成第二硬掩模；
外延成长无掺杂高百分比硅锗层于在该p型场效晶体管区上方的该绝缘体上覆硅硅层上方；
热凝结该无掺杂高百分比硅锗层，以将在该p型场效晶体管区上方的该绝缘体上覆硅硅层转换为无掺杂高百分比硅锗层与形成于该第二硬掩模及该栅极堆栈的一部分底下的无掺杂低百分比硅锗层；以及
成长掺硼硅锗源极/漏极区于在该p型场效晶体管区上方的该无掺杂高百分比硅锗层上方。
12.如权利要求11所述的方法，包含用以下步骤转换在该p型场效晶体管区上方的该绝缘体上覆硅硅层：
将锗推进该绝缘体上覆硅硅层；以及
移除通过该无掺杂高百分比硅锗层的该热凝结而形成的氧化物层。
13.如权利要求11所述的方法，包含：形成厚度有5纳米至10纳米的该绝缘体上覆硅硅层。
14.如权利要求11所述的方法，包含用下列步骤形成各栅极堆栈：
形成氧化铪介电层于在该n型场效晶体管区与该p型场效晶体管区上方的该绝缘体上覆硅硅层上方；
形成氮化钛功函数金属层于该氧化铪介电层上方；以及
形成多晶硅层于该氮化钛功函数金属层上方。
15.如权利要求11所述的方法，包含用下列步骤形成该硬掩模：
形成该硬掩模于该衬底上方；以及
移除在该绝缘体上覆硅硅层上方的该硬掩模与在该p型场效晶体管区上方的该第一硬掩模，留下沿着该第一硬掩模与栅极堆栈的该侧壁的该硬掩模。
16.如权利要求11所述的方法，其中，该无掺杂高百分比硅锗层包含20至50百分比的锗。
17.如权利要求11所述的方法，其中，该无掺杂低百分比硅锗层包含5至20百分比的锗。
18.一种半导体装置，包含：
埋藏氧化物层，在具有n型场效晶体管区及p型场效晶体管区的硅衬底上方；
绝缘体上覆硅硅层，在位于该n型场效晶体管区上方的该埋藏氧化物层上方；
浅沟槽隔离柱体，在该n型场效晶体管区与p型场效晶体管区之间穿过该绝缘体上覆硅硅层及该埋藏氧化物层和该硅衬底的一部分；
无掺杂高百分比硅锗层及无掺杂低百分比硅锗层，在位于该p型场效晶体管区上方的该埋藏氧化物层的数个部分上方；
栅极堆栈，在该n型场效晶体管区与该p型场效晶体管区中的每一者上方；以及
掺硼硅锗源极/漏极，在该栅极堆栈的相对两侧上、位于该无掺杂高百分比硅锗层上方；
其中，该无掺杂高百分比硅锗层及该无掺杂低百分比硅锗层中的锗百分比沿着该埋藏氧化物层的表面分级。
19.如权利要求18所述的半导体装置，其中，在该n型场效晶体管区上方的该绝缘体上覆硅硅层与在该p型场效晶体管区上方的该无掺杂高百分比硅锗层有5纳米至10纳米的厚度。
20.如权利要求18所述的半导体装置，其中，该无掺杂高百分比硅锗层与该无掺杂低百分比硅锗层分别包含20至50百分比的锗与5至20百分比的锗。
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