TWI652725B - 後閘極矽鍺通道凝結及其製造方法 - Google Patents

後閘極矽鍺通道凝結及其製造方法 Download PDF

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TWI652725B
TWI652725B TW106130146A TW106130146A TWI652725B TW I652725 B TWI652725 B TW I652725B TW 106130146 A TW106130146 A TW 106130146A TW 106130146 A TW106130146 A TW 106130146A TW I652725 B TWI652725 B TW I652725B
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喬治 羅伯特 姆芬格
萊恩 史波爾
提莫西Ｊ 麥卡多
朱德尚 羅伯特 侯爾特
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格芯（美國）集成電路科技有限公司
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Abstract

提供藉由後閘極熱凝結及氧化高鍺百分比通道層而在FinFET或FDSOI裝置中形成分級矽鍺百分比PFET通道的方法及所產生的裝置。數個具體實施例包括：形成閘極介電層於形成在基板上方的複數個矽鰭片上方；在各鰭片上方形成閘極；形成硬遮罩及間隔體層於各閘極的側壁上方及各閘極的側壁上；在各鰭片中形成鄰近該閘極及間隔體層的u形空腔；在各u形空腔中且沿著各鰭片之數個側壁磊晶成長無摻雜高百分比矽鍺層；熱凝結該高百分比矽鍺層，以在該基板及數個鰭片底下形成無摻雜低百分比矽鍺；以及形成一S/D區於在各u形空腔中的該高百分比矽鍺層上方，該S/D區的上表面低於該閘極介電層。

Description

後閘極矽鍺通道凝結及其製造方法
本揭示內容係有關於矽鍺(SiGe)鰭片場效電晶體(FinFET)半導體裝置的製造。特別是，本揭示內容可應用於14奈米(nm)及更先進的技術節點。
矽鍺提供高於矽(Si)的載子移動率。FinFET的矽鍺鰭片降低閾值電壓(Vt)，藉此增加流動通過通道的驅動電流。不過，用矽鍺鰭片改善有效通道長度(Leff)效能難以實現，因為(i)矽鍺鰭片源於通道接面(TJ)蝕刻的鬆弛；(ii)閘極氧化物導致鰭片粗糙度劣化的介面問題；(iii)p型場效電晶體(PFET)閘極誘發之汲極漏電流(GIDL)；(iv)介面缺陷密度(DIT)；以及(v)與製作矽鍺鰭片之整合製程相關的n型場效電晶體(NFET)問題，例如，氮化物襯裡造成NFET洩漏。此外，因為高靜態隨機存取記憶體(SRAM)洩漏與矽鍺鰭片整合限制(例如，低溫STI加工及晶體缺陷)，使得良率難以用矽鍺鰭片證明。
因此，亟須一種能形成矽鍺PFET通道而沒 有習知複雜的加工或難題的方法。
本揭示內容的一方面為一種藉由後閘極熱凝結及氧化高鍺(Ge)百分比通道層而在FinFET或全空乏型絕緣體上覆矽(FDSOI)裝置中形成分級(graded)矽鍺百分比PFET通道的方法。
本揭示內容的另一方面為一種具有分級矽鍺百分比PFET通道的FinFET或FDSOI裝置。
本揭示內容的其他方面及特徵會在以下說明中提出以及部份在本技藝一般技術人員審查以下內容或學習本揭示內容的實施後會明白。按照隨附申請專利範圍中特別提出者，可實現及得到本揭示內容的優點。
根據本揭示內容，某些技術效果部份可用一種方法達成，包括：形成複數個矽鰭片於矽基板上方；形成閘極介電層於該等複數個矽鰭片上方；形成閘極於該等複數個矽鰭片中之每一者上方；形成硬遮罩(HM)及間隔體層於各閘極的數個側壁上方及各閘極的數個側壁上；在該等複數個矽鰭片中形成鄰近該閘極及間隔體層的u形空腔；在各u形空腔中且沿著各矽鰭片之數個側壁磊晶成長無摻雜高百分比矽鍺層；熱凝結該無摻雜高百分比矽鍺層，以在該基板及數個矽鰭片底下形成無摻雜低百分比矽鍺；以及形成源極/汲極(S/D)區於在各u形空腔中的該無摻雜高百分比矽鍺層上方，該S/D區的上表面低於該閘極介電層。
本揭示內容的數個方面包括含有20至50百分比之鍺的該無摻雜高百分比矽鍺層。其他數個方面包括含有5至20百分比之鍺的該無摻雜低百分比矽鍺層。另一方面包括：移除藉由該無摻雜高百分比矽鍺層之熱凝結而形成的氧化物層。附加的數個方面包括：形成摻硼矽鍺的S/D區。
本揭示內容的另一方面為一種裝置，包括：複數個無摻雜低百分比矽鍺鰭片，在矽基板上方具有u形無摻雜低百分比矽鍺層在其間；無摻雜高百分比矽鍺層，在該u形無摻雜低百分比矽鍺層上方且沿著該等無摻雜低百分比矽鍺鰭片之數個側壁；S/D區，在該無摻雜高百分比矽鍺層上方，該S/D區的上表面與該等無摻雜低百分比矽鍺鰭片的上表面共面；閘極介電層，在各個無摻雜低百分比矽鍺鰭片上方；閘極，在該閘極介電層上方；以及硬遮罩及間隔體層，在各閘極之相對側壁上方及各閘極之相對側壁上。
該裝置的數個方面包括含有5至20百分比之鍺的該等無摻雜低百分比矽鍺鰭片。另一方面包括完全延伸越過短通道裝置之通道區與在長通道裝置之通道區下部份延伸的該無摻雜低百分比矽鍺層。其他數個方面包括含有20至50百分比之鍺的該無摻雜高百分比矽鍺層。又一方面包括厚度有4.5奈米至20奈米的該無摻雜高百分比矽鍺層。
本揭示內容的又一方面為一種方法，包 括：提供埋藏氧化物(BOX)層於具有NFET區及PFET區的矽基板上方：提供SOI矽層(Si SOI layer)於該BOX層上方；形成淺溝槽隔離(STI)柱體，其在該NFET區與該PFET區之間穿過該SOI矽層及該BOX層和該基板的一部份；形成閘極堆疊及第一硬遮罩於該NFET區與該PFET區中之每一者上面；在位於該NFET區上方的該SOI矽層上方以及沿著在該PFET區上方之該閘極堆疊及該第一硬遮罩的數個側壁，形成第二硬遮罩；磊晶成長無摻雜高百分比矽鍺層於在該PFET區上方的該SOI矽層上方；熱凝結該無摻雜高百分比矽鍺層，以將在該PFET區上方的該SOI矽層轉換為無摻雜高百分比矽鍺層與形成於該第二硬遮罩及該閘極堆疊之一部份底下的無摻雜低百分比矽鍺；以及成長摻硼(B)矽鍺S/D區於在該PFET區上方的該無摻雜高百分比矽鍺層上方。
本揭示內容的數個方面包括：用以下步驟轉換在該PFET區上方的該SOI矽層：將鍺推進該SOI矽層；以及移除藉由該無摻雜高百分比矽鍺層之該熱凝結而形成的氧化物層。其他數個方面包括：形成厚度有5奈米至10奈米的該SOI矽層。另一方面包括：用以下步驟形成各閘極堆疊：在該NFET區及該PFET區上方的該SOI矽層上方形成氧化鉿(HfO2)介電層；形成氮化鈦(TiN)功函數(WF)金屬層於該HfO2介電層上方；以及形成多晶矽層於該TiN WF金屬層上方。附加的數個方面包括：用以下步驟形成該硬遮罩：形成該硬遮罩於該基板上方；以及移 除在該SOI矽層上方的該硬遮罩與在該PFET區上方的該第一硬遮罩，留下沿著該第一硬遮罩及閘極堆疊之該等側壁的該硬遮罩。其他數個方面包括：該無摻雜高百分比矽鍺層包括20至50百分比之鍺。附加的數個方面包括：該無摻雜低百分比矽鍺層包括5至20百分比之鍺。
本揭示內容的又一方面為一種裝置，包括：BOX層，在具有NFET區及PFET區之矽基板上方；SOI矽層，在位於該NFET區上方之該BOX層上方；STI柱體，其在該NFET與該PFET區之間穿過該SOI矽層及該BOX層和該矽基板的一部份；無摻雜高百分比矽鍺層及無摻雜低百分比矽鍺層，在位於該PFET區上方的該BOX層之數個部份上方；閘極堆疊，在該NFET區與該PFET區中之每一者上方；以及摻硼矽鍺S/D，在該閘極堆疊相對兩側上、位於該無摻雜高百分比矽鍺層上方。
本揭示內容的數個方面包括在該NFET區上方的該SOI矽層與在該PFET區上方的該無摻雜高百分比矽鍺層有5奈米至10奈米的厚度。另一方面包括該無摻雜高百分比矽鍺層與該無摻雜低百分比矽鍺層分別包括20至50百分比之鍺與5至20百分比之鍺。
熟諳此藝者由以下詳細說明可明白本揭示內容的其他方面及技術效果，其中係僅以預期可實現本揭示內容的最佳模式舉例描述本揭示內容的具體實施例。應瞭解，本揭示內容能夠做出其他及不同的具體實施例，以及在各種明顯的方面，能夠修改數個細節而不脫離本揭示 內容。因此，附圖及說明內容本質上應被視為圖解說明用而不是用來限定。
101‧‧‧矽鰭片
103‧‧‧矽基板
105‧‧‧閘極介電層
107‧‧‧閘極
109a‧‧‧低K間隔體
109b‧‧‧硬遮罩
113‧‧‧u形空腔
201‧‧‧無摻雜高百分比矽鍺層
201'‧‧‧無摻雜高百分比矽鍺層
301‧‧‧氧化物層
303‧‧‧分級矽鍺百分比PFET通道
305‧‧‧無摻雜低百分比矽鍺層
307‧‧‧矽鍺鰭片
501‧‧‧S/D區
601‧‧‧矽基板
603‧‧‧NFET區
605‧‧‧PFET區
607‧‧‧BOX層
609、609'‧‧‧SOI矽層
611‧‧‧STI柱體
613、615‧‧‧閘極堆疊
617、619‧‧‧硬遮罩層
701‧‧‧無摻雜高百分比矽鍺層
703‧‧‧無摻雜低百分比矽鍺層
801‧‧‧無缺陷摻硼S/D區
在此用附圖舉例說明而不是限定本揭示內容，圖中類似的元件用相同的元件符號表示。
第1圖至第5圖的橫截面圖根據一示範具體實施例示意圖示用於形成有分級矽鍺百分比PFET通道之FinFET裝置的製程流程；以及第6圖至第8圖的橫截面圖根據一示範具體實施例示意圖示用於形成有分級矽鍺百分比PFET通道之FDSOI裝置的製程流程。
為了解釋，在以下的說明中，提出許多特定細節供徹底瞭解示範具體實施例。不過，顯然沒有該等特定細節或用等價配置仍可實施示範具體實施例。在其他情況下，眾所周知的結構及裝置用方塊圖圖示以免不必要地混淆示範具體實施例。此外，除非另有說明，在本專利說明書及申請專利範圍中表示成分、反應狀態等等之數量、比例及數值性質的所有數字應被理解為在所有情況下可用措辭“約”來修飾。
本揭示內容針對及解決在後閘極(post gate)矽鍺通道凝結後隨之而來的矽鍺鰭片Leff效能及良率的當前問題。尤其是，解決該等問題係藉由高鍺百分比通道層之後閘極熱凝結及氧化以在FinFET或FDSOI裝置中形 成分級(graded)矽鍺百分比PFET通道以防止矽鍺堆積缺陷(stacking fault)，致能標準高溫STI製程與標準鰭片顯露(fin reveal)製程，且避免形成晶體缺陷，這通常與早期矽鍺鰭片形成技術有關。
根據本揭示內容具體實施例的方法包括：形成複數個矽鰭片於矽基板上方。形成閘極介電層於該複數個矽鰭片上方。形成閘極於該複數個矽鰭片中之每一者上方。形成一硬遮罩及間隔體層於各閘極的數個側壁上方及各閘極的數個側壁上。在該複數個矽鰭片中形成鄰近該閘極及間隔體層的一u形空腔。一無摻雜高百分比矽鍺層在各u形空腔中沿著各矽鰭片之數個側壁磊晶成長。熱凝結該無摻雜高百分比矽鍺層，這在該基板及數個矽鰭片底下形成一無摻雜低百分比矽鍺，以及形成一S/D區於在各u形空腔中的該無摻雜高百分比矽鍺層上方，該S/D區的一上表面低於該閘極介電層。
又在其他方面，熟諳此藝者從以下說明可輕易明白特徵及技術效果，其中僅通過圖解說明考慮的最佳模式來圖示及描述較佳具體實施例。本揭示內容能為其他及不同的具體實施例，以及它的數個細節在各種明顯方面能夠修改。因此，附圖及說明應被視為本質上是圖解說明用，而非限制。
第1圖至第5圖的橫截面圖根據一示範具體實施例示意圖示用於形成具有分級矽鍺百分比PFET通道之FinFET裝置的製程流程。參照第1圖，在矽基板103 的PFET區上方形成數個矽鰭片101，例如，有100奈米至200奈米的高度，其中有30奈米至50奈米的主動部份，以及寬度有5奈米至12奈米。然後，形成例如厚度有10埃至30埃的閘極介電層105於矽鰭片101上方。在後續加工期間，閘極介電層105可由例如二氧化矽(SiO2)形成，且二氧化矽可換成高k閘極介電質，例如，HfO2(為了便於圖解說明而未圖示)。接下來，形成例如由多晶矽製成的閘極107於閘極介電層105上方。在取代金屬閘極(RMG)加工期間，該多晶矽隨後可換成包括TiN及鎢(W)的金屬堆疊(為了便於圖解說明而未圖示)。隨後，在各閘極107的側壁上方及側壁上形成由例如SiN構成的硬遮罩及間隔體層，而形成低K間隔體109a與硬遮罩109b。低K間隔體109a及硬遮罩109b防止閘極107上的磊晶成長，且該低k材料保護互補裝置(亦即，NFET)免於磊晶成長。然後，例如用乾蝕刻法蝕刻矽鰭片101與矽基板103以形成鄰近閘極107及低K間隔體109a、有例如40奈米至50奈米之深度的u形空腔113。
接下來，在矽鰭片101的側壁上與在u形空腔113上方磊晶成長例如有20至100百分比之鍺(例如，20至50百分比)的無摻雜高百分比矽鍺層201，如第2圖所示。參照第3圖，無摻雜高百分比矽鍺層201熱凝結而在無摻雜高百分比矽鍺層201上方形成例如厚度有10奈米至25奈米的氧化物層301，並且將鍺推進到在各閘極107及閘極介電層105下的分級矽鍺百分比PFET通道 303。結果，在無摻雜高百分比矽鍺層201、閘極介電層105及矽基板103之間形成例如有5至20百分比之鍺的無摻雜低百分比矽鍺層305，而形成矽鍺鰭片307與分級矽鍺百分比PFET通道303(無摻雜高百分比矽鍺層201及無摻雜低百分比矽鍺層305)。無摻雜低百分比矽鍺層305可在短通道裝置之例如有14奈米至20奈米的通道區下面完全延伸，以及在長通道裝置之例如有30奈米或更多的通道區下面部份延伸。
參照第4圖，移除氧化物層301從而減薄無摻雜高百分比矽鍺層201，例如，減薄到4.5奈米至20奈米的厚度，形成無摻雜高百分比矽鍺層201’。接下來，在各u形空腔113中，形成在無摻雜高百分比矽鍺層201’上方且沿著矽鍺鰭片307之側壁向上達到閘極介電層105的例如摻硼矽鍺的S/D區501，如第5圖所示。結果，熱氧化導致在無摻雜低百分比矽鍺層305中的鍺百分比較低，且在無摻雜低百分比矽鍺層305與隨後形成之S/D區之界面處的鍺百分比較高。
第6圖至第8圖的橫截面圖根據一示範具體實施例示意圖示用於形成具有分級矽鍺百分比PFET通道之FDSOI裝置的製程流程。參照第6圖，形成有NFET區603及PFET區605的矽基板601。形成BOX層607，例如，厚度有10奈米至25奈米，於矽基板601上方。然後，形成SOI矽層609，例如，厚度有5奈米至10奈米，於BOX層607上方。接下來，在NFET區與PFET區603 及605之間，形成分別穿過SOI矽層609及BOX層607、和矽基板601之一部份的STI柱體611，例如，深度有10奈米至150奈米。隨後，例如，藉由閘極圖案化，形成閘極堆疊613及615於在NFET區603及PFET區605上方之SOI矽層609的數個部份上方。閘極堆疊613包括在SOI矽層609之數個部份上方形成例如厚度約有15埃的HfO2介電層(為了便於圖解說明而未圖示)；在HfO2介電層上方形成例如厚度約有10奈米的TiN WF金屬層(為了便於圖解說明而未圖示)；以及在TiN WF金屬層上方形成例如厚度有20奈米至50奈米的多晶矽層(為了便於圖解說明而未圖示)。
接下來，於各閘極堆疊613上方形成例如由氮化矽(SiN)構成的硬遮罩層617，且厚度有10奈米至30奈米。之後，以共形(conformally)的方式於矽基板601上方形成例如由氮化物構成的硬遮罩層，且厚度有3奈米至15奈米，然後回蝕，在NFET區603及STI柱體611的一部份上方以及沿著在PFET區605上方之閘極堆疊615及硬遮罩層617的側壁，形成硬遮罩層619。
參照第7圖，在位於PFET區605上方的SOI矽層609上方，磊晶成長無摻雜高百分比矽鍺層(為了便於圖解說明而未圖示)，例如，到20奈米至30奈米的厚度。類似以上在說明第3圖時所述的製程步驟，該無摻雜高百分比矽鍺受到熱凝結而產生氧化物層(為了便於圖解說明而未圖示)，且鍺被推進SOI矽層609及在閘極堆疊 615下的通道區，而形成SOI矽層609’，無摻雜高百分比矽鍺層701，例如，有20至50百分比之鍺，以及無摻雜低百分比矽鍺層703，例如，有5至20百分比之鍺(亦即，形成分級矽鍺百分比PFET通道)。接下來，移除該氧化物層。
如第8圖所示，磊晶成長無缺陷摻硼S/D區801於SOI矽層609’上方。結果，類似第5圖，在閘極堆疊615下的通道區有較低百分比之鍺且通道區與無缺陷摻硼S/D區801的界面處有高百分比之鍺，亦即，在通道/S/D界面處形成有較高鍺百分比的超陡峭接面(ultra-steep junction)。
本揭示內容的具體實施例可實現數種技術效果，包括避免習知的矽鍺鰭片整合限制(低溫STI及晶體缺陷，源於高鍺百分比的較陡峭接面，以及預期源於熱凝結鍺的高應力。此外，關於FDSOI裝置，技術效果包括致能更好地避免超薄SOI通道的結塊缺陷(agglomeration defect)，致能超陡峭接面，以及致能具有緊密NFET/PFET空間之SRAM裝置的閾值電壓偏移(Vt shift)。根據本揭示內容之具體實施例形成的裝置在產業上可用於各種工業應用，例如，微處理器、智慧型手機、行動電話、手機、機上盒、DVD燒錄機及播放機、汽車導航、印表機及周邊設備，網路及電信設備，遊戲系統及數位相機。本揭示內容因此在產業上可應用於各種FinFET或FDSOI裝置，特別是應用於例如14奈米及更先進的技術節點。
在以上說明中，特別用數個示範具體實施例描述本揭示內容。不過，顯然仍可做出各種修改及改變而不脫離本揭示內容更寬廣的精神及範疇，如申請專利範圍所述。因此，本專利說明書及附圖應被視為圖解說明用而非限定。應瞭解，本揭示內容能夠使用各種其他組合及具體實施例以及在如本文所述的本發明概念範疇內能夠做出任何改變或修改。

Claims (19)

  1. 一種製造半導體裝置之方法，該方法包含：形成複數個矽(Si)鰭片於矽基板上方；形成閘極介電層於該複數個矽鰭片上方；形成閘極於該複數個矽鰭片中之每一者上方；形成硬遮罩(HM)及間隔體層於各閘極的數個側壁上方及各閘極的數個側壁上；在該複數個矽鰭片中形成鄰近該閘極及間隔體層的一u形空腔；在各u形空腔中且沿著各矽鰭片之數個側壁磊晶成長無摻雜高百分比矽鍺(SiGe)層；熱凝結該無摻雜高百分比矽鍺層，以在該基板及數個矽鰭片底下形成無摻雜低百分比矽鍺；以及形成源極/汲極(S/D)區於在各u形空腔中的該無摻雜高百分比矽鍺層上方，該S/D區的上表面低於該閘極介電層。
  2. 如申請專利範圍第1項所述之方法，其中，該無摻雜高百分比矽鍺層包含20至50百分比之鍺(Ge)。
  3. 如申請專利範圍第1項所述之方法，其中，該無摻雜低百分比矽鍺層包含5至20百分比之鍺。
  4. 如申請專利範圍第1項所述之方法，更包含：移除藉由該無摻雜高百分比矽鍺層之該熱凝結而形成的氧化物層。
  5. 如申請專利範圍第1項所述之方法，包含：形成有摻硼 (B)矽鍺的該S/D區。
  6. 一種半導體裝置，包含：複數個無摻雜低百分比矽鍺(SiGe)鰭片，在矽(Si)基板上方，具有u形無摻雜低百分比矽鍺層在其間；無摻雜高百分比矽鍺層，在該u形無摻雜低百分比矽鍺層上方且沿著該等無摻雜低百分比矽鍺鰭片之數個側壁；源極/汲極(S/D)區，在該無摻雜高百分比矽鍺層上方，該S/D區的上表面與該等無摻雜低百分比矽鍺鰭片的上表面共面；閘極介電層，在各個無摻雜低百分比矽鍺鰭片上方；閘極，在該閘極介電層上方；以及硬遮罩(HM)及間隔體層，在各閘極之相對側壁上方及各閘極之相對側壁上。
  7. 如申請專利範圍第6項所述之半導體裝置，其中，該等無摻雜低百分比矽鍺鰭片包含5至20百分比之鍺(Ge)。
  8. 如申請專利範圍第6項所述之半導體裝置，其中，該無摻雜低百分比矽鍺層完全延伸越過短通道裝置的通道區且在長通道裝置的通道區下部份延伸。
  9. 如申請專利範圍第6項所述之半導體裝置，其中，該無摻雜高百分比矽鍺層包含20至50百分比之鍺。
  10. 如申請專利範圍第6項所述之半導體裝置，其中，該無摻雜高百分比矽鍺層有4.5奈米至20奈米的厚度。
  11. 一種製造半導體裝置之方法，該方法包含：提供埋藏氧化物(BOX)層於具有n型場效電晶體(NFET)區及p型場效電晶體(PFET)區的矽(Si)基板上方；提供絕緣體上覆矽(SOI)矽層於該BOX層上方；形成淺溝槽隔離(STI)柱體，其在該NFET與該PFET區之間穿過該SOI矽層及該BOX層和該基板的一部份；形成閘極堆疊及第一硬遮罩(HM)於該NFET區與該PFET區中之每一者上方；在位於該NFET區上方的該SOI矽層上方以及沿著在該PFET區上方之該閘極堆疊及該第一硬遮罩的數個側壁，形成第二硬遮罩；磊晶成長無摻雜高百分比矽鍺(SiGe)層於在該PFET區上方的該SOI矽層上方；熱凝結該無摻雜高百分比矽鍺層，以將在該PFET區上方的該SOI矽層轉換為無摻雜高百分比矽鍺(SiGe)層與形成於該第二硬遮罩及該閘極堆疊之一部份底下的無摻雜低百分比矽鍺；以及成長摻硼(B)矽鍺源極/汲極(S/D)區於在該PFET區上方的該無摻雜高百分比矽鍺層上方。
  12. 如申請專利範圍第11項所述之方法，包含用以下步驟轉換在該PFET區上方的該SOI矽層：將鍺(Ge)推進該SOI矽層；以及 移除藉由該無摻雜高百分比矽鍺層之該熱凝結而形成的氧化物層。
  13. 如申請專利範圍第11項所述之方法，包含：形成厚度有5奈米(nm)至10奈米的該SOI矽層。
  14. 如申請專利範圍第11項所述之方法，包含用下列步驟形成各閘極堆疊：形成氧化鉿(HfO2)介電層於在該NFET區與該PFET區上方的該SOI矽層上方；形成氮化鈦(TiN)功函數(WF)金屬層於該HfO2介電層上方；以及形成多晶矽層於該TiN WF金屬層上方。
  15. 如申請專利範圍第11項所述之方法，包含用下列步驟形成該硬遮罩：形成該硬遮罩於該基板上方；以及移除在該SOI矽層上方的該硬遮罩與在該PFET區上方的該第一硬遮罩，留下沿著該第一硬遮罩及閘極堆疊之該等側壁的該硬遮罩。
  16. 如申請專利範圍第11項所述之方法，其中，該無摻雜高百分比矽鍺層包含20至50百分比之鍺(Ge)。
  17. 如申請專利範圍第11項所述之方法，其中，該無摻雜低百分比矽鍺層包含5至20百分比之鍺。
  18. 一種半導體裝置，包含：埋藏氧化物(BOX)層，在具有n型場效電晶體(NFET)區及p型場效電晶體(PFET)區之矽(Si)基板上方； 絕緣體上覆矽(SOI)矽層，在位於該NFET區上方之該BOX層上方；淺溝槽隔離(STI)柱體，在該NFET區與PFET區之間穿過該SOI矽層及該BOX層和該矽基板的一部份；無摻雜高百分比矽鍺(SiGe)層及無摻雜低百分比矽鍺(SiGe)層，在位於該PFET區上方的該BOX層之數個部份上方，其中，該無摻雜高百分比矽鍺層與該無摻雜低百分比矽鍺層分別包含20至50百分比之鍺(Ge)與5至20百分比之鍺(Ge)；閘極堆疊，在該NFET區與該PFET區中之每一者上方；以及摻硼(B)矽鍺源極/汲極(S/D)，在該閘極堆疊之相對兩側上、位於該無摻雜高百分比矽鍺層上方。
  19. 如申請專利範圍第18項所述之半導體裝置，其中，在該NFET區上方的該SOI矽層與在該PFET區上方的該無摻雜高百分比矽鍺層有5奈米(nm)至10奈米的厚度。
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