CN109389956B - Display driving apparatus and display apparatus including the same - Google Patents

Display driving apparatus and display apparatus including the same Download PDF

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Publication number
CN109389956B
CN109389956B CN201810876270.7A CN201810876270A CN109389956B CN 109389956 B CN109389956 B CN 109389956B CN 201810876270 A CN201810876270 A CN 201810876270A CN 109389956 B CN109389956 B CN 109389956B
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clock signal
display
period
clock
signal
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CN109389956A (en
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崔何娜
朴锺旼
林宪用
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LX Semicon Co Ltd
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Silicon Works Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416Control or interface arrangements specially adapted for digitisers
    • G06F3/0418Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04184Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416Control or interface arrangements specially adapted for digitisers
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

The display driving apparatus may include a clock data recovery circuit, a readout circuit, and a selector, wherein the clock data recovery circuit is configured to recover a first clock signal from an input signal having a clock embedded in data; the readout circuitry is configured to sense a touch to the display panel; and a selector configured to supply either one of the first clock signal recovered by the clock data recovery circuit and the internally generated second clock signal to the readout circuit as a third clock signal to drive the readout circuit.

Description

Display driving apparatus and display apparatus including the same
Technical Field
The present disclosure relates to a display device, and more particularly, to a display driving device for driving a touch-sensitive display panel and a display device including the same.
Background
The touch-sensitive display panel is applied not only to mobile terminals such as smart terminals but also to various electronic devices such as notebook computers, monitors, and home appliances. Such a display panel may be classified into an add-on type and a built-in type according to the position of the touch sensor. In order to reduce the thickness of the display panel, a built-in type display panel in which existing components such as common electrodes are used as touch sensing electrodes is applied to the display device.
The display driving apparatus for driving the display panel may include a readout circuit to sense a touch to the display panel. The conventional display driving apparatus receives a clock signal ECLK from the outside as a single-ended TTL input, and drives a readout circuit. However, since the conventional display driving apparatus drives the readout circuit using the clock signal as the TTL input, the display driving apparatus may be susceptible to EMI (electromagnetic interference).
Disclosure of Invention
Various embodiments relate to a display driving apparatus capable of reducing EMI, and a display apparatus including the same.
In an embodiment, a display driving apparatus may include a clock data recovery circuit, a readout circuit, and a selector, wherein the clock data recovery circuit is configured to recover a first clock signal from an input signal having a clock embedded in data; the readout circuitry is configured to sense a touch to the display panel; and a selector configured to supply either one of the first clock signal recovered by the clock data recovery circuit and the internally generated second clock signal to the readout circuit as a third clock signal to drive the readout circuit.
In another embodiment, a display driving apparatus may include a first clock source configured to generate a first clock signal from an input signal having a clock embedded in data, a second clock source, and a selector; the second clock source is configured to generate a second clock signal with a preset frequency through internal oscillation; and a selector configured to select either one of the first clock signal and the second clock signal as a third clock signal and supply the third clock signal to the readout circuit. For touch sensing.
In another embodiment, a display device may include a timing controller configured to provide an input signal having a clock embedded in data; and the display driving apparatus is configured to recover the first clock signal from the input signal, provide any one of the first clock signal and the internally generated second clock signal as a third clock signal according to the display on/off period, and sense a touch using the third clock signal.
Drawings
Fig. 1 is a block diagram illustrating a display driving apparatus and a display apparatus including the same according to an embodiment of the present invention.
Fig. 2 is a timing chart for describing the operation of the display driving apparatus of fig. 1.
Fig. 3 is a block diagram illustrating a display driving apparatus and a display apparatus including the same according to another embodiment of the present invention.
Fig. 4 shows the input signals of the embedded clock of fig. 1 and 3.
Detailed Description
Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Terms used in the present specification and claims are not limited to typical dictionary definitions, but must be interpreted as meanings and concepts conforming to the technical idea of the present invention.
The embodiments described in the present specification and the configurations shown in the drawings are the preferred embodiments of the present invention and do not represent the overall technical idea of the present invention. Therefore, various equivalents and modifications capable of substituting for these embodiments and configurations may be provided at the time point of filing this application.
Fig. 1 is a block diagram illustrating a display driving apparatus 20 according to an embodiment of the present invention and a display apparatus including the display driving apparatus 20.
Referring to fig. 1, the display device may include a timing controller 10, a display driving device 20, a microcontroller 30, and a display panel 40.
The timing controller 10 receives image data and timing signals from a host system (not shown), performs image processing such as image quality compensation on the image data, and supplies differential input signals CEDA and CEDB, which are configured by embedding clocks in data (image and control data), to the display driving device 20.
The display driving apparatus 20 restores the first clock signal PCLK and the DATA from the input signal CEDA/CEDB, drives the display panel 40 using the restored first clock signal PCLK and the DATA, and senses a touch to the display panel 40 using the restored first clock signal PCLK. The display panel 40 is a touch-sensitive display panel that can display an image by a pixel array in which pixels are arranged in a matrix shape and sense a touch in a capacitive manner using a touch electrode as a common electrode. The display driving device 20 may include a clock data recovery circuit 22, a data driving circuit 24, an oscillator 32, a selector 34, and a readout circuit 36.
The clock DATA recovery circuit 22 recovers the first clock signal PCLK and the image and control DATA from the input signal CEDA/CEDB, supplies the recovered first clock signal and the recovered image and control DATA to the DATA driving circuit 24, and supplies the recovered clock signal PCLK to the selector 34.
The data driving circuit 24 supplies the source signal Sn corresponding to the gray-scale value of the image data to the display panel 40. The data driving circuit 24 includes a latch unit (not shown) for latching image data, a digital-to-analog converter (not shown) for converting the image data into a source signal Sn corresponding to a gray level value of the image data, and an output buffer (not shown) for buffering the source signal Sn and outputting the buffered signal to the display panel 40.
The oscillator 32 generates a second clock signal OSC _ CLK having a preset frequency through internal oscillation, and supplies the second clock signal OSC _ CLK to the selector 34. The oscillator 32 generates the second clock signal OSC _ CLK during the off period of the display and is deactivated during the on period of the display. The display off period is a downtime period in which the timing controller 10 is turned off, and may be defined as a period in which the input signals CEDA and CEDB are not input to the display driving device 20. The display turn-on period may be defined as a period in which the input signals CEDA and CEDB are input from the timing controller 10 to display an image on the display panel 40. For example, the oscillator 32 may be configured to receive the control signal CS from the microcontroller 30. Oscillator 32 may be enabled or disabled in response to control signal CS. The control signal CS has a logic level for disabling the oscillator 32 during the display on period and a logic level for enabling the oscillator 32 during the display off period.
The selector 34 selects one of the first clock signal PCLK recovered by the clock data recovery circuit 22 and the second clock signal OSC _ CLK generated by the oscillator 32 as the third clock signal CLK for sensing a touch of the display panel 40, and supplies the third clock signal CLK to the readout circuit 36. The selector 34 selects the first clock signal PCLK as the third clock signal CLK during the display ON period and selects the second clock signal OSC _ CLK as the third clock signal CLK during the display OFF period.
For example, the selector 34 selects one of the first clock signal PCLK and the second clock signal OSC _ CLK as the third clock signal CLK in response to the control signal CS of the microcontroller 30, and supplies the third clock signal CLK to the readout circuit 36. The control signal CS has a logic level for selecting the first clock signal PCLK during the display turn-on period and has a logic level for selecting the second clock signal OSC _ CLK during the display turn-off period. That is, the selector 34 supplies the third clock signal PCLK recovered from the input signal to the readout circuit 36 as the third clock signal CLK during the display-on period, and supplies the second clock signal OSC _ CLK generated at a preset frequency to the readout circuit 36 as the third clock signal CLK during the display-off period.
The readout circuit 36 senses a touch to the display panel 40 using the third clock signal CLK supplied from the selector 34, and outputs the sensing data Tdata. The sensing data Tdata may be provided to the microcontroller 30. The display panel 40 may have touch and display functions and include touch electrodes included in a pixel array. For example, the touch electrodes may be connected to the readout circuit 36 through signal lines, respectively, and set to a predetermined size including a plurality of pixels in consideration of the size of a touch point. The readout circuit 36 may supply the touch driving signal Tx to the touch electrodes of the display panel 40 in response to the clock signal CLK of the selector 34 and receive the feedback signal Rx from the corresponding touch electrodes. The readout circuit 36 may differentially amplify the touch driving signal Tx and the feedback signal Rx for each of the touch electrodes and sense whether a touch has occurred based on a change in capacitance caused by the touch.
In the display turn-on period, the readout circuit 36 supplies the touch driving signal Tx to the touch electrodes of the display panel 40 and receives the feedback signal Rx from the touch electrodes of the display panel 40 in response to the first clock signal PCLK selected as the third clock signal CLK. The readout circuit 36 converts the feedback signal Rx into the sensing data Tdata as a digital signal and supplies the sensing data Tdata to the microcontroller 30. The microcontroller 30 may sense whether a touch occurs and coordinates of the touch by sensing a change in the data Tdata based on a change in capacitance caused by the touch. For example, the readout circuit 36 may include a divider (divider) that divides the restored first clock signal PCLK by a preset value, and supplies the touch driving signal Tx to the touch electrodes of the display panel 40 using the divided internal clock signal.
In the display off period, in response to the second clock signal OSC _ CLK selected as the third clock signal CLK, the readout circuit 36 may provide the touch driving signal Tx to the touch electrodes of the display panel 40, receive the feedback signal Rx from the touch electrodes of the display panel 40, and sense a touch to the display panel 40 based on a change in capacitance caused by the touch. During the display off period, the readout circuit 36 only senses whether a touch to the display panel 40 occurs. Therefore, even if the second clock signal OSC _ CLK of the oscillator 32 changes, the readout circuit 36 can reliably sense a touch. For example, the function of sensing touch during a display off period may be used to perform a tap-and-wake (knock-on) function of a smartphone or the like, whereby a user turns on a liquid crystal screen by tapping the liquid crystal screen.
The readout circuit 36 may sense a touch to the display panel 40 in response to the first clock signal PCLK selected as the third clock signal CLK during the display turn-on period, and the readout circuit 36 may sense a touch to the display panel 40 in response to the second clock signal OSC _ CLK selected as the third clock signal CLK during the display turn-off period. The first clock signal PCLK can be divided by a predetermined value during the display turn-on period. The preset value may be set according to the data transmission rate.
The microcontroller 30 supplies the control signal CS to the selector 34 of the display driving apparatus 20. The microcontroller 30 controls the selector 34 to select the second clock signal OCS _ CLK generated by the oscillator during the display off period. Further, the microcontroller 30 controls the selector 34 to select the first clock signal PCLK recovered by the clock data recovery circuit 22 during the display-on period. For example, the microcontroller 30 may provide the low level control signal CS during the display on period and provide the high level control signal CS during the display off period. Then, the selector 34 may select the first clock signal PCLK in response to the low level control signal CS during the display turn-on period and select the second clock signal OSC _ CLK in response to the high level control signal CS during the display turn-off period. The control signal CS may be transmitted as a control data packet through an interface (e.g., SPI) between the micro controller 30 and the display driving device 20. The microcontroller 30 may receive the sensing data Tdata from the readout circuit 36 and determine whether a touch to the display panel 40 occurs and coordinates of the touch based on a change in the sensing data Tdata caused by the touch.
According to the present embodiment, the clock data recovery circuit 22 for recovering the first clock signal PCLK from the input signal CEDA/CEDB is used as a first clock source during the display turn-on period, and the oscillator 32 for generating the second clock signal OSC _ CLK having a preset frequency is used as a second clock source during the display turn-off period.
Fig. 2 is a timing diagram for describing the operation of fig. 1.
Referring to fig. 1 and 2, the display driving apparatus 20 drives the readout circuit 36 using the first clock signal PCLK recovered from the input signal CEDA/CEDB during the display turn-on period, and drives the readout circuit 36 using the second clock signal OSC _ CLK of the oscillator 32 during the display turn-off period. For example, a function of sensing a touch to the display panel 40 during a display off period may be used to perform a tap wake-up function of a smart phone or the like, whereby a user turns on a liquid crystal screen by tapping the liquid crystal screen. In the display off period, the display driving apparatus 20 only senses whether a touch to the display panel 40 occurs. Therefore, the display driving apparatus 20 may reliably sense a touch using the second clock signal OSC _ CLK of the oscillator 32.
In the present embodiment, the display driving apparatus 20 may divide the first clock signal PCLK recovered from the input signal CEDA/CEDB during the display turn-on period and sense a touch to the display panel 40 and coordinates of the touch using the divided internal clock signal (not shown). The touch coordinates are used by the host system to execute instructions or applications connected to the touch coordinates. The host system may include a desk or a system of smart phones, computers, television systems, set-top boxes, and the like. A divider (not shown) for dividing the restored first clock signal PCLK may be included in the readout circuit 36. Alternatively, the divider may be included in the clock data recovery circuit 22, or disposed between the clock data recovery circuit 22 and the readout circuit 36.
Fig. 3 is a block diagram illustrating a display driving apparatus and a display apparatus including the same according to another embodiment of the present invention. The description of the same components as those of the embodiment of fig. 1 will be replaced with or simply described using the description of fig. 1.
Referring to fig. 3, the display device may include a timing controller 10, a display driving device 20, and a display panel 40.
The timing controller 10 performs image processing such as image quality compensation on the image data, generates control data for controlling operation timing of the display driving device 20, and embeds the image and control data and a clock into the differential input signals CEDA and CEDB. The timing controller 10 supplies differential input signals CEDA and CEDB configured by embedding clocks in data to the display driving device 20.
The display driving apparatus 20 restores the first clock signal PCLK and the DATA from the input signal CEDA/CEDB, drives the display panel 40 using the restored first clock signal PCLK and the DATA, and senses whether a touch to the display panel 40 occurs using the first clock signal PCLK. The display driving apparatus 20 includes a clock data recovery circuit 22, a data driving circuit 24, an oscillator 32, a selector 34, and a readout circuit 36.
The clock DATA recovery circuit 22 recovers the first clock signal PCLK and the DATA from the input signal CEDA/CEDB, supplies the recovered first clock signal and DATA to the DATA driving circuit 24, and supplies the recovered first clock signal PCLK to the selector 34.
The clock data recovery circuit 22 supplies the LOCK signal LOCK to the selector 34. The lock signal has different logic levels according to a display on period and a display off period. For example, the clock data recovery circuit 22 may provide the high-level LOCK signal LOCK to the selector 34 during a display-on period in which the differential input signals CEDA and CEDB are received, and provide the low-level clock signal LOCK to the selector 34 during a display-off period.
The oscillator 32 generates a second clock signal OCS _ CLK having a preset frequency through internal oscillation and supplies the second clock signal OCS _ CLK to the selector 34. For example, oscillator 32 may be disabled during display on periods and enabled during display off periods. For example, the oscillator 32 may be configured to receive the control signal CS from the microcontroller 30. Oscillator 32 may be enabled or disabled in response to control signal CS. The control signal CS has a logic level for disabling the oscillator 32 during the display on period and a logic level for enabling the oscillator 32 during the display off period. The selector 34 selects one of the first clock signal PCLK and the second clock signal OSC _ CLK as the third clock signal CLK in response to the LOCK signal LOCK, and supplies the third clock signal CLK to the readout circuit 36. For example, the selector 34 may select the first clock signal PCLK in response to the high-level LOCK signal LOCK during the display turn-on period and select the second clock signal OSC _ CLK in response to the low-level LOCK signal LOCK during the display turn-off period. That is, the selector 34 selects the first clock signal PCLK recovered by the clock data recovery circuit 22 as the third clock signal CLK during the display-on period or selects the second clock signal OSC _ CLK as the third clock signal CLK during the display-off period and supplies the third clock signal CLK to the readout circuit 36.
The readout circuit 36 senses a touch to the display panel 40 in response to the first clock signal PCLK or the second clock signal OSC _ CLK supplied from the selector 34 as the third clock signal CLK. For example, the readout circuit 36 supplies the touch driving signal Tx to the touch electrodes of the display panel 40 in response to the first clock signal PCLK during the display turn-on period, and supplies the touch driving signal Tx to the touch electrodes of the display panel 40 in response to the second clock signal OSC _ CLK during the display turn-off period. The readout circuit 36 receives a feedback signal Rx from the touch electrode of the display panel 40 and senses a touch to the display panel 40 based on a change in capacitance caused by the touch.
The readout circuit 36 may sense a touch to the display panel 40 in response to the first clock signal PCLK selected as the third clock signal CLK during the display turn-on period, and the readout circuit 36 may sense a touch to the display panel 40 in response to the second clock signal OSC _ CLK selected as the third clock signal CLK during the display turn-off period. The first clock signal PCLK may be divided by a period value during the display turn-on period.
Fig. 4 shows the clock signal embedded input signal CEDA/CEDB of fig. 1 and 3.
Data communication between the timing controller 10 and the display driving device 20 may be implemented in various ways. In the present embodiment, the input signal CEDA/CEDB may be transmitted through CEDS (clock-embedded data signaling). The CEDS may be defined as a communication method of packetizing data into a format having a clock CK embedded in the data.
As shown in fig. 4, the input signal CEDA/B in which the clock CK is embedded may be transmitted as a data packet. For example, one packet may have 28UI (unit interval), and each of the packets may include a delimiter of 4UI and data of 24 UI. The delimiter of 4UI may include a virtual DMY and a clock CK, and the data of 24UI may include image and control data. In fig. 4, the delimiter is 4-bit data represented by "0011", and "00" in the 4-bit data corresponds to the virtual DMY, and "11" corresponds to the clock CK. The delimiter can be applied to all data packets as the same number of bits and the same data value.
The clock data recovery circuit 22 may divide the packet data by the dummy DMY input of "00", recover the edge of the first clock signal PCLK by the clock CK input of "11", and recover the first clock signal PCLK of 28UI by the internal logic circuit. Further, the clock data recovery circuit 22 may generate a sampling clock signal using the first clock signal PCKL and recover data using the sampling clock signal.
The first clock signal PCLK recovered by the clock data recovery circuit 22 may be supplied to the readout circuit 36 during the display turn-on period, and used to sense whether a touch to the display panel 40 occurs and the coordinates of the touch. The first clock signal PCLK may be divided by a time value for sensing whether a touch to the display panel 40 occurs and coordinates of the touch. The preset value may be set according to the data transmission rate. For example, when the data transmission rate is 2.0Gb/s, the first clock signal PCLK has a frequency of 71.4Mhz, and may be divided into internal clock signals of 17.85Mhz corresponding to division by four clocks. The first clock signal PCLK has a frequency of 42.8Mhz when the data transmission rate is 1.2Gb/s, and may be divided into an internal clock signal of 21.4Mhz corresponding to division by two clocks or an internal clock signal of 10.4Mhz corresponding to division by four clocks.
According to an embodiment of the present invention, the display driving apparatus 20 may sense a touch to the display panel 40 using the first clock signal PCLK recovered from the input signal CEDA/CEDB having the clock embedded in the data or the internally generated second clock signal OSC _ CLK, thereby reducing EMI caused by the clock signal ECLK input as the single-ended TTL.
While various embodiments have been described above, those skilled in the art will appreciate that these embodiments are only examples. Accordingly, the disclosure described herein should not be limited based on the described embodiments.

Claims (14)

1. A display driving device comprising:
a clock data recovery circuit configured to recover a first clock signal from an input signal having a clock embedded in data;
a readout circuit configured to sense a touch to the display panel; and
a selector configured to supply either one of the first clock signal recovered by the clock data recovery circuit and an internally generated second clock signal as a third clock signal to the readout circuit to drive the readout circuit, an
Wherein the display driving apparatus divides the first clock signal recovered from the input signal by a preset value, which can be set according to a data transmission rate, during a display turn-on period, and drives the readout circuit using the divided internal clock signal.
2. The display driving apparatus according to claim 1, wherein the selector selects the second clock signal as the third clock signal in response to a period in which the clock is not received.
3. The display drive apparatus according to claim 1,
the selector selects the first clock signal as the third clock signal during a display turn-on period, an
The selector selects the second clock signal as the third clock signal during a display off period.
4. The display drive apparatus according to claim 1, further comprising:
an oscillator configured to generate the second clock signal having a preset frequency and provide the second clock signal to the selector.
5. The display driving apparatus according to claim 1, wherein the selector receives a control signal from a microcontroller, the control signal having different logic levels according to a display on period and a display off period.
6. The display drive apparatus according to claim 5,
the selector selects the first clock signal in response to the control signal having a logic level corresponding to the display turn-on period, an
The selector selects the second clock signal in response to the control signal having a logic level corresponding to the display off period.
7. The display driving apparatus according to claim 1, wherein the clock data recovery circuit supplies a lock signal to the selector, the lock signal having different logic levels according to a display on period and a display off period, and
the selector selects the first clock signal in response to the lock signal having a logic level corresponding to the display turn-on period, an
The selector selects the second clock signal in response to the lock signal having a logic level corresponding to the display off period.
8. A display driving device comprising:
a first clock source configured to generate a first clock signal from an input signal having a clock embedded in data;
a second clock source configured to generate a second clock signal having a preset frequency through internal oscillation; and
a selector configured to select either one of the first clock signal and the second clock signal as a third clock signal and supply the third clock signal to a readout circuit for touch sensing, an
Wherein the display driving apparatus divides the first clock signal recovered from the input signal by a preset value, which can be set according to a data transmission rate, during a display turn-on period, and drives the readout circuit using the divided internal clock signal.
9. The display driving apparatus according to claim 8, wherein the selector selects the second clock signal as the third clock signal in response to a period in which the clock is not received.
10. The display drive apparatus according to claim 8,
the selector selects the first clock signal as the third clock signal during a display turn-on period, an
The selector selects the second clock signal as the third clock signal during a display off period.
11. A display device, comprising:
a timing controller configured to provide an input signal having a clock embedded in data;
a display driving device configured to recover a first clock signal from the input signal, provide any one of the first clock signal and an internally generated second clock signal as a third clock signal according to a display on/off period, and sense a touch using the third clock signal; and
a readout circuit configured to sense a touch to the display panel, an
Wherein the display driving apparatus divides the first clock signal recovered from the input signal by a preset value, which can be set according to a data transmission rate, during a display turn-on period, and drives the readout circuit using the divided internal clock signal.
12. The display device according to claim 11, further comprising:
a microcontroller configured to provide control signals to the display driving apparatus, the control signals having different logic levels according to the display turn-on period and the display turn-off period,
wherein, in response to the control signal, the display driving apparatus selects the first clock signal as the third clock signal during the display on period or selects the second clock signal as the third clock signal during the display off period.
13. The display device according to claim 11, wherein the display driving device comprises:
a clock data recovery circuit configured to recover the first clock signal and data from the input signal;
a data driving circuit configured to supply a source signal corresponding to a gray value of the data to the display panel; and
a selector configured to select either one of the first clock signal recovered by the clock data recovery circuit and the internally generated second clock signal as a third clock signal and supply the third clock signal to the readout circuit to drive the readout circuit.
14. The display device of claim 13, wherein the clock data recovery circuit provides a lock signal to the selector, the lock signal having different logic levels depending on the display on period and the display off period, an
In response to the lock signal, the selector selects the first clock signal as the third clock signal during the display on period or selects the second clock signal as the third clock signal during the display off period.
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