CN109388177B - Inter-core time sequence synchronization method and data transmission method based on multi-core DSP - Google Patents
Inter-core time sequence synchronization method and data transmission method based on multi-core DSP Download PDFInfo
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- CN109388177B CN109388177B CN201811194441.4A CN201811194441A CN109388177B CN 109388177 B CN109388177 B CN 109388177B CN 201811194441 A CN201811194441 A CN 201811194441A CN 109388177 B CN109388177 B CN 109388177B
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Abstract
The invention discloses an inter-core time sequence synchronization method and a data transmission method based on a multi-core DSP, wherein the inter-core time sequence synchronization method comprises the following steps: setting a system clock of a DSP, wherein the DSP sends a timing interrupt according to a predefined timing period; setting a first computing period of a first kernel and a second computing period of a second kernel in the DSP, wherein the first computing period is greater than or equal to the timing period, and the first computing period is smaller than the second computing period; the first kernel determines a first starting point of a first computing period and a second starting point of a second computing period in the first kernel according to the received timed interrupt, and respectively sends an interrupt to the second kernel as the starting points of the first computing period and the second computing period in the second kernel. The embodiment provided by the invention can solve the problem of time sequence synchronization of different calculation periods among the cores in the multi-core DSP and effectively improve the data transmission efficiency among the cores.
Description
Technical Field
The invention relates to the field of embedded system development, in particular to an inter-core time sequence synchronization method and a data transmission method based on a multi-core DSP.
Background
Compared with the traditional embedded system, the embedded system is widely applied to the embedded system market at present, and is based on a multi-core DSP (Digital Signal Processing) system, the multi-core DSP system is provided with a plurality of cores with higher reliability, a plurality of independent data Processing devices can be integrated through deep fusion, and the traditional low-speed communication interface in the past is replaced by an inter-core interface, so that the volume of the device is reduced, the reliability is improved, and the time delay of internal communication is shortened.
However, when the method is applied to an information processing system on a missile, the time of each calculation cycle of a plurality of cores in the multi-core DSP is different, and how to synchronize the time sequences of different calculation cycles among the plurality of cores becomes a key problem to be solved by the multi-core DSP.
Disclosure of Invention
In order to solve at least one of the above problems, a first aspect of the present invention provides a method for inter-core timing synchronization based on a multi-core DSP, comprising:
setting a system clock of a DSP, wherein the DSP sends a timing interrupt according to a predefined timing period;
setting a first computing period of a first kernel and a second computing period of a second kernel in the DSP, wherein the first computing period is greater than or equal to the timing period, and the first computing period is smaller than the second computing period;
the first kernel determines a first starting point of a first computing period and a second starting point of a second computing period in the first kernel according to the received timed interrupt, and respectively sends a first interrupt to the second kernel at the first starting point and a second interrupt to the second kernel at the second starting point;
and the second core receives the first interrupt and the second interrupt and respectively serves as a first starting point of a first computing period and a second starting point of a second computing period in the second core.
Further, the timing period is a divisor of the first calculation period and a divisor of the second calculation period.
Further, the first computation cycle is a divisor of the second computation cycle.
Furthermore, the inter-core timing synchronization method also comprises a first counter and a second counter for accumulating the number of the timed interruption,
when the first core receives the timing interruption for the first time, the first counter starts counting, a first starting point of the first computing period in the first core is determined according to the multiple relation between the timing period and the first computing period, and the first counter is cleared;
and when the first core receives the timing interrupt for the first time, the second counter starts counting, a second starting point of the second calculation period in the first core is determined according to the multiple relation between the timing period and the second calculation period, and the second counter is cleared.
Further, the first core clock used by the first core and the second core clock used by the second core are the same source clock.
Further, the first interrupt and the second interrupt are both inter-core interrupts.
A second aspect of the present invention provides a transmission method for transmitting data by using the inter-core timing synchronization method of the first aspect, including:
synchronizing the first core and the second core;
the first kernel collects data at a first starting point of each first computation cycle, transmits the collected data to the second kernel at a second starting point of the second computation cycle, and sends the second interrupt;
and the second kernel receives the second interrupt and the acquired data and performs data processing on the acquired data.
Further, the first core and the second core adopt an inter-core bus to perform data transmission.
A third aspect of the invention provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the method of the first aspect.
A fourth aspect of the invention provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the method of the second aspect.
The invention has the following beneficial effects:
the invention provides an inter-core time sequence synchronization method and a data transmission method based on a multi-core DSP, which respectively determine the starting points of a first calculation period and a second calculation period in a first core by setting a system clock and a timing interrupt of the DSP, and respectively determine the starting points of the first calculation period and the second calculation period in the second core by the first interrupt and the second interrupt sent by the first core, thereby realizing the inter-core time sequence synchronization problem in the multi-core DSP and effectively improving the inter-core data transmission efficiency.
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The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
FIG. 1 is a flow diagram illustrating a method for inter-core timing synchronization in one embodiment of the invention;
FIG. 2 is a diagram illustrating the inter-core timing synchronization method according to an embodiment of the present invention;
FIG. 3 shows a timing diagram of the inter-core timing synchronization method in one embodiment of the invention;
fig. 4 shows a flow chart of the data transmission method in an embodiment of the invention.
Detailed Description
In order to more clearly illustrate the invention, the invention is further described below with reference to preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
As shown in fig. 1, an embodiment of the present invention provides a method for timing synchronization between cores based on a multi-core DSP, including: setting a system clock of a DSP, wherein the DSP sends a timing interrupt according to a predefined timing period; setting a first computing period of a first kernel and a second computing period of a second kernel in the DSP, wherein the first computing period is greater than or equal to the timing period, and the first computing period is smaller than the second computing period; the first kernel determines a first starting point of a first computing period and a second starting point of a second computing period in the first kernel according to the received timed interrupt, and respectively sends a first interrupt to the second kernel at the first starting point and a second interrupt to the second kernel at the second starting point; and the second core receives the first interrupt and the second interrupt and respectively serves as a first starting point of a first computing period and a second starting point of a second computing period in the second core.
In one specific example, as shown in FIG. 2, the system clock of the DSP is set to 50MHz, the predefined timing period is 0.05ms, and the DSP sends timed interrupts at a frequency of 20KHz according to the timing period. The first kernel of the DSP is used for collecting data and circularly collects the data according to a first computing period of the first kernel; and the second core of the DSP is used for processing the acquired data and circularly calculating and processing the acquired data in a second calculation period of the second core. In order to improve the reliability and stability of the data acquisition and processing of the DSP, the timing period is set to be a divisor of the first calculation period and a divisor of the second calculation period, and further, the first calculation period is a divisor of the second calculation period, in this embodiment, the first calculation period is set to be 0.25ms, and the second calculation period is set to be 5 ms. The first kernel receives the timed interrupt, determines a first starting point of the first computing period in the first kernel according to the duration of the first computing period by taking the timed interrupt as a timing starting point, and sends a first interrupt to the second kernel, wherein the second kernel takes the received first interrupt as a first starting point of the first computing period in the second kernel; similarly, the first core receives the timed interrupt and determines a second start point of the second computation cycle in the first core according to the duration of the second computation cycle by using the timed interrupt as a timing start point, and sends a second interrupt to the second core, and the second core uses the received second interrupt as a second start point of the second computation cycle in the second core. To this end, the first core and the second core are synchronized.
Further, in order to improve the reliability of synchronization between the first core and the second core, the inter-core timing synchronization method further includes a first counter and a second counter for accumulating the number of times of timer interruption, where the first counter is used to determine the first computation period, the first counter starts to count when the first core receives the timer interruption for the first time, that is, the first counter accumulates once every time the first core receives the timer interruption, and a first starting point of the first computation period in the first core is determined according to a multiple relationship between the timer period and the first computation period; as shown in fig. 3, in this embodiment, a timing period t0 is 0.05ms, a first calculation period t1 is 0.25ms, and the first core takes a first received timer interrupt as a timing start t, then the first counter accumulates 5 timer interrupts as the first calculation period, and the first core can determine a first start t1 of the first calculation period according to the first counter and sends a first interrupt to a second core to determine a first start t1 of a first calculation period in the second core, and at the same time, the first counter in the first core is cleared to start cycle counting from a next timer interrupt. Similarly, the second counter is configured to determine the second computation cycle, and when the first core receives the timer interrupt for the first time, the second counter also starts counting, and a second starting point of the second computation cycle in the first core is determined according to a multiple relationship between the timing cycle and the second computation cycle; in this embodiment, if the timing period t0 is 0.05ms, and the second calculation period t2 is set to be 5ms, then the second counter accumulates 100 interrupts as the second calculation period, the first core can determine the second start t2 of the second calculation period according to the second counter, and sends a second interrupt to the second core to determine the second start t2 of the second calculation period in the second core, and meanwhile, the second clear counter in the first core starts cycle counting from the next interrupt.
It should be noted that the timing cycle, the first calculation cycle, the second calculation cycle, the first counter, and the second counter in the present invention are only used for illustration, and a person skilled in the art should set the values and the number of the timing cycle, the calculation cycle, and the counters according to the duration of the calculation cycle of the DSP core in practical application, so as to implement a specific application requirement as a design criterion, and details are not described herein.
In order to further improve the reliability of synchronization between the first core and the second core, the first core clock used by the first core and the second core clock used by the second core are homologous clocks. In this embodiment, the first core and the second core use the same external clock source, for example, FPGA as the external clock source, and simultaneously provide stable clock signals to the first core and the second core; through multiple actual measurements, the error of the same calculation period between the first kernel and the second kernel is about 10ns, and the requirement of an information processing system on the missile is met.
In order to further reduce coupling and interference between information processing systems on the missiles, the first interrupt and the second interrupt adopt inter-core interrupt of the DSP, transmission of synchronous signals between the first core and the second core is effectively improved, independence between the first core and the second core is achieved, and meanwhile unnecessary transmission errors caused by interrupt faults are avoided.
Corresponding to the inter-core timing synchronization method provided in the foregoing embodiment, an embodiment of the present application further provides a data transmission method for performing data transmission by using the inter-core timing synchronization method, as shown in fig. 4, including: synchronizing the first core and the second core; the first kernel collects data at a first starting point of each first computation cycle, transmits the collected data to the second kernel at a second starting point of the second computation cycle, and sends the second interrupt; and the second kernel receives the second interrupt and the acquired data and performs data processing on the acquired data. Therefore, under the condition that the first kernel and the second kernel are synchronous, data are transmitted between the first kernel and the second kernel, namely, the first interrupt and the second interrupt are used for circularly transmitting the data, and the quality of data transmission can be effectively improved.
Further, in order to improve the transmission rate of data transmission between the first core and the second core, the first core and the second core use an inter-core bus for data transmission, and the transmission rate may reach 10Gbps, which is much higher than the transmission rate of data transmission using the serial bus 485 or 422. Therefore, the first kernel and the second kernel use the inter-kernel bus for data transmission, and the communication efficiency is greatly improved, and meanwhile, the communication reliability is also improved.
One embodiment of the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements: setting a system clock of a DSP, wherein the DSP sends a timing interrupt according to a predefined timing period; setting a first computing period of a first kernel and a second computing period of a second kernel in the DSP, wherein the first computing period is greater than or equal to the timing period, and the first computing period is smaller than the second computing period; the first kernel determines a first starting point of a first computing period and a second starting point of a second computing period in the first kernel according to the received timed interrupt, and respectively sends a first interrupt to the second kernel at the first starting point and a second interrupt to the second kernel at the second starting point; and the second core receives the first interrupt and the second interrupt and respectively serves as a first starting point of a first computing period and a second starting point of a second computing period in the second core.
Another embodiment of the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements: synchronizing the first core and the second core; the first kernel collects data at a first starting point of each first computation cycle, transmits the collected data to the second kernel at a second starting point of the second computation cycle, and sends the second interrupt; and the second kernel receives the second interrupt and the acquired data and performs data processing on the acquired data.
In practice, the computer-readable storage medium may take any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this real-time example, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
The invention provides an inter-core time sequence synchronization method and a data transmission method based on a multi-core DSP, which respectively determine the starting points of a first calculation period and a second calculation period in a first core by setting a system clock and a timing interrupt of the DSP, and respectively determine the starting points of the first calculation period and the second calculation period in the second core by the first interrupt and the second interrupt sent by the first core, thereby realizing the inter-core time sequence synchronization problem in the multi-core DSP and effectively improving the inter-core data transmission efficiency.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.
Claims (8)
1. An inter-core time sequence synchronization method based on a multi-core DSP is characterized by comprising the following steps:
setting a system clock of a DSP, wherein the DSP sends a timing interrupt according to a predefined timing period;
setting a first computing period of a first kernel and a second computing period of a second kernel in the DSP, wherein the first computing period is greater than or equal to the timing period, and the first computing period is smaller than the second computing period;
the first kernel determines a first starting point of a first computing period and a second starting point of a second computing period in the first kernel according to the received timed interrupt, and respectively sends a first interrupt to the second kernel at the first starting point and a second interrupt to the second kernel at the second starting point;
the second core receives the first interrupt and the second interrupt and respectively serves as a first starting point of a first computing period and a second starting point of a second computing period in the second core;
wherein the timing period is a divisor of the first computation period and a divisor of the second computation period;
the inter-core timing synchronization method further includes a first counter and a second counter for accumulating the number of timer interrupts,
when the first core receives the timing interruption for the first time, the first counter starts counting, a first starting point of the first computing period in the first core is determined according to the multiple relation between the timing period and the first computing period, and the first counter is cleared;
and when the first core receives the timing interrupt for the first time, the second counter starts counting, a second starting point of the second calculation period in the first core is determined according to the multiple relation between the timing period and the second calculation period, and the second counter is cleared.
2. The method of claim 1, wherein the first computation cycle is a divisor of the second computation cycle.
3. The method of claim 1, wherein a first core clock used by the first core and a second core clock used by the second core are homologous clocks.
4. The method of inter-core timing synchronization of claim 1, wherein the first interrupt and the second interrupt are both inter-core interrupts.
5. A data transmission method for performing data transmission by using the inter-core timing synchronization method according to any one of claims 1 to 4, comprising:
synchronizing the first core and the second core;
the first kernel collects data at a first starting point of each first computation cycle, transmits the collected data to the second kernel at a second starting point of the second computation cycle, and sends the second interrupt;
and the second kernel receives the second interrupt and the acquired data and performs data processing on the acquired data.
6. The data transmission method according to claim 5, wherein the first core and the second core perform data transmission by using an inter-core bus.
7. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-4.
8. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method of claim 5 or 6.
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