CN109378987B - Three-level topological circuit, single-phase inverter and three-phase inverter - Google Patents

Three-level topological circuit, single-phase inverter and three-phase inverter Download PDF

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Publication number
CN109378987B
CN109378987B CN201811645639.XA CN201811645639A CN109378987B CN 109378987 B CN109378987 B CN 109378987B CN 201811645639 A CN201811645639 A CN 201811645639A CN 109378987 B CN109378987 B CN 109378987B
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electrically connected
diode
switch module
inductor
capacitor
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CN109378987A (en
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赵龙
苑红
李爱刚
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Sineng Electric Co ltd
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Sineng Electric Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention discloses a three-level topology circuit, a single-phase inverter and a three-phase inverter. The first end of a first inductor of the three-level topological circuit is electrically connected with the anode of the bus, and the second end of the first inductor is electrically connected with the input end of the first switch module; the output end of the first switch module is electrically connected with the input end of the second switch module; the output end of the second switch module is electrically connected with the second inductor; the anode of the first diode is electrically connected with the neutral point, and the cathode of the first diode is electrically connected with the input end of the second switch module; the first end of the third inductor is electrically connected with the negative electrode of the bus, and the second end of the third inductor is electrically connected with the output end of the fourth switch module; the input end of the fourth switch module is electrically connected with the output end of the third switch module; the input end of the third switching module is electrically connected with the second inductor; the anode of the second diode is electrically connected with the output end of the third switch module, and the cathode of the second diode is electrically connected with the midpoint of the bus. The soft switching of the inverter is realized, and the conversion efficiency of the inverter is improved.

Description

Three-level topological circuit, single-phase inverter and three-phase inverter
Technical Field
The embodiment of the invention relates to the technical field of power electronic devices, in particular to a three-level topological circuit, a single-phase inverter and a three-phase inverter.
Background
When the switch tube is switched on or switched off, the soft switch circuit enables the voltage at two ends of the switch tube to be zero or the current passing through the switch tube to be zero, so that zero-voltage switching-on or zero-current switching-off is realized, the switching-on and switching-off loss of the switch tube is reduced, the conversion efficiency of the switch tube is improved, and the soft switch circuit can be widely applied to electric energy conversion devices of power electronic devices.
At present, a soft switching circuit is mostly applied to a dc-dc conversion device, and a specific topology is required or a peripheral circuit is required to be added to realize soft start of a switching tube.
However, the soft switching circuit in the prior art is difficult to apply to the inverter, and the soft switching circuit has poor versatility, and a large number of peripheral circuits are required to be added to realize soft switching in another part of the circuit, thereby increasing the complexity and the fault point of the circuit.
Disclosure of Invention
The invention provides a three-level topological circuit, a single-phase inverter and a three-phase inverter, wherein the three-level topological circuit can be applied to the inverter, the universality of soft switching between topologies is increased, a complex peripheral circuit is avoided, and the conversion efficiency of the inverter is improved.
In a first aspect, an embodiment of the present invention provides a three-level topology circuit, including a bus positive electrode, a first inductor, a first switch module, a second switch module, a first diode, a second inductor, a third switch module, a fourth switch module, a second diode, a neutral point, and a bus negative electrode;
the first end of the first inductor is electrically connected with the positive electrode of the bus, and the second end of the first inductor is electrically connected with the input end of the first switch module;
the output end of the first switch module is electrically connected with the input end of the second switch module;
the output end of the second switch module is electrically connected with the second inductor;
the anode of the first diode is electrically connected with the neutral point, and the cathode of the first diode is electrically connected with the input end of the second switch module;
a first end of the third inductor is electrically connected with the negative pole of the bus, and a second end of the third inductor is electrically connected with an output end of the fourth switch module;
the input end of the fourth switch module is electrically connected with the output end of the third switch module;
the input end of the third switching module is electrically connected with the second inductor;
the anode of the second diode is electrically connected with the output end of the third switch module, and the cathode of the second diode is electrically connected with the neutral point.
Further, the three-level topology circuit further includes a third diode, a first capacitor, a fifth switch module, a fourth diode, a fourth inductor, a second capacitor, a fifth diode, a third capacitor, a sixth switch module, a sixth diode, a fifth inductor, and a fourth capacitor;
an anode of the third diode is electrically connected to the second end of the first inductor, and a cathode of the third diode is electrically connected to the first end of the first capacitor;
a second terminal of the first capacitor is electrically connected to the neutral point;
an input end of the fifth switching module is electrically connected with a first end of the first capacitor, and an output end of the fifth switching module is electrically connected with a first end of the fourth inductor;
a second end of the fourth inductor is electrically connected with a first end of the second capacitor;
a second terminal of the second capacitor is electrically connected to the neutral point;
the anode of the fourth diode is electrically connected with the neutral point, and the cathode of the fourth diode is electrically connected with the first end of the fourth inductor;
a cathode of the fifth diode is electrically connected with the second end of the third inductor, and an anode of the fifth diode is electrically connected with the first end of the third capacitor;
a second terminal of the third capacitor is electrically connected to the neutral point;
an input end of the sixth switching module is electrically connected with a first end of the fifth inductor, and an output end of the sixth switching module is electrically connected with a first end of the third capacitor;
the anode of the sixth diode is electrically connected with the first end of the fifth inductor, and the cathode of the sixth diode is electrically connected with the neutral point;
a second end of the fifth inductor is electrically connected with a first end of the fourth capacitor;
a second terminal of the fourth capacitor is electrically connected to the neutral point.
Further, the difference value between the voltage of the first node and the voltage of the positive electrode of the bus is A, and A is more than or equal to 30V and less than or equal to 100V;
the difference value between the voltage of the negative electrode of the bus and the voltage of the second node is B, and B is more than or equal to 30V and less than or equal to 100V;
wherein the first node is a connection point of a cathode of the third diode, a first end of the first capacitor, and an input end of the fifth switching module;
the second node is a connection point of an anode of the fifth diode, a first end of the third capacitor, and an output end of the sixth switching module.
Further, the first switch module, the second switch module, the third switch module, the fourth switch module, the fifth switch module and the sixth switch module all include a switch tube and a diode connected in parallel with the switch tube.
Further, the first diode, the second diode, the third diode, the fourth diode, the fifth diode, and the sixth diode are all fast recovery diodes.
Further, the switch tube comprises a field effect transistor or an insulated gate bipolar transistor.
In a second aspect, embodiments of the present invention further provide a single-phase inverter, which includes the three-level topology circuit of the first aspect.
In a third aspect, the embodiment of the present invention further provides a three-phase inverter, which includes the three-level topology circuit of the first aspect.
The three-level topology circuit provided by the embodiment of the invention comprises a bus anode, a first inductor, a first switch module, a second switch module, a first diode, a second inductor, a third switch module, a fourth switch module, a second diode, a neutral point and a bus cathode, wherein a first end of the first inductor is electrically connected with the bus anode, and a second end of the first inductor is electrically connected with an input end of the first switch module; the output end of the first switch module is electrically connected with the input end of the second switch module; the output end of the second switch module is electrically connected with the second inductor; the anode of the first diode is electrically connected with the neutral point, and the cathode of the diode is electrically connected with the input end of the second switch module; the first end of the third inductor is electrically connected with the negative electrode of the bus, and the second end of the third inductor is electrically connected with the output end of the fourth switch module; the input end of the fourth switch module is electrically connected with the output end of the third switch module; the input end of the third switching module is electrically connected with the second inductor; the positive electrode of the second diode is electrically connected with the output end of the third switch module, the negative electrode of the second diode is electrically connected with the midpoint of the bus, and by arranging the first inductor and the third inductor, because the currents on the first inductor and the third inductor can not be suddenly changed, the current rising edge of the first switch module, the voltage falling edge at two ends of the first switch module and the current rising edge of the fourth switch module are staggered with the voltage falling edge at two ends of the fourth switch module, and the reverse recovery currents of the first diode and the second diode are reduced at the same time, so that the problems that the soft switch circuit is difficult to apply in an inverter, other circuits are difficult to borrow, the requirement on circuit topology is high, a large number of peripheral circuits are required to be added for realizing the soft switch in a part of circuits, and the complexity and fault points of the circuit are increased by adding a large number of peripheral circuits are solved, the soft start of the first switch module and the fourth switch module can be achieved by using less peripheral circuits in the inverter, and meanwhile, the reverse recovery loss of the first diode and the second diode in the inverter is reduced, the current utilization rate in the switch modules is increased, and therefore the conversion efficiency of the inverter is improved.
Drawings
Fig. 1 is a schematic structural diagram of a three-level topology circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a three-level topology circuit according to a second embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a schematic structural diagram of a three-level topology circuit according to a first embodiment of the present invention, as shown in fig. 1, the three-level topology circuit includes a BUS positive BUS +, a first inductor L1, a first switch module T1, a second switch module T2, a first diode D1, a second inductor L2, a third inductor L3, a third switch module T3, a fourth switch module T4, a second diode D2, a neutral point BUS _0, and a BUS negative BUS-; a first end of the first inductor L1 is electrically connected to the BUS positive BUS +, and a second end of the first inductor L1 is electrically connected to the input terminal of the first switch module T1; the output end of the first switch module T1 is electrically connected with the input end of the second switch module T2; the output terminal of the second switching module T2 is electrically connected to the second inductor L2; the anode of the first diode D1 is electrically connected with the neutral point BUS _0, and the cathode of the first diode D1 is electrically connected with the input end of the second switch module T2; a first end of the third inductor L3 is electrically connected with the BUS negative BUS-, and a second end of the third inductor L3 is electrically connected with the input end of the fourth switch module T4; an input end of the fourth switching module T4 is electrically connected with an input end of the third switching module T3; an input terminal of the third switching module T4 is electrically connected to the second inductor L2; the anode of the second diode D2 is electrically connected to the output terminal of the third switching module T3, and the cathode of the second diode D2 is electrically connected to the BUS midpoint BUS _ 0.
It should be noted that in this embodiment, the input terminal of the switch module includes a power input terminal such as a collector or a drain of the switch module, and the output terminal of the switch module includes a power output terminal such as an emitter or a source of the switch module.
The first diode D1 and the second diode D2 play a role of clamping in the present embodiment. When the power flow of the inverter flows in the forward direction, the inverter is converted from direct current into alternating current, the first switch module T1 and the third switch module T3 alternately wave, the second switch module T2 is normally open, the fourth switch module T4 is normally closed, and the circuit comprises two branches, namely a branch consisting of a BUS positive electrode BUS +, a first inductor L1, a first switch module T1, a second switch module T2 and a second inductor L2, and a branch consisting of a neutral point BUS _0, a first diode D1, a second switch module T2 and a second inductor L2. When the first switch module T1 is turned on, the current flowing out from the BUS bar positive electrode BUS + sequentially passes through the first inductor L1, the first switch module T1 and the second switch module T2 to reach the second inductor L2, when the first switch module T1 is turned off, the current flowing out from the neutral point BUS _0 sequentially passes through the first diode D1 and the second switch module T2 to reach the second inductor L2, so when the first switch module T1 is turned on from off, the current flowing through the first diode D1 commutates to the first switch module T1, the current flowing through the first switch module T1 starts to rise, because the induction generated by the first inductor L1 may obstruct the change of the current, the voltage rise may not cause the current to increase immediately, on the contrary, the voltage fall may not cause the current to decrease immediately, that is, the current on the first inductor L1 may not abruptly change, thereby the rising rate of the current of the first switch module T1 may be slowed down, the rising edge of the current of the first switch module T1 and the falling edge of the voltage at the two ends of the first switch module T1 are staggered, so that the turn-on loss of the first switch module T1 is reduced, and meanwhile, when the reverse voltage is suddenly applied to the first diode D1, because a large number of carriers exist during the turn-on, the large number of carriers can reversely flow under the reverse voltage, so that a large reverse recovery current is generated until the residual carriers are consumed.
It should be noted that the fourth switch module T4 and the first switch module T1 are mirror images, the operation principle of the fourth switch module T3 is the same as that of the first switch module T1, and in order to avoid repetition, the operation principle of the fourth switch module T4 is not described herein again.
The three-level topology circuit provided by the embodiment comprises a bus anode, a first inductor, a first switch module, a second switch module, a first diode, a second inductor, a third switch module, a fourth switch module, a second diode, a neutral point and a bus cathode, wherein a first end of the first inductor is electrically connected with the bus anode, and a second end of the first inductor is electrically connected with an input end of the first switch module; the output end of the first switch module is electrically connected with the input end of the second switch module; the output end of the second switch module is electrically connected with the second inductor; the anode of the first diode is electrically connected with the neutral point, and the cathode of the diode is electrically connected with the input end of the second switch module; the first end of the third inductor is electrically connected with the negative electrode of the bus, and the second end of the third inductor is electrically connected with the output end of the fourth switch module; the input end of the fourth switch module is electrically connected with the output end of the third switch module; the input end of the third switching module is electrically connected with the second inductor; the positive electrode of the second diode is electrically connected with the output end of the third switch module, the negative electrode of the second diode is electrically connected with the midpoint of the bus, and by arranging the first inductor and the third inductor, because the currents on the first inductor and the third inductor can not be suddenly changed, the current rising edge of the first switch module, the voltage falling edge at two ends of the first switch module and the current rising edge of the fourth switch module are staggered with the voltage falling edge at two ends of the fourth switch module, and the reverse recovery currents of the first diode and the second diode are reduced at the same time, so that the problems that the soft switch circuit is difficult to apply in an inverter, other circuits are difficult to borrow, the requirement on circuit topology is high, a large number of peripheral circuits are required to be added for realizing the soft switch in a part of circuits, and the complexity and fault points of the circuit are increased by adding a large number of peripheral circuits are solved, the soft start of the first switch module and the fourth switch module can be achieved by using less peripheral circuits in the inverter, and meanwhile, the reverse recovery of the first diode and the second diode in the inverter is reduced, the current utilization rate in the switch modules is improved, and therefore the conversion efficiency of the inverter is improved.
Example two
Fig. 2 is a schematic structural diagram of a three-level topology circuit according to a second embodiment of the present invention, and as shown in fig. 2, the three-level topology circuit in this embodiment further includes a third diode D3, a first capacitor C1, a fifth switch module T5, a fourth diode D4, a fourth inductor L4, a second capacitor C2, a fifth diode D5, a third capacitor C3, a sixth switch module T6, a sixth diode D6, a fifth inductor L5, and a fourth capacitor C4 in addition to the three-level topology circuit in the first embodiment; an anode of the third diode D3 is electrically connected to the second end of the first inductor L1, and a cathode of the third diode D3 is electrically connected to the first end of the first capacitor C1; a second terminal of the first capacitor C1 is electrically connected to the neutral point BUS _ 0; an input terminal of the fifth switching module T5 is electrically connected to a first terminal of the first capacitor C1, and an output terminal of the fifth switching module T5 is electrically connected to a first terminal of the fourth inductor L4; a second end of the fourth inductor L4 is electrically connected with a first end of a second capacitor C2; the anode of the fourth diode D4 is electrically connected to the neutral point BUS _0, and the cathode of the fourth diode D4 is electrically connected to the first end of the fourth inductor L4; a cathode of the fifth diode D5 is electrically connected to the second end of the third inductor L3, and an anode of the fifth diode D5 is electrically connected to the first end of the third capacitor C3; a second terminal of the third capacitor C3 is electrically connected to the neutral point BUS _ 0; an input terminal of the sixth switching module T6 is electrically connected to a first terminal of the fifth inductor L5, and an output terminal of the sixth switching module T6 is electrically connected to a first terminal of the third capacitor C3; an anode of the sixth diode D6 is electrically connected to the first end of the fifth inductor L5, and a cathode of the sixth diode D6 is electrically connected to the neutral point BUS _ 0; a second end of the fifth inductor L5 is electrically connected with a first end of the fourth capacitor C4; a second terminal of the fourth capacitor C4 is electrically connected to the neutral point BUS _ 0.
Among them, the third diode D3 and the fifth diode D5 play a role of freewheeling and clamping in the present embodiment, and the fourth diode D4 and the sixth diode D6 play a role of freewheeling in the present embodiment. When the first switch module T1 is turned off, the current in the first inductor L1 can freewheel through the third diode D3, and at the same time, the third diode D3 can clamp the turn-off voltage of the first switch module T1 to the first capacitor C1, and at the same time, the first BUCK circuit composed of the fifth switch module T5, the fourth diode D4, and the fourth inductor L4 transfers the energy in the first capacitor C1 to the second capacitor C2, so that the energy is fed back to the bus for recycling, and the BUCK circuit operates in a discontinuous current state, and presents a constant resistance state, so that the voltage in the first capacitor C1 is kept constant. Similarly, when the fourth switch module T4 is turned off, the current flowing through the third inductor L3 can freewheel through the fifth diode D5, and at the same time, the fifth diode D5 can clamp the turn-off voltage of the fourth switch module T4 to the third capacitor C3, and at the same time, the second BUCK circuit formed by the sixth switch module T6, the sixth diode D6 and the fifth inductor L5 transfers the energy of the third capacitor C3 to the fourth capacitor C4, so that the energy is fed back to the bus bar for recycling. According to the technical scheme, the turn-off voltage of the first switch module T1 is clamped to the first capacitor C1, then the energy on the first capacitor C1 is transferred to the second capacitor C2 through the first BUCK circuit, so that the part of energy is fed back to the bus to be recycled, the turn-off voltage of the fourth switch module T4 is clamped to the third capacitor C3, then the energy on the third capacitor C3 is transferred to the fourth capacitor C4 through the second BUCK circuit, so that the part of energy is fed back to the bus to be recycled, and the energy utilization rate in the three-level topology circuit can be improved.
On the basis of the technical scheme, optionally, the difference value between the voltage of the first node BUS + _ A and the voltage of the BUS positive electrode BUS + is A, and A is more than or equal to 30V and less than or equal to 100V; the difference value of the voltage of the BUS negative electrode BUS-and the voltage of the second node BUS-A is B, and B is more than or equal to 30V and less than or equal to 100V; the first node BUS + _ A is a connection point of a negative electrode of the third diode, a first end of the first capacitor and an input end of the fifth switch module; the second node BUS- _ A is a connection point of the anode of the fifth diode, the first end of the third capacitor and the output end of the sixth switching module.
The difference between the voltage of the first node BUS + _ A and the voltage of the BUS anode BUS + is A, A is more than or equal to 30V and less than or equal to 100V, illustratively, the voltage of the BUS anode BUS + is 750V, the voltage of the first node BUS + _ A is 800V, and the difference between the voltage of the first node BUS + _ A and the voltage of the BUS anode BUS + is 50V. The voltage difference between the BUS negative electrode BUS-and the second node BUS- _ A is B, 30V is larger than or equal to B and smaller than or equal to 100V, illustratively, the voltage of the BUS negative electrode BUS-is-750V, the voltage at the second node BUS- _ A is-800V, and the voltage difference between the BUS negative electrode BUS-and the second node BUS- _ A is 50V. Since the difference between the voltage at the first node BUS + _ A and the voltage of the BUS bar positive BUS + affects the efficiency with which the first BUCK circuit transfers the energy on the first capacitor C1 into the second capacitor C2, i.e. the greater the difference between the voltage at the first node BUS + _ A and the voltage of the BUS bar positive BUS +, the higher the efficiency with which the first BUCK circuit transfers the energy on the first capacitor C1 into the second capacitor C2, and the difference between the voltage at the second node BUS- _ A and the voltage of the BUS bar negative BUS-affects the efficiency with which the second BUCK circuit transfers the energy on the third capacitor C3 into the fourth capacitor C4, i.e. the greater the difference between the voltage at the second node BUS- _ A and the voltage of the BUS bar negative BUS-, the higher the efficiency with which the second BUCK circuit transfers the energy on the third capacitor C3 into the fourth capacitor C4. So when the voltage at the first node BUS + _ a is higher than the voltage of the BUS positive BUS +, the voltage at the second node BUS- _ a is lower than the voltage of the BUS negative BUS-, the first BUCK circuit transfers the energy on the first capacitor C1 into the second capacitor C2 at a switching frequency doubled to the first switching module T1, and the second BUCK circuit transfers the energy on the third capacitor C3 into the fourth capacitor C4 at a switching frequency doubled to the fourth switching module T4. If the frequency of the first BUCK circuit is lower than the switching frequency of the first switch module T1, the energy generated in the first capacitor C1 is not ready to be transferred to the second capacitor C2, the voltage of the first capacitor C1 will be higher, and similarly, the voltage of the third capacitor C3 will be higher, and the withstand voltages of the first capacitor C1 and the third capacitor C3 cannot be too high, so that the voltage at the first node BUS + _ a and the voltage at the second node BUS _aalso need to be limited.
Based on the above technical solution, optionally, with reference to fig. 2, the first switch module T1, the second switch module T2, the third switch module T3, the fourth switch module T4, the fifth switch module T5, and the sixth switch module T6 each include a switch tube and a diode connected in parallel with the switch tube.
When the power flow of the inverter flows reversely, the inverter is converted from alternating current to direct current, the first switch module T1 and the third switch module T3 alternately wave, the second switch module T2 is normally open, the fourth switch module T4 is normally closed, and the circuit comprises two branches, namely a branch consisting of a second inductor L2, a diode in the second switch module T2, a diode in the first switch module T1, a branch consisting of the first inductor L1 and a BUS positive electrode BUS +, and a branch consisting of the second inductor L2, the third switch module T3, the second diode D2 and a neutral point BUS _ 0. When the third switching module T3 is turned off, the current flowing out from the second inductor L2 sequentially passes through the diode in the second switching module T2, the diode in the first switching module T1, the first inductor L1 to the BUS bar positive electrode BUS +, when the third switching module T3 is turned on, the current flowing out from the second inductor L2 sequentially passes through the third switching module T3, the second diode D2 to the neutral point BUS _0, so when the third switching module T3 is turned on from off, the current flowing through the diode in the second switching module T2, the diode in the first switching module T1 commutates to the third switching module T3 and the second diode D2, the diode in the first switching module T1 and the diode in the second switching module T2 generate a large reverse recovery loss, and at this time, since the current on the first inductor L1 may not abruptly change, the reverse voltages of the diode in the first switching module T1 and the diode in the second switching module T2 may not suddenly change, the reverse recovery loss of the diode in the first switch module T1 and the diode in the second switch module T2 may be reduced, thereby improving the conversion efficiency of the inverter.
On the basis of the above technical solution, optionally, the first diode D1, the second diode D2, the third diode D3, the fourth diode D4, the fifth diode D5, and the sixth diode D6 are all fast recovery diodes.
Based on the above technical solution, optionally, the switching tubes in the first switch module T1, the second switch module T2, the third switch module T3, the fourth switch module T4, the fifth switch module T5 and the sixth switch module T6 may be any one of field effect transistors or insulated gate bipolar transistors, and when the switching tubes in the first switch module T1, the second switch module T2, the third switch module T3, the fourth switch module T4, the fifth switch module T5 and the sixth switch module T6 are insulated gate bipolar transistors, specifically, the emitters of the insulated gate bipolar transistors are connected to the anodes of the diodes connected in parallel with the switching tubes, and the collectors of the insulated gate bipolar transistors are connected to the cathodes of the diodes connected in parallel with the switching tubes.
EXAMPLE III
The third embodiment of the invention provides a single-phase inverter, and the single-phase inverter comprises the first embodiment and the second embodiment of the invention which provide a three-level topological circuit, the three-level topological circuit reduces the loss of a switching tube, improves the current utilization rate of the switching tube, and simultaneously improves the conversion efficiency of the single-phase inverter.
The third embodiment of the invention also provides a three-phase inverter, and the three-phase inverter comprises the first embodiment and the second embodiment of the invention which provide a three-level topological circuit, the three-level topological circuit reduces the loss of a switching tube, improves the current utilization rate of the switching tube, and simultaneously improves the conversion efficiency of the three-phase inverter.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (7)

1. A three-level topological circuit is characterized by comprising a bus anode, a first inductor, a first switch module, a second switch module, a first diode, a second inductor, a third switch module, a fourth switch module, a second diode, a neutral point and a bus cathode;
the first end of the first inductor is electrically connected with the positive electrode of the bus, and the second end of the first inductor is electrically connected with the input end of the first switch module;
the output end of the first switch module is electrically connected with the input end of the second switch module;
the output end of the second switch module is electrically connected with the second inductor;
the anode of the first diode is electrically connected with the neutral point, and the cathode of the first diode is electrically connected with the input end of the second switch module;
a first end of the third inductor is electrically connected with the negative pole of the bus, and a second end of the third inductor is electrically connected with an output end of the fourth switch module;
the input end of the fourth switch module is electrically connected with the output end of the third switch module;
the input end of the third switching module is electrically connected with the second inductor;
the anode of the second diode is electrically connected with the output end of the third switch module, and the cathode of the second diode is electrically connected with the neutral point;
the circuit also comprises a third diode, a first capacitor, a fifth switch module, a fourth diode, a fourth inductor, a second capacitor, a fifth diode, a third capacitor, a sixth switch module, a sixth diode, a fifth inductor and a fourth capacitor;
an anode of the third diode is electrically connected to the second end of the first inductor, and a cathode of the third diode is electrically connected to the first end of the first capacitor;
a second terminal of the first capacitor is electrically connected to the neutral point;
an input end of the fifth switching module is electrically connected with a first end of the first capacitor, and an output end of the fifth switching module is electrically connected with a first end of the fourth inductor;
a second end of the fourth inductor is electrically connected with a first end of the second capacitor;
a second terminal of the second capacitor is electrically connected to the neutral point;
the anode of the fourth diode is electrically connected with the neutral point, and the cathode of the fourth diode is electrically connected with the first end of the fourth inductor;
a cathode of the fifth diode is electrically connected with the second end of the third inductor, and an anode of the fifth diode is electrically connected with the first end of the third capacitor;
a second terminal of the third capacitor is electrically connected to the neutral point;
an input end of the sixth switching module is electrically connected with a first end of the fifth inductor, and an output end of the sixth switching module is electrically connected with a first end of the third capacitor;
the anode of the sixth diode is electrically connected with the first end of the fifth inductor, and the cathode of the sixth diode is electrically connected with the neutral point;
a second end of the fifth inductor is electrically connected with a first end of the fourth capacitor;
a second terminal of the fourth capacitor is electrically connected to the neutral point.
2. The three-level topology circuit of claim 1, wherein the difference between the voltage of the first node and the voltage of the positive pole of the bus is a, 30V ≦ a ≦ 100V;
the difference value between the voltage of the negative electrode of the bus and the voltage of the second node is B, and B is more than or equal to 30V and less than or equal to 100V;
wherein the first node is a connection point of a cathode of the third diode, a first end of the first capacitor, and an input end of the fifth switching module;
the second node is a connection point of an anode of the fifth diode, a first end of the third capacitor, and an output end of the sixth switching module.
3. The three-level topology circuit of claim 2, wherein the first, second, third, fourth, fifth, and sixth switching modules each comprise a switching tube and a diode in parallel with the switching tube.
4. The three-level topology circuit of claim 1, wherein the first diode, the second diode, the third diode, the fourth diode, the fifth diode, and the sixth diode are fast recovery diodes.
5. The three-level topology circuit of claim 1, wherein the switching transistor comprises a field effect transistor or an insulated gate bipolar transistor.
6. A single-phase inverter comprising the three-level topology circuit of any one of claims 1 to 5.
7. A three-phase inverter comprising the three-level topology circuit of any one of claims 1 to 5.
CN201811645639.XA 2018-12-30 2018-12-30 Three-level topological circuit, single-phase inverter and three-phase inverter Active CN109378987B (en)

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CN102611342B (en) * 2012-03-13 2014-10-08 华为技术有限公司 three-level inverter
CN102684532B (en) * 2012-04-23 2015-05-27 华为技术有限公司 Three-level inverter
CN102946205A (en) * 2012-10-29 2013-02-27 华为技术有限公司 Three-level inverter and power supply equipment
CN104218832B (en) * 2013-05-30 2016-12-28 阳光电源股份有限公司 A kind of single-phase five level topology and inverters
CN204216795U (en) * 2014-11-28 2015-03-18 东南大学 For the elementary cell of multi-level converter, three level and m level topological structure
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