CN109359486B - Encryption and decryption system and operation method thereof - Google Patents
Encryption and decryption system and operation method thereof Download PDFInfo
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Abstract
The invention discloses an encryption and decryption system and an operation method thereof; the cipher key chip comprises a cipher key chip, a cipher text chip, a random number generator and a peripheral circuit, wherein the peripheral circuit consists of a controller, a read-write circuit, a signal amplifier and an address coding circuit. Before encryption, the random number generator generates a random signal to be written into the key chip. During encryption, plaintext data is written into a ciphertext chip, then the plaintext data is associated with part of unit addresses serving as keys in a key chip, and a key signal is applied to a plaintext data unit to perform encryption calculation, so that data encryption is completed. And during decryption, reading the key in the key chip, and performing decryption calculation with the ciphertext in the ciphertext chip to finish data decryption. In the whole process, the key chip is always in an off-line state. The invention takes the resistance state as the key, encrypts the plaintext data on the basis of hardware, covers the original data, stores the key off line, improves the safety of information storage and saves power consumption and time delay.
Description
Technical Field
The invention belongs to the field of information security, and particularly relates to an encryption and decryption system and an operation method thereof.
Background
Encryption and decryption of data have important applications in the information age. The encryption process refers to encoding plaintext data by an encoding means, a method used in the encoding process is a secret key, and the encoded data is ciphertext data. The decryption process is the inverse operation of the encryption process, the ciphertext is decoded through the key, and the output is the plaintext. In the encryption and decryption processes, the key must be unique and can be repeated, otherwise, the ciphertext can be cracked easily or cannot be cracked at all, and thus the original data cannot be obtained. The key is the key to the whole encryption and decryption process, and therefore, its security determines how easy the ciphertext is to be cracked.
The traditional encryption method is designed as proposed in the invention patent of China (application number: CN108347335A) of login verification method and system based on SM3 algorithm and random challenge code, so that the international algorithms widely used at present, such as MD5, are optimized, and the number of bits of summary information and login challenge code are increased. The design is an encryption process based on a data algorithm and carried out on a software level, although the prior art is improved, the design is based on the algorithm, and is easy to monitor and further cracked; moreover, although the complicated operation steps increase the security, the whole system consumes a large amount of power consumption, operation time and storage space; in addition, the memory for storing the original data is violently cracked, and the data in the memory can be obtained by directly avoiding the encryption and decryption algorithm. Therefore, the encryption process based on the data algorithm still has the problems of low security and low energy efficiency.
Disclosure of Invention
In view of the defects of the prior art, the present invention aims to provide an encryption and decryption system and an operation method thereof, which aims to improve the problems of low security and low energy efficiency in the encryption method based on the data algorithm.
The invention provides an encryption and decryption system, comprising: the cipher key comprises a key chip, a cipher text chip, a random number generator and a peripheral circuit; the random number generator is used for randomly generating a series of binary codes according to an instruction; the peripheral circuit is connected with the key chip and the ciphertext chip and used for reading the key data in the key chip and performing logic operation on the plaintext data in the ciphertext chip to generate a ciphertext, namely, data encryption is realized.
Furthermore, the key chip and the ciphertext chip have the same structure, and both include: the device comprises a resistive cross bar array consisting of N resistive units and N transistors and an address selection circuit corresponding to the array, wherein each resistive unit in the array is connected with one transistor in series; the grid electrode of the transistor is connected with a Selection Line (SL), the source electrode of the transistor is connected with a Word Line (WL), the drain electrode of the transistor is connected with the anode of the resistance changing unit, and the cathode of the resistance changing unit is connected with a Bit Line (BL).
All the resistive units and the transistors are made of the same material and have the same parameters.
When positive voltage pulses exceeding a first threshold value are applied to the two ends of the positive electrode and the negative electrode of the resistance change unit, the resistance change unit is changed into a low resistance state; when negative voltage pulses exceeding a second threshold value are applied to the two ends of the positive electrode and the negative electrode of the resistance change unit, the resistance change unit is changed into a high resistance state; the low resistance state of the resistance change unit is recorded as a logic value 1, and the high resistance state of the resistance change unit is recorded as a logic value 0.
Further, the peripheral circuit includes: the cipher text encryption and decryption device comprises a controller, a secret key read-write circuit, a cipher text read-write circuit, a signal amplifier and an address coding circuit; a first input end of the key read-write circuit is connected to an output end of the random number generator, a second input end of the key read-write circuit is connected to a first output end of the controller, and an output end of the key read-write circuit is connected to a first input end of the key chip; the first input end of the ciphertext read-write circuit is connected to the first output end of the signal amplifier, the second input end of the ciphertext read-write circuit is connected to the second output end of the controller, and the output end of the ciphertext read-write circuit is connected to the first input end of the ciphertext chip; the first input end of the signal amplifier is connected to the output end of the key chip, and the first input end of the signal amplifier is connected to the third output end of the controller; the input end of the address coding circuit is connected to the second output end of the signal amplifier, the first output end of the address coding circuit is connected to the second input end of the key chip, and the second output end of the address coding circuit is connected to the second input end of the ciphertext chip; the controller is used for providing various operating voltages for the key read-write circuit, the ciphertext read-write circuit, the signal amplifier and the address coding circuit; the key reading and writing circuit is used for reading or writing data in the key chip; the ciphertext read-write circuit is used for reading or writing data in the ciphertext chip; the signal amplifier is used for converting the current signal read from the key chip into a voltage signal meeting the requirement; the address coding circuit is used for associating and coding the addresses of the units in the key chip and the ciphertext chip.
The invention also provides an operation method based on the encryption and decryption system, which can execute the data encryption function and comprises the following steps:
s11: generating a random pulse sequence by the random number generator, and controlling the key read-write circuit to write random data into the key chip by the controller;
s12: the controller controls the ciphertext read-write circuit to write plaintext data into the ciphertext chip;
s13: the address of plaintext data in the ciphertext chip is associated with the address of part of data in the key chip through the address coding circuit, and the part of data is a key;
s14: and reading the key data in the key chip, and performing logic operation on the plaintext data in the ciphertext chip through the signal amplifier and the ciphertext read-write circuit to generate a ciphertext, namely realizing data encryption.
Wherein the logical operation is XOR logic.
The invention also provides an operation method based on the encryption and decryption system, which can execute the data decryption function and comprises the following steps:
s21: selecting a key in the key chip corresponding to a ciphertext data address in the ciphertext chip through the address coding circuit;
s22: and reading the key data in the key chip, and performing logic operation on the ciphertext in the ciphertext chip through the signal amplifier and the ciphertext read-write circuit to generate plaintext data, namely realizing data decryption.
Wherein, the bit number of partial data in the key chip is customized by a user.
The cache region in the address coding circuit is used for storing information related to the key address in the key chip and the ciphertext address in the ciphertext chip.
Compared with the prior art, the technical scheme of the invention has the advantages that the key can be stored for a long time due to the fact that the resistance state of the device is used as the key; the safety of key storage is enhanced by the characteristics of random generation and offline key storage; on the basis of hardware, by means of an encryption and decryption mode integrating storage and logic operation, power consumption and time delay are saved, the ciphertext is prevented from being cracked violently, and the safety of information storage is improved.
Drawings
FIG. 1 is a schematic view of a current-voltage characteristic curve of a resistive switching device;
FIG. 2 is a schematic diagram of an encryption and decryption system;
FIG. 3 is a schematic structural diagram of a resistance change unit chip;
FIG. 4 is a schematic diagram of a data encryption process;
FIG. 5 is a schematic diagram of a data decryption process;
FIG. 6 is a schematic diagram of a signal amplifier circuit;
FIG. 7 is a schematic diagram of the XOR logic operation;
FIG. 8 is a diagram of the XOR logical true values;
fig. 9 shows a first embodiment of the present invention: the encryption operation schematic diagram of the data;
fig. 10 shows a second embodiment of the present invention: the operation of decrypting data is schematically shown.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Before the technical scheme of the invention is introduced, some characteristics of the resistive switching device are introduced first, and fig. 1 is a schematic view of a volt-ampere characteristic curve of a bipolar resistive switching device. As can be seen from the graph, when the forward voltage applied across the resistive switching device is greater than or equal to the first threshold, e.g., VSetThe device changes from a high resistance state to a low resistance state; when the negative voltage applied to the resistive switching device is less than or equal to a second threshold, e.g., VResetThe device changes from the low resistance state to the high resistance state.
Based on the characteristics of the resistance change device, the resistance state of the resistance change device is controlled by controlling the voltage at two ends of the resistance change device, and binary data '0' and '1' are written in through the change of the resistance state of the resistance change device. For example, when the resistance change device is low-resistance, data 1 is written; when the resistance change device is high-resistance, data 0 is written. Of course, when the resistance change device is low resistance, data 0 may be written; when the resistance change device is high-resistance, data 1 is written. In the invention, the high resistance state of the resistance change device is recorded as logic 0, and the low resistance state is recorded as logic 1.
FIG. 1 also showsGoes out of the read voltage VReadSize of (V)ReadThe voltage amplitude is far smaller than the first threshold and the second threshold, and the resistance state of the resistance change device cannot be greatly influenced.
Fig. 2 is a schematic diagram of an encryption and decryption system of the present invention, which specifically includes: the cipher key chip comprises a cipher key chip, a cipher text chip, a random number generator and a peripheral circuit, wherein the peripheral circuit consists of a controller, a cipher key read-write circuit, a cipher text read-write circuit, a signal amplifier and an address coding circuit. The output end of the random number generator is connected with the input end of the key read-write circuit, the output end of the key read-write circuit is connected with the key chip, the key chip is connected with the input end of the signal amplifier, the output end of the signal amplifier is connected with the input end of the ciphertext read-write circuit, and the output end of the ciphertext read-write circuit is connected with the ciphertext chip. The output end of the controller is connected with the input ends of the key read-write circuit, the ciphertext read-write circuit and the address coding circuit, and the output end of the address coding circuit is connected with the key chip and the ciphertext chip.
The random number generator can randomly generate a series of binary codes according to the instruction;
the controller provides various operating voltages for the read-write circuit, the signal amplifier and the address coding circuit;
the key reading and writing circuit is used for reading or writing data in the key chip;
the ciphertext read-write circuit is used for reading or writing data in the ciphertext chip;
the signal amplifier is connected with the key chip and the ciphertext read-write circuit and has the function of converting the current signal read from the key chip into a voltage signal meeting the requirement;
the address coding circuit associates and codes the addresses of the units in the key chip and the ciphertext chip.
Fig. 3 is a schematic diagram of a chip structure of a resistive switching unit, which specifically includes a resistive switching crossbar array and a corresponding on-chip address selection circuit. In the resistive cross bar array, each resistive unit is connected with a transistor in series, the grid electrode of the transistor is connected with a Selection Line (SL), the source electrode of the transistor is connected with a Word Line (WL), the drain electrode of the transistor is connected with the anode of the resistive unit, and the cathode of the resistive unit is connected with a Bit Line (BL). And the materials and parameters of all the resistance change units and the transistors are consistent.
When positive voltage pulses exceeding a first threshold value are applied to the two ends of the positive electrode and the negative electrode of the resistance change unit, the resistance change unit is changed into a low resistance state; when negative voltage pulses exceeding a second threshold value are applied to the two ends of the positive electrode and the negative electrode of the resistance change unit, the resistance change unit is changed into a high resistance state. And recording the low resistance state of the resistance change unit as a logic value 1, and recording the high resistance state of the resistance change unit as a logic value 0. The first threshold and the second threshold are intrinsic parameters of the resistive switching unit, and the thresholds corresponding to different resistive switching units are different, and after the resistive switching units are determined, a person skilled in the art can measure the thresholds according to a method provided in the prior art. Fig. 4 is a schematic diagram of an encryption operation flow based on the system structure, which specifically includes the following operation steps:
s101: the random number generator generates a binary code;
s102: writing the binary code data into the key chip;
s103: writing the plaintext data into the ciphertext chip;
s104: associating the address of the plaintext data in the ciphertext chip with the address of the user-defined data in the key chip; the part of data defined by the user is the key data;
s105: carrying out XOR logical operation on the key data in the key chip and the plaintext data in the ciphertext chip;
s106: and finishing data encryption after all data are calculated.
Fig. 5 is a schematic diagram of a decryption operation flow based on the system structure, which specifically includes the following operation steps:
s201: reading key data in the key chip;
s202: carrying out XOR logical operation on the key data and the ciphertext data in the ciphertext chip;
s203: and finishing the data decryption after all the data are calculated.
Fig. 6 is a schematic diagram of a signal amplifier. The result of reading part of the data from the key chip is represented by the current IINIs input and can be obtained according to circuit knowledgeVOUT＝IINThe resistance values of R and R are far larger than the low resistance state of the resistive device, and the specific resistance values can be determined according to actual conditions.
When the data stored in the unit in the key chip is 1, the unit is in a low resistance state, the read current is large, and therefore VOUTThe high level is marked as logic 1; when the data stored in the unit in the key chip is 0, the unit is in a high-impedance state, the read current is small, and therefore V isOUTThe low level is marked as logic 0; in summary, the signal amplifier converts the current input into a corresponding voltage output;
FIG. 7 is a schematic diagram of the XOR logic operation. For convenience of description, the key data in the key chip is p, and the plaintext data/ciphertext data in the ciphertext chip is q. For the resistance change unit, p and q variables are expressed in the form of resistance states; for the ports of the transistor gate, source and resistive cell cathode, the p and q variables are represented in the form of voltages.
When the data in the ciphertext chip is 0, namely q is 0, if p is 0, the gate voltage is less than the transistor starting voltage, the transistor is pinched off, the resistance state of the resistance change unit cannot be changed, and the calculation result is 0; if p is 1, the gate voltage is greater than the transistor turn-on voltage, the transistor is turned on, and at this time, the positive electrode of the resistive switching unit is at a high level and the negative electrode of the resistive switching unit is at a low level, so that the resistive switching unit is in a low resistance state, and the calculation result is 1. When the data in the chip B is 1, that is, q is equal to 1, if p is equal to 0, the gate voltage is less than the transistor turn-on voltage, the transistor is pinched off, the resistance state of the resistance change unit does not change, and the calculation result is 1; if p is 1, the gate voltage is greater than the transistor starting voltage, the transistor is turned on, at this time, the positive electrode of the resistive switching unit is at a low level, the negative electrode of the resistive switching unit is at a high level, so that the resistive switching unit is in a high-resistance state, and the calculation result is 0;
FIG. 8 is a diagram of the XOR logical true values;
fig. 9 shows a first embodiment of the present invention: the encryption operation of data is schematically shown. The random number generator generates a binary code of "10101001" and has been written into the key chip. The plaintext '01011010' has been written in the ciphertext chip. The user selects the first 4 bits of data in the key chip as a key, and associates the address of the 8 bits of data in the ciphertext chip with the address of the key data in the key chip, namely the key data in the key chip is '1010'.
During encryption, firstly, XOR logical operation is carried out on the key '1010' and the previous 4-bit data '0101' in the ciphertext chip, the calculation result is '1111', plaintext data are covered, and the plaintext data are directly stored in the ciphertext chip; then, XOR logical operation is carried out on the key '1010' and the later 4-bit data '1010' in the ciphertext chip, the calculation result is '0000', and plaintext data are covered and directly stored in the ciphertext chip. The '11110000' is the cipher text, and the encryption process is finished;
fig. 10 shows a second embodiment of the present invention: the operation of decrypting data is schematically shown. The address coding circuit firstly determines the key address corresponding to the ciphertext '11110000' in the ciphertext chip to obtain the key '1010'.
During decryption, firstly, XOR logical operation is carried out on the key '1010' and the first 4-bit data '1111' in the ciphertext chip, the calculation result is '0101', the ciphertext data are covered, and the ciphertext data are directly stored in the ciphertext chip; then, XOR logical operation is carried out on the key '1010' and the later 4-bit data '0000' in the ciphertext chip, the calculation result is '1010', and the ciphertext data is covered and directly stored in the ciphertext chip. 01011010 is the plaintext, and the decryption process is completed.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. An encryption and decryption system, comprising: the cipher key comprises a key chip, a cipher text chip, a random number generator and a peripheral circuit;
the random number generator is used for randomly generating a series of binary codes according to an instruction, and the binary codes are written into the key chip;
the key chip and the ciphertext chip have the same structure and both comprise: the device comprises a resistive cross bar array consisting of N resistive units and N transistors and an address selection circuit corresponding to the array, wherein each resistive unit in the array is connected with one transistor in series; the grid electrode of the transistor is connected with the selection line, the source electrode of the transistor is connected with the word line, the drain electrode of the transistor is connected with the anode of the resistance change unit, and the cathode of the resistance change unit is connected with the bit line;
the peripheral circuit is connected with the key chip and the ciphertext chip and is used for reading the key data p in the key chip, converting the key data p into corresponding voltage after reading the key data p and applying the corresponding voltage to the transistor grid of the ciphertext chip; reading the ciphertext/plaintext data q in the ciphertext chip, converting the ciphertext/plaintext data q into corresponding voltage after reading the ciphertext/plaintext data q, applying the voltage to the negative electrode of the resistance change unit of the ciphertext chip, and performing data conversion on the ciphertext/plaintext data q to obtain a data output
Converting the voltage into corresponding voltage, and applying the voltage to a source electrode of the ciphertext chip transistor;
the peripheral circuit comprises a signal amplifier which is used for converting the current signal read in the key chip into a voltage signal which meets the requirement.
2. The encryption and decryption system of claim 1, wherein the resistive elements, the transistors and the materials and parameters are the same.
3. The encryption and decryption system of claim 1, wherein the resistive switching element changes to a low resistance state when a positive voltage pulse exceeding a first threshold is applied across a positive and a negative terminal of the resistive switching element; when negative voltage pulses exceeding a second threshold value are applied to the two ends of the positive electrode and the negative electrode of the resistance change unit, the resistance change unit is changed into a high resistance state; the low resistance state of the resistance change unit is recorded as a logic value 1, and the high resistance state of the resistance change unit is recorded as a logic value 0.
4. The encryption and decryption system of any of claims 1-3, wherein the peripheral circuit further comprises: the device comprises a controller, a key read-write circuit, a ciphertext read-write circuit and an address coding circuit;
a first input end of the key read-write circuit is connected to an output end of the random number generator, a second input end of the key read-write circuit is connected to a first output end of the controller, and an output end of the key read-write circuit is connected to a first input end of the key chip;
the first input end of the ciphertext read-write circuit is connected to the first output end of the signal amplifier, the second input end of the ciphertext read-write circuit is connected to the second output end of the controller, and the output end of the ciphertext read-write circuit is connected to the first input end of the ciphertext chip;
the first input end of the signal amplifier is connected to the output end of the key chip, and the first input end of the signal amplifier is connected to the third output end of the controller;
the input end of the address coding circuit is connected to the second output end of the signal amplifier, the first output end of the address coding circuit is connected to the second input end of the key chip, and the second output end of the address coding circuit is connected to the second input end of the ciphertext chip;
the controller is used for providing various operating voltages for the key read-write circuit, the ciphertext read-write circuit, the signal amplifier and the address coding circuit;
the key reading and writing circuit is used for reading or writing data in the key chip;
the ciphertext read-write circuit is used for reading or writing data in the ciphertext chip;
the address coding circuit is used for associating and coding the addresses of the units in the key chip and the ciphertext chip.
5. A method of operating an encryption and decryption system according to claim 4, wherein the data encryption function is performed, comprising the steps of:
s11: generating a random pulse sequence by the random number generator, and controlling the key read-write circuit to write random data into the key chip by the controller;
s12: the controller controls the ciphertext read-write circuit to write plaintext data into the ciphertext chip;
s13: the address of plaintext data in the ciphertext chip is associated with the address of part of data in the key chip through the address coding circuit, and the part of data is a key;
s14: and reading the key data p in the key chip, and carrying out XOR logical operation on the plaintext data in the ciphertext chip through the signal amplifier and the ciphertext read-write circuit to generate a ciphertext, namely realizing data encryption.
6. A method of operating an encryption and decryption system according to claim 4, wherein the data decryption function is performed, comprising the steps of:
s21: selecting a key in the key chip corresponding to a ciphertext data address in the ciphertext chip through the address coding circuit;
s22: and reading the key data p in the key chip, and carrying out XOR logical operation on the ciphertext in the ciphertext chip through the signal amplifier and the ciphertext read-write circuit to generate plaintext data, namely realizing data decryption.
7. A method of operation as claimed in claim 5 or 6, wherein the number of bits of the partial data in the key chip is user-defined.
8. The method of claim 7, wherein a buffer in the address encoding circuit is configured to store information that associates a key address in the key chip and a ciphertext address in the ciphertext chip.
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| CN201811242297.7A CN109359486B (en) | 2018-10-24 | 2018-10-24 | Encryption and decryption system and operation method thereof |
| PCT/CN2019/095682 WO2020082820A1 (en) | 2018-10-24 | 2019-07-12 | Encryption and decryption system and operation method therefor |
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| CN109359486B (en) * | 2018-10-24 | 2021-07-27 | 华中科技大学 | Encryption and decryption system and operation method thereof |
| CN110298181A (en) * | 2019-05-14 | 2019-10-01 | 北京航空航天大学 | Data encryption storage method, data decryption method and encrypted memory chip |
| CN110989972B (en) * | 2019-12-05 | 2021-11-30 | 清华大学 | Random number generation method and random number generator |
| CN113158203B (en) * | 2021-04-01 | 2024-05-17 | 深圳市纽创信安科技开发有限公司 | SOC chip, circuit and external data read-write method of SOC chip |
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| CN104516834A (en) * | 2013-09-26 | 2015-04-15 | 英特尔公司 | Data storage in persistent memory |
| CN105518786A (en) * | 2013-09-09 | 2016-04-20 | 高通股份有限公司 | Physically unclonable function based on resistivity of magnetoresistive random-access memory magnetic tunnel junctions |
| EP3319265A1 (en) * | 2016-11-08 | 2018-05-09 | Honeywell International Inc. | Configuration based cryptographic key generation |
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| KR101369748B1 (en) * | 2006-12-04 | 2014-03-06 | 삼성전자주식회사 | Method for encrypting datas and appatus therefor |
| CN101001142A (en) * | 2007-01-17 | 2007-07-18 | 张建华 | Encipher-decipher method based on iterative random number generator |
| CN106656475B (en) * | 2017-01-09 | 2020-01-21 | 李朋林 | Novel symmetric key encryption method for high-speed encryption |
| CN109359486B (en) * | 2018-10-24 | 2021-07-27 | 华中科技大学 | Encryption and decryption system and operation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105518786A (en) * | 2013-09-09 | 2016-04-20 | 高通股份有限公司 | Physically unclonable function based on resistivity of magnetoresistive random-access memory magnetic tunnel junctions |
| CN104516834A (en) * | 2013-09-26 | 2015-04-15 | 英特尔公司 | Data storage in persistent memory |
| EP3319265A1 (en) * | 2016-11-08 | 2018-05-09 | Honeywell International Inc. | Configuration based cryptographic key generation |
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