WO2015140365A1

WO2015140365A1 - Method and device for generating identifiers and truly random numbers

Info

Publication number: WO2015140365A1
Application number: PCT/ES2015/000038
Authority: WO
Inventors: Iluminada BATURONE CASTILLO; Susana EIROA LORENZO; Miguel Ángel PRADA DELGADO
Original assignee: Universidad De Sevilla; Consejo Superior De Investigaciones Científicas
Priority date: 2014-03-20
Filing date: 2015-03-19
Publication date: 2015-09-24
Also published as: ES2548792B1; ES2548792A1

Abstract

The invention relates to a method comprising two steps. The first step involves classifying the static memory cells into two discrete sets according to their behaviour towards repeatedly being connected to a power supply after having been with out a power supply for a sufficient period of time, such that the cells of one of the sets are suitable for generating identifiers (key or secret) and the cells of the other set are suitable for generating truly random numbers. Thanks to this classification, in the second step, involving the generation of numbers, the identifiers and the random numbers generated perform better. The invention also relates to a device for carrying out the method according to the invention, said method being carried out by adding very simple circuitry to the memory or running very simple software. The scientific-technical fields of the invention are those of cryptography, electronic technology, security and privacy.

Description

Title

Method and device to generate truly random identifiers and numbers

Object of the invention

The present invention aims at a method consisting of two stages: a first stage of classification of static memory cells into two disjoint assemblies according to their behavior before repeated times when they are connected to power after having been in sufficient time without power, so that the cells of one of the sets are suitable for generating identifiers (keys or secrets) and those of the other are suitable for generating truly random numbers. Thanks to this classification, in the second stage of number generation, the identifiers as well as the random numbers generated offer better performance. The device for implementing the proposed method that can be performed by adding very simple circuitry to memory or by executing very simple software is also object of the invention. The scientific-technical areas to which the invention can correspond are those of Cryptography, Electronic Technology, Security and Privacy.

State of the art

Static memory cells are characterized in that they have two stable states, so that they maintain the binary data (logical value "0" or "1") that is written to them while they are powered, but they lose information if the power is interrupted. If they are fed but they are not written, the cells evolve towards one value or another in a way that is difficult to predict, model mathematically and clone physically, so it is very difficult to obtain a set of cells that behave same form. Taking advantage of these features, these cells have been used to generate truly random circuit identifiers and numbers. Static memory cells consist of cross-coupled circuits, such as latches, flip-flops, ÑOR doors, inverters, etc. In [Kumar2008] cells based on two cross latches are proposed to identify FPGAs. In [Maes2008] it proposes the use of flip-flops to identify FPGAs. In [Su2008], cells based on two OR cross doors are proposed to identify integrated circuits of specific applications. In [Layman2004] a method is proposed that uses cells based on two cross inverters (the typical ones that form the static random access memories, SRAMs) to identify the integrated circuit wafers and / or the dice into which each wafer is divided.

In identification applications, a challenge-response technique is usually used with memory cells to identify the device in which the memory is included, so that the challenge is the cells to be used and the responses are the values to those that stabilize the cells when the power is connected to them [Guajardo2007] [Holcomb2009] [Kim2010] [Gebara2012]. Other methods that combine the responses of the cells have also been proposed. In these applications a registration stage is always necessary in which each device is assigned an identifier, ID. In the identification stage, the distance (usually a Hamming distance, HD) between the ID generated by the device and those registered is calculated and the device is identified as the one whose registered ID has the shortest distance. In authentication applications only one device is registered, so in the authentication stage the distance between the generated and the registered ID is calculated and if the distance is below a threshold, the device is considered authentic, and if not, The device is considered false. The quality of an identification / authentication technique is usually assessed by measuring the reasons of false rejection (FRR, "False Rejection Rate") and false acceptance (FAR, "False Acceptance Rate") for each threshold value chosen. Ideally, there should be at least one threshold value for which there are no authentic devices rejected as false (FRR = 0) and, at the same time, there are no false devices accepted as authentic (FAR = 0). Equally, the percentages of genuine (authentic) and impostor population are also represented against each threshold value chosen. Ideally, both populations are clearly separated.

In identification / authentication applications, it is important that cells always provide the same value. However, there are cells that provide a value in the identification stage other than that assigned to them in the registration stage. There are memory cells that have a clear tendency to stabilize in one value or another and cells that do not have any clear tendency (their initialization value is different each time they are fed). In [Holcomb2009] SRAM cells are classified depending on their voltage transfer curves ("Voltage Transfer Curves" or VTCs) in asymmetric cells ("skewed cells"), which have a greater probability to stabilize in one value than in another, and symmetric cells ("neutral cells"), which do not present any clear tendency to one value or another. One of the reasons why a cell is of one type or another is the variations that have occurred in the memory manufacturing process, which result in the two constituent cross circuits of each cell not being perfectly identical. The cells that are asymmetric for this reason are the most appropriate when generating identifiers because they characterize the intrinsic, unique and unrepeatable nature of memory. But variations in the manufacturing process are not the only reason. The memories present remanence, that is, previous values stored in the cells can influence the future values at which the cells evolve if the time that the memory is off is short. Although this influence can be eliminated if the shutdown time is sufficient (for example a few tens of seconds). On the other hand, in the case of SRAMs, it has been studied that aging and the NBTI (Negative Bias Temperature Instability) effect, a consequence of prolonged use of SRAM, also cause a cell to be asymmetric or symmetric [Guajardo2007] [Holcomb2009 ]. Much more influential than the reason before modifying the behavior of the cells are the operating conditions, especially the temperature. The temperature influences the threshold tensions and the electron-hollow mobility of the CMOS transistors that make up each memory cell, so that a change in temperature can convert an asymmetric cell into symmetric and vice versa [Kim2010] [Gebara2012]. The variations in the supply voltage also influence considerably because they modify the static noise range (Static Noise Margin, SNM) of the cells, making them more or less susceptible to noise [Holcomb2009].

To reduce the problem of cells that provide a value in the identification stage other than that assigned to them in the registration stage, different solutions have been proposed. The proposal in [Holcomb2009] is to average the values at which a given set of SRAM cells are stabilized for a given number of measurements made at the nominal supply temperature and voltage and, based on the average obtained, assign each cell the most likely binary value to form with them the registered identifier. The proposal in [Kim2010] is to generate an identifier as in [Holcomb2009], but not a single identifier obtained under nominal operating conditions, but to generate several identifiers for various operating conditions, mainly for various temperatures. The more IDs you register For each SRAM, one for each temperature, the better the characterization of the SRAM. As a compromise between good characterization and registration stage not too expensive, it is proposed to generate a 10 for the maximum operating temperature, another for the minimum and another for the intermediate value. The proposal in [Gebara2012] extends the work in [Kim2010] and characterizes the memory cells by feeding them with various voltage values (from 0.2Vdd to 1.4Vdd, with Vdd the nominal value) for a time (approximately 1 microsecond) and then adjusting the feed to its nominal value before reading the values at which the cells are stabilized. Several measurements are made at each supply voltage value and for each temperature value. The information that is stored in the registration stage is not only the most likely ID for each temperature, but also the probability of each cell stabilizing at one value or another. They even introduce the possibility of not using memory cells whose values change in different temperature conditions. To measure the distance between the ID generated in the identification stage and the ID stored for each temperature in the registration stage, they introduce a similarity measure that weighs the distance between a generated bit and another stored by the probability recorded for that cell and then merge the results obtained with each ID for each temperature. To implement this technique, a system is proposed that tests the SRAMs included in the integrated circuits at the wafer level. The system for testing the wafers must include a programmable power supply using a computer that sets the supply voltage to the different values (from 0.2Vdd to 1.4Vdd for approximately 1 microsecond) and then adjusting it to the nominal value. In addition, a temperature chamber or a temperature forcing system is also programmable by the computer. This proposal is aimed at semiconductor manufacturers or specialized integrated circuit vendors.

In applications of dynamic construction of keys or secrets, it is also important that the cells always provide the same value. To reduce the problem of cells that do not, public data algorithms (Helper Data Algorithms or HDA) are usually used, among which the best known is the code offset based HDA (Code Offset-based HDA) that , like identification / authentication applications, it has a registration and a secret recovery stage. In the registration phase the following steps are carried out: (a) an answer is obtained, R, from several initialization values of memory cells, (b) a random code word, C, is chosen from a error correction code, (c) se calculates a vector of public data such as W = XOR (C, R) and (d) W is stored. In the secret recovery phase the following steps are carried out: (a) a response is obtained from the memory of the In the same way as in the registration phase, R '(as there are cells that do not always provide the same value, the response R' will not be identical to R, although similar), (b) C = XOR (W, R ') = XOR [XOR (C, R), R'], (c) the error correction code decoding algorithm is applied to C, so that if C is close to C, the decoder recovers C and, therefore therefore, R = XOR (W, C) is recovered. The result of a hash function applied on R can be used as a cryptographic key [Guajardo2007]. The most expensive step of these algorithms is the decoding of the error correction code. The complexity of this decoding is reduced if the percentage of cells that always provide the same value increases.

Cross-coupled circuits have also been used to design truly random number generators (TRNGs). The idea is to use the initial values of the cells as a source of entropy, extracting the noise that causes a cell in a meta-stable state (which is neither of its two stable states) to evolve into one of its stable states. Entropy is a mathematical measure of disorder, randomness or variability. According to the recommendations of the NIST (National Institute of Standards and Technology), the minimum entropy is the measure in the worst case of the uncertainty of a random variable, that is, it provides the maximum value that can take the probability of hitting the value of the random variable. The minimum entropy of a binary source, such as a memory cell, is defined as: Hmi * - -lo & G _* ⁾ where p _max is the maximum of a cell's chance of taking a "0" or a '' .

Assuming that all the bits provided by the cells when the power is connected are independent, each sequence of n bits has the following total minimum entropy:

In the applications of generation of truly random numbers, unlike in the applications of generation of identifiers or dynamic construction of secrets, it is interesting that the cells provide different value each time they are fed so that the total minimum entropy increases. Asymmetric cells are not suitable for generating randomness since their behavior can be predicted. Symmetric cells are much more suitable. It has been proposed to include additional circuitry that controls the original noise level of the cells and adjusts them to operate in a meta-stability regime. Other authors have also proposed to include circuitry to evaluate the quality of random numbers as they are generated. Another option is to process the bits to improve their statistical properties. A classic solution is to apply an XOR operator or a von Neumann concealer. The patent application [Harris2011] proposes the processing of the initialization bits generated by an error correction circuit. To achieve a truly random n-bit sequence, the proposal in [Holcomb2009] is to use a compression function (in particular a PH hash function) that compresses a sequence of many more bits, the more the smaller the total minimum entropy that has been obtained. The work in [Leest2012] uses a SHA-256 as hash function. The patent in [Níshino2005] also proposes the use of hash melons, preferably the MD2, MD4 or MD5 algorithms. The total minimum entropy values reported for SRAMs are usually low, because most cells always stabilize at the same value. For example, it is reported in [Holcomb2009] that to obtain a 128-bit number that passes the statistical tests of randomness 4096 bits are needed and in [Leest2012] it is reported that to obtain a 256-bit number, 12800 bits are required (in [Leest2012] different operating temperatures are contemplated for memory). The more bits that are necessary (because the lower the total minimum entropy), the slower the generation of random numbers.

Authentically random numbers are used in a multitude of encryption algorithms and secure communication protocols. In many cases, they are used as a seed to initialize algorithms for generating pseudo-random numbers, as proposed in [Leest2012]. In [Handschuh2012], random numbers are also derived from memory initialization bits in an indirect way, using a deterministic random number generator. Bibliography

[Gebara2012] F. H. Gebara, J. Kim, J. D. Schaub, and V. Strumpenl. "Temperature- profiled device fingerprint generation and authentication from power-up states of static cells". US Patent 8,219, 857 B2, July 2012.

[Guajardo2007] J. Guajardo, S. Kumar, G.J. Schrijen, and P. Tuyls. TPGA intrinsic PUFs and their use for IP protection ". Proc. Of Cryptographic Hardware and Embedded Systems (CHES), pages 63-80, 2007.

[Handschuh2012] H. Handschuh, G.J. Schrijen, E. Van der Sluis, "Random number generating system based on memory start-up noise", PCT / EP2012 / 056277, Oct. 2012.

[Harris2011] E.B. Harris, R. Hogg, RA. Kohler, RJ. McPariand, and W.E. Werner, "Secure random number generator", US Patent Application US 2011/0022648 A1, January 2011.

[Holcomb2009] D.E. Holcomb, W.P. Burieson, and K. Fu. "Power-up SRAM state as an identifying fingerprint and source of true random numbers". IEEE Transactions on Computers, 58 (9), pages 1198-1210, 2009.

[Kim2010] J. Kim, J. Lee, and J.A. Abraham. "Toward reliable SRAM-based device identification". In Proc. IEEE International Conference on Computer Design (ICCD), pages 313-320, 2010.

[Kumar2008] S.S. Kumar, J. Guajardo, R. Maes, G.J. Schrijenand, P. Tuyls, "The butterfly PUF protecting IP on every FPGA", in Proc. 1st IEEE Int. Workshop on Hardware-Oriented Security and Trust, HOST, 2008.

[Layman2004] P. A. Layman, S. Chaudhry, J. G. Norman, J. R. Thomson, "Electronic ﬁ ngerprinting of semiconductor integrated circuits". US Patent 6, 738,294, May 2004.

[Leest2012] V. van der Leest, E. van der Sluis, G.J. Schrijen, P. Tuyls, and H. Handschuh. "Efficient implementation of true random number generator based on SRAM PUFs". In Cryptography and Security: From Theory to Applications, pages 300-318. Springer, 2012.

[Maes2008] R. Maes, P. Tuyls, I. Verbauwhede. "Intrinsic PUFs from Flip-flops on reconfigurable devices". In: 3rd Benelux Workshop on Information and System Security (WISSec 2008), Eindhoven, NL, page 17, 2008.

[Nishino2005] Y. Nishino, "Methods and apparatus for random number generation". US Patent 7,676,531 B2, March 2010.

[Su2008] Y. Su, J. Holleman, and B. Otis, "A digital 1.6 pJ / bit chip identification circuit using process variations," IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 69-77, Jan. 2008. Description of the figures

Figure 1. Flow chart illustrating the steps of the first phase of the method of the invention.

Figure 2: Flow chart illustrating the steps of the second phase of the method of the invention.

Figure 3: Percentage of cells for the 20 samples of the analyzed circuit that are always stabilized at the same value in all operating conditions when: (a) all memory cells are contemplated because the method of the invention has not been applied ( in continuous black line), (b) only the cells labeled A are contemplated when the first phase of the method of the invention is carried out once contemplating three values of supply voltage and the same temperature (in continuous gray line) and (c) Only cells labeled A are contemplated when performing the first phase of the method of the invention three times contemplating three operating temperatures and the same supply voltage (in broken lines).

Figure 4: Impost and genuine populations for 128-bit identifiers when the bits come from: (a) any 128 cells in memory because the method of the invention has not been applied (in continuous black line), (b) 128 labeled cells as A when performing the first phase of the method of the invention once contemplating three values of supply voltage and the same temperature (in solid gray line) and (c) 128 cells labeled as A when performing the first phase of the method of three times. the invention contemplating three operating temperatures and the same supply voltage (in dashed lines).

Figure 5: Minimum total entropy (in%) for the 4 samples of the circuit measured in (a) nominal conditions, (b) the worst case for conditions in which the supply voltage varies and (c) the worst case for conditions in which vary the operating temperature. In all the figures, the total minimum entropy measured when the 2280 memory cells (without applying the method of the invention) is shown in a continuous black line, in a continuous gray line when the cells labeled B are considered when performing once the first phase of the method of the invention contemplating three values of supply voltage and the same temperature and in broken lines, when considering the cells labeled B when performing the first phase of the method of the invention three times contemplating three operating temperatures and The same supply voltage. Figure 6: Block diagram of the device that implements the method of the invention.

Figure 7: Schematic illustrating an embodiment of the device using additional circuitry in an FPGA to perform the classification and control blocks.

Description of the invention

The method proposed in the present invention aims at a new registration stage in which memory cells are classified into two disjoint sets, one suitable for generating identifiers (keys or secrets), and another suitable for generating random numbers. Thanks to this classification, in the number generation stage, the generated identifiers are more repeatable, so that they can have a smaller number of bits to achieve the same identification capabilities, keys or secrets can be generated reducing the complexity of the error correction codes and the entropy of the random numbers generated is improved. In addition, all this is achieved with the same registration stage, which can be repeated to improve the quality of the identifiers and random numbers generated in different operating conditions. The method can be applied without the need for a complex and expensive experimental setup (temperature chambers or temperature forcing systems are not necessary), but simply by controlling the supply voltage. As a consequence, the registration stage can be carried out with the memory in its application context, in a convenient and simple way. It is not necessary for the registration stage to be carried out by specialized vendors or at the factory where the memory is manufactured. The device presented in this invention to implement the proposed method can be made by adding very simple circuitry to any static memory or by running very simple software. The device can be authenticated without the need to store its identifier because it generates it in operation time and, at the same time, it can safely communicate its identity and any other sensitive information using the truly random numbers it generates. The proposed method allows generating at least one identification number of n bits and at least a truly random number of m bits from N static memory cells, each cell having the capacity to store a bit of information, in which n can take values from 0 to Nm and m can take values from 0 to Nn. The method is characterized in that it comprises a first phase in which classify the N memory cells into at least two groups labeled A and B, and a second phase in which at least one identification number of n bits is generated from n cells labeled in the first phase as A and at least a truly random number of m bits from m cells labeled in the first phase as B, where the first phase of classification is carried out at least once, so that, once the cells are classified, the generation of numbers of Identification and randomization can be carried out directly by executing the second phase without having to re-execute the first phase.

The first phase of the method, in turn, comprises: (a) leaving the memory without power (and, therefore, its cells) for a sufficient time for all the values of the bits that could be stored to disappear,

(b) connect the memory to a fixed supply voltage and read the values of the bits to which N memory cells have stabilized without first writing anything to them,

(c) save the values of the bits read from the N cells,

(d) leave the memory without power for long enough to erase the stored values,

(e) re-feed the memory with the same voltage value and reread the bit values of the N cells without first writing anything in them,

(f) compare the bit values obtained in step (e) with those saved in step (c), classifying the memory cells into two groups: the cells that always provide the same bit value and the cells that once they have provided a different bit value, (g) go to step (h) if all measurements have already been taken for the same set supply voltage value; while, in another case, return to step (d),

(h) label the cells that have always provided the same bit value for all measurements made at the same voltage value as S, label the other cells as U and save the result of the classification for the analyzed voltage value, (i) go to step (j) if all the supply voltage values have already been analyzed; while, in another case, set a new supply voltage value to analyze and return to step (a),

(j) compare the classification results obtained for the analyzed voltage values and label the memory cells that have always been labeled as S with all the voltage values analyzed with a label A and label the cells that have always been labeled as U with all voltage values analyzed with a B tag (assigning a C tag to cells that are not assigned a A or B tag). Figure 1 shows the flow chart illustrating the steps of the first phase of the method of the invention.

The second phase of the method in turn comprises:

(1) leave the memory (and, therefore, its cells) without power for a sufficient time so that all bit values that may be stored disappear,

(2) feed the memory to its nominal voltage value, write nothing in the N cells analyzed in the first phase and generate a sequence of bits (A-string) with the bit values to which the labeled cells have stabilized such as A and generate another sequence of bits (B-string) with the bit values of the cells labeled B, ending the reading when at least one A-string of n bits and a B-string of m bits are available,

(3) use the A-string to generate at least one digital identification number of n bits and the B-string to generate at least a truly random number of m bits. Figure 2 shows the flow chart illustrating the steps of the second phase of the method of the invention.

In the first phase of the method, P supply voltage values are analyzed (P being greater than or equal to 1), of which at least one is the nominal voltage value (Vdd). If several supply voltage values are analyzed in the first phase of the method, it is convenient to analyze the voltage range for which memory can work normally, which is usually 10% above and below Vdd. Therefore, it is convenient to analyze, in addition to Vdd, a value less than the nominal Vdd _min = 0.9Vdcl and a value greater than the nominal Vdd _max = 1.1Vdd. As memory can work normally, it is not necessary to disconnect it from the rest of the circuitry to which it could be connected. In addition, if the memory is part of an electronic device that can also work with these voltage levels, the method of the invention can be applied to the entire device without problem.

The method is also characterized in that when the first phase of the method is repeated, the cells that in the previous first phase were labeled with A are labeled with A and in the current first phase of the method they are re-labeled as A; the cells that in the previous first phase were labeled with B are tagged with B and in the current first phase of the method they are re-labeled as B and the rest of the cells are labeled with a C tag. When the first phase of the method is performed without indicating that it is a repetition, any result of possible previous classifications is deleted and the result of the current classification is stored. The repetition of the first phase of the method allows the classification to be refined considering other possible memory operating conditions.

Since SRAMs are part of many integrated circuits or electronic devices, the method of this invention focuses primarily on them, but other types of static memory cells can be used. To test the advantages of the method of the invention in identification / authentication and key or secret generation applications, the values at which 168 memory cells of a SRAM included in an integrated circuit of specific applications manufactured in a technology have been stabilized 90 nm of TSMC (Taiwan Semiconductor Manufacturing Company). The memory has not been disconnected from the rest of the circuitry. Twenty samples of the same integrated circuit have been analyzed under different operating conditions: supply voltage of 0.9Vdd, Vdd and 1.1 Vdd, with Vdd the nominal supply value; and temperatures of 5 ° C, 25 ° C and 75 ° C. For each operating condition the measurements have been repeated 20 times (with 20 times the resulting classification was already stabilized). Figure 3 shows in a continuous black line the percentage of cells for the 20 samples of the circuit that are always stabilized at the same value in all operating conditions if the method of the invention is not applied. If the first phase of the method of the invention is applied considering the three supply voltage values (0.9Vdd, Vdd, and 1.1Vdd) at the same temperature (25 ° C in that case), the percentage of cells that are labeled as A is between 71.4% and 83.9%. The percentage of these cells for the 20 circuit samples that are always stabilized at the same value in all operating conditions (considering the rest of the temperatures) is shown in a continuous gray line in Figure 3. When considering only the cells labeled A , the percentage of them that always provides the same value has increased considerably, passing, for example in one of the samples, from 73.8%, if the method is not applied, to 90.5%, when the method is applied.

Another test has been applied three times the first phase of the method considering only the nominal supply voltage value. The first time was performed when the operating temperature of the circuit was 25 ° C. Subsequently, the first phase of the method is repeated when the circuit was at an operating temperature of 5 ° C, and again the first phase of the method is repeated when the circuit was at an operating temperature of 75 ° C. The percentage of cells that are labeled as A is between 62.5% and 73.8%. Cells labeled A are much more stable in all operating conditions. The percentage of these cells for the 20 circuit samples that are always stabilized at the same value in all operating conditions (considering the rest of the supply voltages) is shown in dashed lines in Figure 3. When considering only the cells labeled as A, the percentage of them that always provide the same value has increased again considerably, passing, for example in one of the samples, from 73.8%, if the method is not applied, to 99.2%, when the method is applied.

In order to generate the n-bit identifier in the second phase of the method, n cells labeled A are required. If, in the worst case, type A cells are 62.5% of the N, the order of 1.6n cells needs to be labeled at least. For example, for a 128-bit identifier, N≥ 205 cells are required. The number of cells N analyzed in the first phase sets the maximum bit size of the identifiers that can be generated. Of course, depending on the application, an identifier with more bits or several identifiers with fewer bits each can be generated. The latter case may be interesting to change the identifier that is generated, for example to revoke identifiers that might have been compromised. Figure 4 illustrates how the application of the method of the invention improves the separation between the impostor and genuine population in identification / authentication applications. The graphics correspond to 128-bit IDs. The resulting populations are shown in continuous black line when any 128 cells in memory are used. The resulting populations are shown in a continuous gray line when the first phase method is applied considering the three supply voltage values (0.9Vdd, Vdd, and 1.1 Vdd) at the same temperature (25 ° C) and the ID is generated with 128 cells labeled A. The resulting populations are shown in dashed lines when the method is applied, applying the first phase three times considering only the nominal supply voltage value (the first time when the circuit's operating temperature was 25 ° C, subsequently repeated for 5 ° C, and again repeated for 75 ° C) and the ID is generated with 128 cells labeled A. In identification / authentication applications, the ID of the user must be re-registered. memory if the first phase of the method is repeated. The results are advantageous not only to generate IDs but also to retrieve secrets or keys. For example, Figure 4 illustrates that the maximum Hamming distance between IDs obtained in the key recovery phase and IDs registered for the same set of cells (genuine population) can reach 22% if the method is not applied, which is equivalent to the percentage of error that would have to correct the error correction code in an HDA algorithm. Applying the first phase of the method once contemplating different supply voltages and the same temperature, the maximum distance is reduced to 15%, which considerably simplifies the decoder of the error correction code. If the first phase of the method is carried out three times contemplating three different operating temperatures and the same supply voltage, as mentioned above, the reliability of the key generation is increased (Hamming's maximum distance is reduced up to 10% ).

In order to prove the advantages of the method of the invention for generating truly random numbers, the values at which 2280 memory cells of the same previous SRAM included in an integrated circuit of specific applications have been measured (manufactured in the 90 nm technology of TSMC). Four samples of the same integrated circuit under different operating conditions have been analyzed: supply voltage of 0.9Vdd, Vdd and 1.1 Vdd, with Vdd the nominal supply value; and temperatures of 5 ° C, 25 ° C and 75 ° C. For each operating condition the measures have been repeated 100 times to obtain a good estimate of the entropy. Figure 5 shows the minimum total entropy for the 4 samples of the circuit measured in (a) nominal conditions, (b) the worst case for conditions in which the supply voltage varies and (c) the worst case for conditions in which the operating temperature varies. In all figures, the total minimum entropy measured when 2280 memory cells are considered in a continuous black line, without applying the method of the invention. A worse value of 1.7% is obtained.

In continuous gray line, Figure 5 shows the minimum total entropy measured when considering the cells labeled B after applying the first phase of the method of the invention considering the three values of supply voltage (0.9Vdd, Vdd, and 1.1 Vdd) at the same temperature (25 ° C in that case). The worst value obtained is increased to 7.75%. The percentage of cells that are labeled B is between 8.9% and 10%. The total minimum entropy measured when considering the cells labeled B after considering the first phase of the method three times considering the nominal voltage value and the three operating temperatures of 5 ° C, 25 ° C and 75 ° is shown in broken lines. C, as previously commented. The worst value obtained from total minimum entropy increases to 16%. The percentage of cells that are labeled B is reduced, between 2.6% and 3.8%.

To generate a random number of m bits, m cells labeled B are needed. If, in the worst case, type B cells are 8.9% of the N, at least 11.2m cells need to be labeled. For example, to generate a random number of 80 bits, you need N≥ 896 cells. If the classification has been further refined and, in the worst case, type B cells are 2.6% of the N, at least 38.5m cells need to be labeled. For example, to generate a random number of 80 bits, you need N> 3080 cells. The number of N cells analyzed in the first phase sets the maximum bit size of the truly random numbers that can be generated. Normally this is not a limitation because the static memories used in today's electronic devices are high capacity. Of course, depending on the application, a random number with more bits or several random numbers with fewer bits each can be generated.

The time that has been chosen in the experiments to leave the memory without power has been 30 seconds. If in the first phase of the method Q = 20 measurements are made for each P = 3 supply voltage, 30x20x3 = 1800 seconds = 30 minutes are necessary. In each measure the N memory cells must be read, but this time is negligible compared to the previous one, so many can be analyzed cells. The first phase of the method can be carried out in any time interval in which it is not necessary to generate random identifiers or numbers. In addition, it is not a phase that has to be carried out continuously. On the other hand, the time for number generation is essentially marked by the reading time of the cells necessary to generate the n-bit identifier and the random number of m bits. The memory analyzed in the experiments provided 60 bits for each word and the reading time of each word was at least 2.4 nanoseconds. In the worst case (if each cell had different access addresses) to generate a number of n bits, 2.4 nanoseconds would be needed for each bit, for example 307.2 nanoseconds for a 128-bit number. If the analyzed memory is double port, the time is reduced by half: 1.2 nanoseconds per bit in the worst case, for example 153.6 nanoseconds for a 128-bit number. The method of the invention not only reduces the reading time of cells (because fewer cells need to be read) but also the time of the possible subsequent processing (for example, if a hash function is applied to obtain a completely random 128-bit seed in In all operating conditions, 942 bytes would need to be processed without applying the method, while 207 bytes would only need to be processed after applying the method with a first phase contemplating three supply voltage values, as discussed above, which would mean a reduction in the data processing of 78%).

The method can be implemented by means of a device that has at least two selectable modes of operation: memory cell labeling mode and number generation mode, where the number generation mode works correctly if the data mode has been previously carried out. tagged at least once. Said device is characterized in that it comprises:

• a static memory (1),

• a voltage block (2) that stops feeding the memory (1) or feeds it at a certain voltage value,

• a classification block (3) which, if the mode of operation is that of labeling, analyzes which cells in memory (1) to assign the label A and to which the label B, and, if the mode of operation is that of number generation, sends the classification result to the control block (4);

• a control block (4) that controls all other blocks to execute the steps of the method, so that: (a) it indicates to the voltage block (2) when not to feed the memory (1) and when to feed it and, in that case, set the value of the supply voltage; (b) enables the reading of the memory (1) and activates the specific signals of the reading of the memory cells; (c) indicates to the classification block (3) the mode of operation and, if the mode of operation is that of number generation, (d) uses the information stored in the labeling mode to read the bits generated by the memory cells with tag

A and generate with them identifiers and the bits generated by the cells with label B and generate with them random numbers.

Figure 6 shows the block diagram of the device that implements the method of the invention.

In one embodiment of the device, the static memory (1) is a static random access memory, SRAM.

The voltage block can be made using a programmable power supply available in many laboratories. However, to achieve a portable and cheap embodiment that can, for example, be included in the printed circuit board containing the memory, it is preferable that the voltage block (2) comprises:

• a switch controlled by a digital signal from the control block (4) that closes or opens the switch to feed or not to memory (1) and

· A potentiometer digitally controlled by the control block (4) to modify the value of the voltage that feeds the memory (1), in the case of analyzing more than one supply voltage value (in the case of analyzing only the nominal voltage value the potentiometer is not necessary). In a preferred embodiment of the device, the classification block (3) comprises:

• a memory or registers to store the N bits read from the memory (1) in the first measurement carried out at a supply voltage, deleting the previously stored ones;

• XOR operators intended to compare the bits read from memory (1) in each measurement with the bits stored from the first measurement made at the same voltage supply value, resulting in logical values "0" if the values of the bits of both readings match and "1" values if the values do not match; • OR operators intended to combine the results of previous XOR operators obtained on measurements at the same supply voltage value, resulting in a logical value "0" for a cell that always provides the same bit value in all measurements and a logical value "1" for a cell that has ever provided a different bit value;

• one memory or registers destined to store NxP bits (N bits for each one of the P voltage values analyzed), each bit of them N labeling one of the N memory cells analyzed, so that the bit value indicates if the cell has been labeled as S (bit value "0") or as U (bit value "1") for each voltage value, so that, in the case of analyzing a single voltage value, at a a cell labeled S is assigned the code of tag A and a cell labeled as U is assigned the code of tag B;

• ÑOR operators, in the case of analyzing P> 1 supply voltage values, intended to combine P bits of tags for each cell, so that if a logical value "1" results, the cell is assigned the code of the label A;

• AND operators, in the case of analyzing P> 1 supply voltage values, intended to combine P tag bits for each cell, so that if a logical value "1" results, the cell is assigned the code of the label B;

• a memory or registers to store 2N bits, in the case of analyzing P> 1 supply voltage values, every 2 bits encoding if each of the N memory cells analyzed has the label A, B or none of them. · XOR operators intended to compare the labels associated with the N cells obtained in the current labeling operation mode with the labels obtained in previous labeling operation mode (s).

Of course, any other embodiment equivalent to the one described above would be equally valid (for example, applying that NAND operators of supplemented data is equivalent to OR operators of non-complementary data).

The memories or records used by the classification block can be deleted or rewritten after the labeling mode, except for the memory or records stored the 2N bits of the labels, which must be maintained to be used in the device number generation mode or in possible repetitions of the labeling.

In a preferred embodiment of the device, the control block (4) comprises:

• counters to measure: (a) the time that is left to the memory block (1) without feeding, (b) the measurements that are carried out for each supply voltage value, (c) the number of the values of voltage to analyze, in the case of analyzing several supply voltages, (d) the memory cells that are analyzed, (e) the number of bits to generate identifiers and (f) the number of bits to generate random numbers;

· A block that translates the labels associated with the N cells into memory access addresses (1).

Since the labels associated with the cells are stored in order, it is possible to know how to access the cells labeled as A to generate the identifiers and those labeled as B to generate the random numbers (it is known, for example, to which word in the memory they correspond and what bit inside the word).

When the labeling operation mode is configured in the device, the control block (4) receives as configuration parameters at least the number N of memory cells to be analyzed, the number P of supply voltages to be set, the number Q of Measures to be taken for each supply voltage and a REP binary signal, which indicates whether the labeling is repeated or not, and receives a start signal, INIT, which initializes all counters to zero and marks the beginning of the labeling process, so that the control block (4), for each of the voltages to be analyzed, tells the voltage block (2) not to feed the memory (1) for the necessary time, which is controlled by one of the counters of the control block; After that time, the control block (4) instructs the voltage block (2) to feed the memory (1) to the determined voltage value and activates the specific signals of the data reading in the memory (1) to read the bits to which N memory cells have been stabilized, the reading mechanism of the input signals and memory (1) depending, the timing of said reading depending on the type of memory used, and controlling one of the block counters control (4) when the reading of N cells at least ends; in addition, the control block (4) tells the classification block (3) to operate in labeling mode, so that the classification block (3) receives the N bits of the memory (1), storing the bits corresponding to the first measurement of each supply voltage and comparing with them the successive N bits read in the successive measurements, using XOR operators for comparison, and combining with OR operators the results for each cell obtained from the XOR operations, resulting in a value logical "0" for cells that always provide the same bit value in successive measurements and a logical value "1" for cells that have ever changed the bit value provided in successive measurements, storing those results in memory or N-bit registers associated with the analyzed supply voltage; so that when the counter of the control block (4) that counts the measures analyzed at that voltage value reaches the configured Q value, if P = 1 and REP = 0 (the labeling is not repeated), the block of control (4) instructs the classification block (3) to store in a memory or registers of 2N bits, in an orderly manner, the N labels encoded with 2 bits of the N cells, so that the classification block (3) stores the 2 bits that indicate the A tag for the cells that always provided the same bit value (a "0" logical value resulted after the OR operation) and stores the 2 bits that indicate the B tag for the cells that ever changed the bit value provided (a logical value "1" resulted after the OR operation); and if REP = 1 and N maintains its value (the labeling is repeated), the control block (4) instructs the classification block (3) to compare in an orderly manner and by XOR operators if each label obtained for each cell is A or B, as in previous labels, in which case the corresponding labels A or B are stored in the memory or 2-bit registers, while if the new label obtained is neither A nor B or the new ones do not coincide with the new ones obtained tags, then 2 bits indicating the C tag are stored for that cell; while if P> 1, the control block (4) initiates other Q measurements, initializing the counters that count the number of cells to be analyzed and the number of measurements to be performed, indicating to the voltage block (2) the following value of tension to analyze; repeating the process until the control block counter (4) that counts the analyzed voltage values reaches the configured P value, in which case, the control block (4) tells the classification block (3) to combine the P groups of N bits stored for each supply voltage analyzed by ÑOR and AND operators and store in a memory or registers of 2N bits, in an orderly manner, the N labels encoded with 2 bits of the N cells, so that the block of classification (3), if REP = 0, it stores the 2 bits that indicate the label A for the cells that always provided the same bit value for all the measurements and all the voltages (they were a logical value "1" after the operation OR), stores the 2 bits that indicate the B label for the cells that ever changed the bit value provided for all voltages (a "1" logic value resulted after the AND operation), and stores 2 bits that indicate the tag C, for the rest of the cells, and if REP = 1 and the value of N is maintained, the control block (4) tells the classification block (3) to compare in an orderly manner and by XOR operators if each label obtained for each cell it is A or B, as in previous labels, in which case the corresponding labels A or B are stored in the memory or 2-bit registers, while if the new label obtained is neither A nor B or does not match with the previous the new labels obtained, the 2 bits that indicate the C label are stored for that cell; so that, when the labeling process is finished, the control block (4) indicates this by means of a binary signal FIN.

When the number generation operation mode is configured in the device, the control block (4) receives as configuration parameters at least the size in bits, n, of the identifier to be generated and the size in bits, m, of the random number to be generated, and receives a start signal, INIT, which initializes all the counters to zero and marks the beginning of the generation process, so that the control block (4) tells the voltage block (2) not to supply the memory (1) for the necessary time, which is controlled by one of the counters of the control block; after that time (or if the memory had already been disconnected from the power for at least that time) the control block (4) tells the voltage block (2) to feed the memory to the nominal voltage value and tells the classification block (3) to send the associated labels to the N cells, so that they are translated into access addresses to the cells of type A and B of the memory (1); using this information, the control block activates the specific signals of the data reading in the type A and B cells of the memory (1), the reading mechanism of the input signals and the memory (1) and the timing of said reading depending on the type of memory used, and the control block (4) concatenates the bits generated by cells labeled A in the A-chain and the bits generated by cells labeled as B in the B-chain; so that one of the counters of the control block counts n bits of the A-string, which the control block provides as an identifier and one of the counters of the control block counts m bits of the B-string, that the block of control provides them as a truly random number; so that when the generation process of numbers has ended, the control block (4) indicates this by means of a FIN binary signal.

Embodiment of the invention The functionality of the classification and control blocks can be carried out by means of software executed in a microcontroller or microprocessor for which the memory is an external memory.

Another possibility is to perform the classification and control blocks using additional circuitry (dedicated hardware). Figure 7 illustrates a schematic of this solution. The classification and control blocks have been implemented in a FPGA (Field Programmable Gate Array) XC3S50 of Xilinx, which has 1728 equivalent logical cells and 72 Kbits (K = 1024) of Block RAMs (4 Block RAMs of 18 Kbits each ). This exemplary embodiment includes a static SRAM memory, external to the FPGA, with a capacity for 2 ¹⁵ words of 8 bits each, which allows parallel reading of the 8 bits. The voltage block, also external to the FPGA, contains a potentiometer controlled by an 11-bit signal and a switch controlled by a 1-bit signal, where the 12 control bits are provided by the control block implemented by a state machine finite (FSM) in the FPGA. Both the FPGA and the voltage block receive power externally through a voltage regulator while the SRAM receives power from the voltage block. Everything is included in a small printed circuit board. In this exemplary embodiment, the SRAM is not part of any digital system but in other embodiments, the SRAM could be a block of a larger system and it would not be necessary to disconnect it from the system.

The FSM (control block) implemented in the FPGA controls, by means of the binary signal "Mode" (which takes the value indicated to the input), if the mode of operation is number generation (in which case the bits that are read from the SRAM are sent to the control block) or the mode is labeled (in which case the bits that are read are sent to the classification block). In the labeling operation mode, the FSM (control block) controls all the write and read enable signals of the FPGA Block RAMs and all the timing of the labeling steps. The FSM contains a 32-bit counter to measure the time left to the memory block without feeding. This counter has the size necessary to count at least 30 seconds at the clock frequency of the FPGA (which is 50MHz) without overflowing. The FSM also contains a 5-bit counter to count the measurements, Q, which are carried out for each supply voltage value (which takes the value indicated at the input) and a 2-bit counter to count the number, P, of the voltage values to be analyzed (which takes the value indicated to the input, limited in this example of embodiment to 3 values). The WFTU also controls whether the measurement taken from memory is the first of a labeling phase or not. The bits that are read for the first time from the SRAM are stored in one of the FPGA Block RAMs and the bits of the successive measurements are compared with them by XOR operators (8 XOR operators in this embodiment to compare the 8 bits of a word in parallel). The results (S or U labels) for the three possible supply voltage values of this example are stored in the other three Block RAMs. The final labels of the labeling process (labels A, B or C) are stored in the first of the Block RAMs. Since N free bits of that Block RAM are left to store the first measurements of other possible tags, tags of up to N = 6144 cells can be stored in this embodiment, occupying all that Block RAM. The FSM contains a 10-bit counter to count the N memory cells to analyze (up to 2 x ¹⁰ x 8 cells, but with the limit in 6144 cells). The 10-bit counter performs the function of addressing the memory. If the REP signal (which takes the value that is marked to the input) indicates that the labeling is repeated and the value of N is maintained, the new labels (A, B or C) obtained are compared by XOR operators with those previously stored, so that if the output of these operators indicates that there has been no change of labeling, the stored labels are maintained while if there has been change, the label C is stored. This labeling control is the one that performs the sub-block called "labeling logic" within the classification block.

When the mode selected is that of number generation, the 10-bit counter of the FSM also performs the function of addressing the memory. The sub-block "tag translator" that contains the FSM checks if there is a bit in the word addressed by the counter to be used to generate an identifier or a truly random number. If so, the WFTU reads that word from the SRAM and selects the bits for the identifier or the random number based on its label. If not, the counter is incremented without that word being read. A 7-bit counter counts the number of bits, n, of the identifiers and the number of bits, m, of the random numbers. In this exemplary embodiment, the bits of the truly random identifier and number are provided in series by the ID and TRN outputs, respectively.

Depending on the mode of operation, the 7 bits for the n / P input bus are taken as the value of n (number generation mode) or P (labeling mode) and the 7 bits for the m / Q input bus are they take the value of m (number generation mode) or Q (labeling mode). The 10 bits per input bus N allow you to choose the number of addresses that are read at most from memory, while the binary signals INIT, REP and FIN indicate, respectively, the start of processing, whether or not there is a repetition of the mode labeling and completion of processing.

Claims

1.- Method to generate at least one identification number of n bits and at least a truly random number of m bits from N static memory cells, each cell having the capacity to store a bit of information, in which n can take values from 0 to Nm and m can take values from 0 to Nn, the method being characterized in that it comprises a first phase in which the N memory cells are classified into at least two groups labeled A and B, and a second phase in the that at least one identification number of n bits is generated from n cells labeled in the first phase as A and at least a truly random number of m bits from m cells labeled in the first phase as B, where the first Classification phase is carried out at least once, so that, once the cells are classified, the generation of identification and random numbers can be carried out directly by executing the second phase without having to rerun the first phase; where the first phase of the method in turn comprises:

(a) leave the memory without power (and, therefore, its cells) for a sufficient time so that all the values of the bits that could be stored disappear,

(c) save the values of the bits read from the N cells,

(d) leave the memory without power for long enough to erase the stored values, (e) re-feed the memory with the same voltage value and reread the bit values of the N cells without first writing anything in them,

(f) compare the bit values obtained in step (e) with those saved in step (c), classifying the memory cells into two groups: the cells that always provide the same bit value and the cells that once have provided a different bit value, (g) go to step (h) if all measurements have already been taken for the same set supply voltage value; while, in another case, return to step (d),

(h) label the cells that have always provided the same bit value for all measurements made at the same voltage value as S, label the other cells as U and save the result of the classification for the analyzed voltage value,

(i) go to step (j) if all the supply voltage values have already been analyzed; while, in another case, set a new supply voltage value to analyze and return to step (a), (j) compare the classification results obtained for the analyzed voltage values and label the memory cells that have been labeled always as S with all the voltage values analyzed with a label A and label the cells that have always been labeled as U with all the voltage values analyzed with a label B (assigning a label C to the cells that are not assigned a label A or B); and where the second phase of the method in turn comprises:

(1) leave the memory without power (and, therefore, its cells) for a sufficient time so that all the bit values that could be stored disappear, (2) feed the memory to its nominal voltage value, not write anything in the N cells analyzed in the first phase and generate a bit sequence (A-string) with the bit values to which the cells labeled A have stabilized and generate another bit sequence (B-string) with the bit values of the cells labeled B, ending the reading when at least one A-string of n bits and a B-string of m bits are available,

(3) use the A-string to generate at least one digital identification number of n bits and the B-string to generate at least a truly random number of m bits.

2. Method according to claim 1 characterized in that in a first phase P voltage supply values are analyzed (P being greater than or equal to 1), of which at least one is the nominal voltage value (Vdd).

3. Method according to any one of claims 1 to 2, characterized in that when the first phase of the method is repeated, the cells that in the previous first phase were labeled with A are labeled and in the current first phase of the method they return to be labeled as A; the cells that in the previous first phase were labeled with B are tagged with B and in the current first phase of the method they are re-labeled as B and the rest of the cells are labeled with a C tag.

4. - Method according to any one of claims 1 to 2, characterized in that when the first phase of the method is carried out without indicating that it is a repetition, any result of possible previous classifications is erased and the result of the current classification is stored.

5. Device for implementing the method as defined in claims 1 to 4 which presents at least two modes of operation you selected: memory cell labeling mode and number generation mode, where the number generation mode works correctly if previously the labeling mode has been carried out at least once; said device being characterized in that it comprises:

• a static memory (1),

· A control block (4) that controls all other blocks to execute the steps of the method, so that: (a) it indicates to the voltage block (2) when not to feed the memory (1) and when to feed it and, in that case, set the value of the supply voltage; (b) enables the reading of the memory (1) and activates the specific signals of the reading of the memory cells; (c) indicates to the classification block (3) the mode of operation and, if the mode of operation is that of number generation, (d) uses the information stored in the labeling mode to read the bits generated by the memory cells with tag

Device according to claim 5, characterized in that the static memory (1) is a static random access memory, SRAM.

Device according to any one of claims 5 to 6, characterized in that the voltage block (2) comprises:

• a potentiometer digitally controlled by the control block (4) to modify the value of the voltage that feeds the memory (1), in the case of analyzing more than one supply voltage value (in the case of analyzing only the nominal voltage value the potentiometer is not necessary).

Device according to any one of claims 5 to 7, characterized in that the classification block (3) comprises:

• XOR operators intended to compare the bits read from memory (1) in each measurement with the bits stored from the first measurement made at the same voltage supply value, resulting in logical values "0" if the values of the bits of both readings match and "1" values if the values do not match;

• OR operators intended to combine the results of previous XOR operators obtained on measurements at the same voltage value of feeding, resulting in a logical value "0" for a cell that always provides the same bit value in all measurements and a logical value "1" for a cell that has ever provided a different bit value;

• a memory or registers destined to store NxP bits (N bits for each of the P voltage values analyzed), each bit of the N labeling one of the N memory cells analyzed, so that the bit value indicates if the cell has been labeled as S (bit value "0") or as U (bit value "1") for each voltage value, so that, in the case of analyzing a single voltage value, at a a cell labeled S is assigned the code of tag A and a cell labeled as U is assigned the code of tag B;

• OR operators, in the case of analyzing P> 1 supply voltage values, intended to combine P tag bits for each cell, so that if a logical value "1" results, the cell is assigned the code of the label A;

· A memory or registers to store 2N bits, in the case of analyzing P> 1 supply voltage values, every 2 bits encoding if each of the N memory cells analyzed has the label A, B or none of them.

• XOR operators intended to compare the labels associated with the N cells obtained in the current labeling operation mode with the labels obtained in previous labeling operation mode (s).

Device according to any one of claims 5 to 8, characterized in that the control block (4) comprises:

• counters to measure: (a) the time that is left to the memory block (1) without feeding, (b) the measurements that are carried out for each supply voltage value, (c) the number of the values of voltage to analyze, in the case of analyzing several supply voltages, (d) the memory cells that are analyzed, (e) the number of bits to generate identifiers and (f) the number of bits to generate random numbers; • a block that translates the labels associated with the N cells into memory access addresses (1).

10. Device according to any of claims 5 to 9, wherein, when configuring the labeling operation mode, the control block (4) receives as configuration parameters at least the number N of memory cells to be analyzed, the number P of supply voltages to be set, the number Q of measurements to be taken for each supply voltage and a binary signal REP, which indicates whether the labeling is repeated or not, and receives a start signal, INIT, which initializes all zero the counters and which marks the beginning of the labeling process, so that the control block (4), for each of the voltages to be analyzed, tells the voltage block (2) not to feed the memory (1) during the required time, which is controlled by one of the control block counters; After that time, the control block (4) instructs the voltage block (2) to feed the memory (1) to the determined voltage value and activates the specific signals of the data reading in the memory (1) to read the bits to which N memory cells have been stabilized, the reading mechanism of the input signals and memory (1) depending, the timing of said reading depending on the type of memory used, and controlling one of the block counters control (4) when the reading of N cells at least ends; in addition, the control block (4) tells the classification block (3) to operate in labeling mode, so that the classification block (3) receives the N bits of the memory (1), storing the corresponding bits to the first measurement of each supply voltage and comparing with them the successive N bits read in the successive measurements, using XOR operators for comparison, and combining with OR operators the results for each cell obtained from the XOR operations, resulting in a logical value " 0 "for cells that always provide the same bit value in successive measurements and a logical value" 1 "for cells that have ever changed the bit value provided in successive measurements, storing those results in memory or registers N bits associated with the analyzed supply voltage; so that when the counter of the control block (4) that counts the measures analyzed at that voltage value reaches the configured Q value, if P = 1 and REP = 0 (the labeling is not repeated), the block of control (4) instructs the classification block (3) to store in a memory or registers of 2N bits, in an orderly manner, the N labels encoded with 2 bits of the N cells, so that the classification block (3) stores the 2 bits that indicate the label A for the cells that always provided the same value bit (resulted in a logical value "0" after the OR operation) and stores the 2 bits that indicate the B label for the cells that ever changed the bit value provided (resulted in a logical value "1" after the OR operation) ; and if REP = 1 and N maintains its value (the labeling is repeated), the control block (4) instructs the classification block (3) to compare in an orderly manner and by XOR operators if each label obtained for each cell is A or B, as in previous labels, in which case the corresponding labels A or B are stored in the memory or 2-bit registers, while if the new label obtained is neither A nor B or the new ones do not coincide with the new ones obtained tags, then 2 bits indicating the C tag are stored for that cell; while if P> 1, the control block (4) initiates other Q measurements, initializing the counters that count the number of cells to be analyzed and the number of measurements to be performed, indicating to the voltage block (2) the following value of tension to analyze; repeating the process until the control block counter (4) that counts the analyzed voltage values reaches the configured P value, in which case, the control block (4) tells the classification block (3) to combine the P groups of N bits stored for each supply voltage analyzed by ÑOR and AND operators and store in a memory or registers of 2N bits, in an orderly manner, the N labels encoded with 2 bits of the N cells, so that the block of classification (3), if REP = 0, it stores the 2 bits that indicate the label A for the cells that always provided the same bit value for all the measurements and all the voltages (they were a logical value "1" after the operation ÑOR), stores the 2 bits that indicate the label B for the cells that ever changed the bit value provided for all voltages (a "1" logic value resulted after the AND operation), and stores 2 bits that indicate the label C , for the rest of the cells, and if REP = 1 and the value of N is maintained, the control block (4) tells the classification block (3) to compare in an orderly manner and by XOR operators if each label obtained for each cell is A or B, as in previous labels, in which case the corresponding labels A or B are stored in the memory or 2-bit registers, while if the new label obtained is neither A nor B or does not match the previous the new labels obtained, the 2 bits that indicate the C label are stored for that cell; so that, when the labeling process is finished, the control block (4) indicates this by means of a binary signal FIN.

Device according to any one of claims 5 to 10, in which, when configuring the number generation operation mode, the control block (4) receives as configuration parameters at least the bit size, n, of the identifier a generate and the bit size, m, of the random number to be generated, and receives a start signal, INIT, which initializes all counters to zero and marks the beginning of the generation process, so that the control block (4) instructs the voltage block (2) not to feed the memory (1) for the necessary time, which is controlled by one of the counters of the control block; after that time (or if the memory had already been disconnected from the power for at least that time) the control block (4) tells the voltage block (2) to feed the memory to the nominal voltage value and tells the classification block (3) to send the associated labels to the N cells, so that they are translated into access addresses to the cells of type A and B of the memory (1); using this information, the control block activates the specific signals of the data reading in the type A and B cells of the memory (1), the reading mechanism of the input signals and the memory (1) and the timing of said reading depending on the type of memory used, and the control block (4) concatenates the bits generated by cells labeled A in the A-chain and the bits generated by cells labeled as B in the B-chain; so that one of the counters of the control block counts n bits of the A-string, which the control block provides as an identifier and one of the counters of the control block counts m bits of the B-string, that the block of control provides them as a truly random number; so that, when the number generation process is finished, the control block (4) indicates this by means of a binary signal FIN.