CN109359074A - A kind of PCIE signal expansion equipment and communication test method - Google Patents
A kind of PCIE signal expansion equipment and communication test method Download PDFInfo
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Abstract
A kind of PCIE signal expansion equipment, including PCIE bus interface circuit unit, PCIE turn serial port circuit unit, serial ports test circuit unit and power supply circuit unit, and test method includes that serial ports is surveyed with serial ports to survey certainly；Simple, easy to accomplish, the easy to operate equipment of its structure, method test is fast and effective, and precision is high；Testing procedure and test connection are simple；The test platform built using the method only needs one piece of board connection, does not need excessive test cable.
Description
Technical Field
The present invention relates to the field of computer design, and in particular, to a PCIE (Peripheral component interconnect Express) signal expansion device and a communication test method.
Background
With the rapid development of computer technology in information technology, PCIE buses are increasingly applied to processor systems due to their excellent performances such as high bandwidth, flexibility in expansion, support of hot plug and heat exchange, and with the gradual increase of PCIE bus devices that need to be mounted on a computer system, PCIE signal expansion devices based on PCIE switch are in due course.
In the prior art, devices such as a network card with a PCIE interface or 1394 with a PCIE interface are used for testing a PCIE communication function of a computer motherboard, and the testing method and the testing steps are complex and tedious, and the testing convenience is low.
Disclosure of Invention
The invention aims to provide PCIE signal expansion equipment and a communication test method, which can overcome the defects of the prior art, are equipment with simple structure, easy realization and convenient operation, and have quick and effective test and high precision.
The technical scheme of the invention is as follows: a PCIE signal expansion device is characterized by comprising a PCIE bus interface circuit unit, a PCIE-to-serial port circuit unit, a serial port test circuit unit and a power supply circuit unit; the PCIE-to-serial port circuit unit is respectively in bidirectional connection with the PCIE bus interface circuit unit and the serial port test circuit unit; and the power supply circuit unit is connected with the PCIE-to-serial port circuit unit and provides a working power supply for the signal expansion equipment.
The PCIE bus interface circuit unit is used for realizing the input of an extended PCIE signal in PCIE signal extension equipment to be tested and is composed of two paths of VPX (VITA 46 standard) connectors; one of the connectors is a VPX P0 connector, which is used for realizing the input of a power supply signal, generating a +12V power supply voltage and connecting the power supply voltage with a PCIE-to-serial port circuit unit; the other is a VPX P1 connector which is used for realizing the communication of the extended PCIE signals in the PCIE signal extension equipment to be tested and is connected with the PCIE-to-serial port circuit unit.
The VPX P0 connector is a CPCI Express 254018 connector of ERNI company and can realize the input of a +12V power supply; the VPX P1 connector is a CPCIExpress 973028 connector of ERNI company, and realizes input of PCIE signals.
The PCIE-to-serial port circuit unit is used for realizing the conversion from a PCIE bus protocol to a serial port bus protocol and consists of a PCIE-to-serial port chip, an EEP chip and a crystal oscillator; one end of the PCIE-to-serial port chip is connected with a VPX P1 connector in a PCIE bus interface circuit unit to realize the communication of PCIE signals, and the other end of the PCIE-to-serial port chip is connected with a serial port test circuit to realize the communication of serial port signals; the EEP chip is connected with the PCIE-to-serial port chip and used for storing software configuration of the PCIE-to-serial port chip; the crystal oscillator is connected with the PCIE serial port chip and used for providing clock input.
The PCIE-to-serial port chip adopts a PI7C9X795 chip of DIODES company to complete the conversion from a PCIE bus protocol of X1 to a 2-path serial port bus protocol; the EEP chip is AT93C56 chip of ATMEL company; the crystal oscillator is a ZPB-26-14.7456MHz crystal oscillator of Tangshan finishing company.
The serial port test circuit is used for realizing serial port signal test connection in different test modes and is composed of a test connector; the test connector is composed of 12 x2 2.54mm pin connector and 2 jump caps; the pin connector is provided with 4 terminals which are respectively marked as a serial port 0 sending signal 1 terminal, a serial port 0 receiving signal 2 terminal, a serial port 1 sending signal 3 terminal and a serial port 1 receiving signal 4 terminal; the 4 terminals can realize mutual data communication and test according to 1 jump cap respectively.
The power supply circuit unit is composed of 2 power supply circuit modules, and is respectively used for realizing the power supply of +1.8V level and +3.3V level of the PCIE-to-serial port circuit, and is respectively marked as the +1.8V level power supply circuit module and the +3.3V level power supply circuit module.
The +3.3V level power supply circuit module is composed of a level conversion chip U20, a capacitor C347, a capacitor C350, a capacitor C41, a resistor R502, a resistor R510, a capacitor N2, a capacitor C34, a resistor R499, a capacitor C35, a patch inductor L2, a capacitor C36, a resistor R494, a resistor R495, a capacitor C47, a capacitor C44, a capacitor C29 and a capacitor M29; the level conversion chip U20 is a level conversion chip TPS56428 chip of TI company, and is provided with an EN pin, a PG pin, 2 VREG5 pins, a PWPD pin, 4 GND pins, 2 VIN pins, 2 SW pins, a VBST pin and a VFB pin; one end of the resistor R502 is connected with a +12V power supply, and the other end of the resistor R is connected with the capacitor C41 and then grounded; the connecting point of the resistor R502 and the capacitor C41 is connected with an EN pin; one end of the resistor R510 is connected with the PG pin, and the other end of the resistor R is grounded after being connected with the capacitor N2; the 2 VREG5 pins are connected to the connection point of a resistor R510 and a capacitor N2 after being shorted; the 2 VIN pins are in short circuit and are connected to a +12V power supply; the capacitor C347 and the capacitor C350 are connected in parallel, one end of the capacitor C347 is connected with a +12V power supply, and the other end of the capacitor C347 is grounded; one end of the capacitor C34 is connected with the VBST pin, and the other end of the capacitor C34 is connected with the resistor R499; the 2 SW pins are short-circuited, +3.3V voltage is output, and the SW pins are connected to a resistor R499; the other end of the resistor R499 is connected with a capacitor C35, and then one end of the patch inductor L2 is connected with the resistor R499; the capacitor C36 and the resistor R494 are respectively connected in parallel between the other end of the chip inductor L2 and the VFB pin; one end of the resistor R495 is connected with the VFB pin, and the other end of the resistor R495 is grounded; the capacitor C47, the capacitor C44, the capacitor C29 and the capacitor M29 are connected in parallel, one end of each capacitor C47, one end of each capacitor C44, one end of each capacitor C29 and one end of each capacitor M29 are connected with the 2 SW pins which are mutually short-circuited, and the other end of each capacitor C44.
The +1.8V level power supply circuit module is composed of a level conversion chip U21, a capacitor C346, a capacitor C349, a capacitor C42, a resistor R503, a resistor R511, a capacitor N3, a capacitor C37, a resistor R500, a capacitor C38, a patch inductor L3, a capacitor C39, a resistor R496, a resistor R497, a capacitor C48, a capacitor C45, a capacitor C30 and a capacitor M30; the level conversion chip U21 is a level conversion chip TPS56428 chip of TI company, and is provided with an EN pin, a PG pin, 2 VREG5 pins, a PWPD pin, 4 GND pins, 2 VIN pins, 2 SW pins, a VBST pin and a VFB pin; one end of the resistor R503 is connected with a +12V power supply, and the other end of the resistor R503 is connected with the capacitor C42 and then grounded; the connection point of the resistor R503 and the capacitor C42 is connected with the EN pin; one end of the resistor R511 is connected with the PG pin, and the other end of the resistor R511 is grounded after being connected with the capacitor N3; the 2 VREG5 pins are connected to the connection point of a resistor R511 and a capacitor N3 after being shorted; the 2 VIN pins are in short circuit and are connected to a +12V power supply; the capacitor C346 and the capacitor C349 are connected in parallel, one end of the capacitor C349 is connected with a +12V power supply, and the other end of the capacitor C349 is grounded; one end of the capacitor C37 is connected with the VBST pin, and the other end of the capacitor C37 is connected with the resistor R500; the 2 SW pins are short-circuited, +1.8V voltage is output, and the SW pins are connected to a resistor R500; the other end of the resistor R500 is connected with a capacitor C38 and then grounded; one end of the chip inductor L2 is connected with a resistor R500; the capacitor C39 and the resistor R496 are respectively connected in parallel between the other end of the chip inductor L2 and the VFB pin; one end of the resistor R497 is connected with the VFB pin, and the other end of the resistor R497 is grounded; the capacitor C48, the capacitor C45, the capacitor C30 and the capacitor M30 are connected in parallel, one end of each capacitor C48, one end of each capacitor C45, one end of each capacitor C30 and one end of each capacitor M30 are connected with the 2 SW pins which are mutually short-circuited, and the other end of each capacitor C45.
A communication test method of PCIE signal expansion equipment is characterized in that the test method comprises a serial port self test and a serial port opposite test; wherein,
the test method for the serial port self-test comprises the following steps:
(1) connecting a PC (personal computer) with the PCIE signal expansion equipment to be tested, and connecting the PCIE signal expansion equipment to be tested with the PCIE signal expansion equipment;
(2) driving PCIE signal expansion equipment to test serial port communication;
(3) the PCIE bus interface circuit unit is connected with the PCIE signal expansion equipment to be tested, and converts the PCIE signal into 2 paths of serial port signals which are a serial port 0 signal and a serial port 1 signal respectively through the PCIE-to-serial port circuit unit;
(4) connecting pin connector terminals in a serial port test circuit unit, wherein 1 hop caps are connected with a serial port 0 sending signal 1 terminal and a serial port 0 receiving signal 2 terminal, and the other hop cap is connected with a serial port 1 sending signal 3 terminal and a serial port 1 receiving signal 4 terminal;
(5) opening serial port test software, sending any data to a serial port 0 sending signal 1 terminal, and checking whether a serial port 0 receiving signal 2 terminal receives data or not; meanwhile, any data is sent to a signal 3 terminal of the serial port 1, and whether a signal 4 terminal of the serial port 1 receives the data is checked; if the data received by the serial port 0 signal receiving 2 terminal is the same as the data sent by the serial port 0 signal sending 1 terminal, and the data received by the serial port 1 signal receiving 4 terminal is the same as the data sent by the serial port 1 signal sending 3 terminal, the communication of the path of PCIEx1 channel of the PCIE signal expansion equipment is proved to be normal, and the serial port self-test is completed;
the serial port test method comprises the following steps:
(1) connecting a PC (personal computer) with the PCIE signal expansion equipment to be tested, and connecting the PCIE signal expansion equipment to be tested with the PCIE signal expansion equipment;
(2) driving PCIE signal expansion equipment to test serial port communication;
(3) the PCIE bus interface circuit unit is connected with the PCIE signal expansion equipment to be tested, and converts the PCIE signal into 2 paths of serial port signals which are a serial port 0 signal and a serial port 1 signal respectively through the PCIE-to-serial port circuit unit;
(4) connecting pin connector terminals in a serial port test circuit unit, wherein 1 hop caps are connected with a serial port 0 sending signal 1 terminal and a serial port 1 sending signal 3 terminal, and the other hop cap is connected with a serial port 0 receiving signal 2 terminal and a serial port 1 receiving signal 4 terminal;
(5) opening serial port test software, sending any data to a serial port 0 sending signal 1 terminal, and checking whether a serial port 1 receiving signal 4 terminal receives data or not; if the data received by the serial port 1 signal receiving 4 terminal is the same as the data sent by the serial port 0 signal sending 1 terminal, the communication of the path of the PCIEx1 channel of the PCIE signal expansion equipment is proved to be normal, and the serial port test is completed.
The invention has the advantages that: the PCIE signal is converted into a serial port signal for communication test, and the test steps are simple; the test platform built by the method only needs one board card for connection, does not need excessive test cables, and is simple in test connection; the device has the advantages of simple structure, easy realization, convenient operation, quick and effective test and high precision.
Drawings
Fig. 1 is a schematic diagram of an overall structure of a PCIE signal expansion device according to the present invention.
Fig. 2 is a schematic structural diagram of an embodiment of a PCIE signal expansion device according to the present invention.
Fig. 3 is a schematic structural diagram of a PCIE bus interface circuit unit in the PCIE signal expansion device according to the present invention.
Fig. 4 is a schematic structural diagram of a PCIE-to-serial port circuit unit in a PCIE signal expansion device according to the present invention.
Fig. 5 is a schematic structural diagram of a serial port test circuit unit in a PCIE signal expansion device according to the present invention.
Fig. 6 is a schematic structural diagram of a power supply circuit unit in a PCIE signal expansion device according to the present invention.
Fig. 7 is a schematic circuit structure diagram of a power supply circuit unit in a PCIE signal expansion device according to the present invention (where 7-a is a +3.3V level power supply circuit module, and 7-b is a +1.8 level power supply circuit module).
Fig. 8 is a schematic diagram of a work flow structure of a communication testing method of a PCIE signal expansion device according to the present invention.
Detailed Description
Example (b): a PCIE signal expansion device, as shown in fig. 1 and fig. 2, is characterized in that it includes a PCIE bus interface circuit unit, a PCIE-to-serial port circuit unit, a serial port test circuit unit, and a power supply circuit unit; the PCIE-to-serial port circuit unit is respectively in bidirectional connection with the PCIE bus interface circuit unit and the serial port test circuit unit; and the power supply circuit unit is connected with the PCIE-to-serial port circuit unit and provides a working power supply for the signal expansion equipment.
The PCIE bus interface circuit unit is used for realizing the input of an extended PCIE signal in PCIE signal extension equipment to be tested and consists of two paths of VPX connectors; one of the connectors is a VPX P0 connector, which is used for realizing the input of a power supply signal, generating a +12V power supply voltage and connecting the power supply voltage with a PCIE-to-serial port circuit unit; the other is a VPX P1 connector used to implement communication of extended PCIE signals in the PCIE signal extension device to be tested, and connected to the PCIE-to-serial port circuit unit, as shown in fig. 3.
The VPX P0 connector is a CPCI Express 254018 connector of ERNI company and can realize the input of a +12V power supply; the VPX P1 connector is a CPCI Express 973028 connector of ERNI corporation, and realizes the input of PCIE signals, as shown in FIG. 3.
The PCIE-to-serial port circuit unit is used for realizing the conversion from a PCIE bus protocol to a serial port bus protocol and consists of a PCIE-to-serial port chip, an EEP chip and a crystal oscillator; one end of the PCIE-to-serial port chip is connected with a VPX P1 connector in a PCIE bus interface circuit unit to realize the communication of PCIE signals, and the other end of the PCIE-to-serial port chip is connected with a serial port test circuit to realize the communication of serial port signals; the EEP chip is connected with the PCIE-to-serial port chip and used for storing software configuration of the PCIE-to-serial port chip; the crystal oscillator is connected with the PCIE serial port chip to provide clock input, as shown in fig. 4.
The PCIE-to-serial port chip adopts a PI7C9X795 chip of DIODES company to complete the conversion from a PCIE bus protocol of X1 to a 2-path serial port bus protocol; the EEP chip is AT93C56 chip of ATMEL company; the crystal oscillator is a ZPB-26-14.7456MHz crystal oscillator of Tangshan finishing company, as shown in FIG. 4.
The serial port test circuit is used for realizing serial port signal test connection in different test modes and is composed of a test connector; the test connector is composed of 12 x2 2.54mm pin connector and 2 jump caps; the pin connector is provided with 4 terminals which are respectively marked as a serial port 0 sending signal 1 terminal, a serial port 0 receiving signal 2 terminal, a serial port 1 sending signal 3 terminal and a serial port 1 receiving signal 4 terminal; the 4 terminals can realize mutual data communication and test according to 1 jump cap respectively, as shown in fig. 5.
The power supply circuit is composed of 2 power supply circuit modules, and is respectively used for realizing power supply to the +1.8V level and the +3.3V level of the PCIE-to-serial port circuit, and is respectively referred to as a +1.8V level power supply circuit module and a +3.3V level power supply circuit module, as shown in fig. 6 and fig. 7.
The +3.3V level power supply circuit module is composed of a level conversion chip U20, a capacitor C347, a capacitor C350, a capacitor C41, a resistor R502, a resistor R510, a capacitor N2, a capacitor C34, a resistor R499, a capacitor C35, a patch inductor L2, a capacitor C36, a resistor R494, a resistor R495, a capacitor C47, a capacitor C44, a capacitor C29 and a capacitor M29, and is shown in FIG. 7-a; the level conversion chip U20 is a level conversion chip TPS56428 chip of TI company, and is provided with an EN pin, a PG pin, 2 VREG5 pins, a PWPD pin, 4 GND pins, 2 VIN pins, 2 SW pins, a VBST pin and a VFB pin; one end of the resistor R502 is connected with a +12V power supply, and the other end of the resistor R is connected with the capacitor C41 and then grounded; the connecting point of the resistor R502 and the capacitor C41 is connected with an EN pin; one end of the resistor R510 is connected with the PG pin, and the other end of the resistor R is grounded after being connected with the capacitor N2; the 2 VREG5 pins are connected to the connection point of a resistor R510 and a capacitor N2 after being shorted; the 2 VIN pins are in short circuit and are connected to a +12V power supply; the capacitor C347 and the capacitor C350 are connected in parallel, one end of the capacitor C347 is connected with a +12V power supply, and the other end of the capacitor C347 is grounded; one end of the capacitor C34 is connected with the VBST pin, and the other end of the capacitor C34 is connected with the resistor R499; the 2 SW pins are short-circuited, +3.3V voltage is output, and the SW pins are connected to a resistor R499; the other end of the resistor R499 is connected with a capacitor C35, and then one end of the patch inductor L2 is connected with the resistor R499; the capacitor C36 and the resistor R494 are respectively connected in parallel between the other end of the chip inductor L2 and the VFB pin; one end of the resistor R495 is connected with the VFB pin, and the other end of the resistor R495 is grounded; the capacitor C47, the capacitor C44, the capacitor C29 and the capacitor M29 are connected in parallel, one end of each capacitor C47, one end of each capacitor C44, one end of each capacitor C29 and one end of each capacitor M29 are connected with the 2 SW pins which are mutually short-circuited, and the other end of each capacitor C44.
The +1.8V level power supply circuit module is composed of a level conversion chip U21, a capacitor C346, a capacitor C349, a capacitor C42, a resistor R503, a resistor R511, a capacitor N3, a capacitor C37, a resistor R500, a capacitor C38, a patch inductor L3, a capacitor C39, a resistor R496, a resistor R497, a capacitor C48, a capacitor C45, a capacitor C30 and a capacitor M30, as shown in FIG. 7-b; the level conversion chip U21 is a level conversion chip TPS56428 chip of TI company, and is provided with an EN pin, a PG pin, 2 VREG5 pins, a PWPD pin, 4 GND pins, 2 VIN pins, 2 SW pins, a VBST pin and a VFB pin; one end of the resistor R503 is connected with a +12V power supply, and the other end of the resistor R503 is connected with the capacitor C42 and then grounded; the connection point of the resistor R503 and the capacitor C42 is connected with the EN pin; one end of the resistor R511 is connected with the PG pin, and the other end of the resistor R511 is grounded after being connected with the capacitor N3; the 2 VREG5 pins are connected to the connection point of a resistor R511 and a capacitor N3 after being shorted; the 2 VIN pins are in short circuit and are connected to a +12V power supply; the capacitor C346 and the capacitor C349 are connected in parallel, one end of the capacitor C349 is connected with a +12V power supply, and the other end of the capacitor C349 is grounded; one end of the capacitor C37 is connected with the VBST pin, and the other end of the capacitor C37 is connected with the resistor R500; the 2 SW pins are short-circuited, +1.8V voltage is output, and the SW pins are connected to a resistor R500; the other end of the resistor R500 is connected with a capacitor C38 and then grounded; one end of the chip inductor L2 is connected with a resistor R500; the capacitor C39 and the resistor R496 are respectively connected in parallel between the other end of the chip inductor L2 and the VFB pin; one end of the resistor R497 is connected with the VFB pin, and the other end of the resistor R497 is grounded; the capacitor C48, the capacitor C45, the capacitor C30 and the capacitor M30 are connected in parallel, one end of each capacitor C48, one end of each capacitor C45, one end of each capacitor C30 and one end of each capacitor M30 are connected with the 2 SW pins which are mutually short-circuited, and the other end of each capacitor C45.
A communication test method for PCIE signal expansion devices, as shown in fig. 8, is characterized in that the test method includes a serial port self test and a serial port counter test; wherein,
the test method for the serial port self-test comprises the following steps:
(1) connecting a PC (personal computer) with the PCIE signal expansion equipment to be tested, and connecting the PCIE signal expansion equipment to be tested with the PCIE signal expansion equipment;
(2) driving PCIE signal expansion equipment to test serial port communication;
(3) the PCIE bus interface circuit unit is connected with the PCIE signal expansion equipment to be tested, and converts the PCIE signal into 2 paths of serial port signals which are a serial port 0 signal and a serial port 1 signal respectively through the PCIE-to-serial port circuit unit;
(4) connecting pin connector terminals in a serial port test circuit unit, wherein 1 hop caps are connected with a serial port 0 sending signal 1 terminal and a serial port 0 receiving signal 2 terminal, and the other hop cap is connected with a serial port 1 sending signal 3 terminal and a serial port 1 receiving signal 4 terminal;
(5) opening serial port test software, sending any data to a serial port 0 sending signal 1 terminal, and checking whether a serial port 0 receiving signal 2 terminal receives data or not; meanwhile, any data is sent to a signal 3 terminal of the serial port 1, and whether a signal 4 terminal of the serial port 1 receives the data is checked; if the data received by the serial port 0 signal receiving 2 terminal is the same as the data sent by the serial port 0 signal sending 1 terminal, and the data received by the serial port 1 signal receiving 4 terminal is the same as the data sent by the serial port 1 signal sending 3 terminal, the communication of the path of PCIEx1 channel of the PCIE signal expansion equipment is proved to be normal, and the serial port self-test is completed;
the serial port test method comprises the following steps:
(1) connecting a PC (personal computer) with the PCIE signal expansion equipment to be tested, and connecting the PCIE signal expansion equipment to be tested with the PCIE signal expansion equipment;
(2) driving PCIE signal expansion equipment to test serial port communication;
(3) the PCIE bus interface circuit unit is connected with the PCIE signal expansion equipment to be tested, and converts the PCIE signal into 2 paths of serial port signals which are a serial port 0 signal and a serial port 1 signal respectively through the PCIE-to-serial port circuit unit;
(4) connecting pin connector terminals in a serial port test circuit unit, wherein 1 hop caps are connected with a serial port 0 sending signal 1 terminal and a serial port 1 sending signal 3 terminal, and the other hop cap is connected with a serial port 0 receiving signal 2 terminal and a serial port 1 receiving signal 4 terminal;
(5) opening serial port test software, sending any data to a serial port 0 sending signal 1 terminal, and checking whether a serial port 1 receiving signal 4 terminal receives data or not; if the data received by the serial port 1 signal receiving 4 terminal is the same as the data sent by the serial port 0 signal sending 1 terminal, the communication of the path of the PCIEx1 channel of the PCIE signal expansion equipment is proved to be normal, and the serial port test is completed.
The present invention will be described in further detail with reference to the following examples and the accompanying drawings.
Referring to fig. 1, a method for testing communication of PCIE signal expansion devices includes: the system comprises a PCIE bus interface circuit, a PCIE-to-serial port circuit, a serial port test circuit and a power supply circuit. The PCIE bus interface circuit is connected with the PCIE-to-serial port circuit, the PCIE-to-serial port circuit is connected with the serial port test circuit, and the power supply circuit is connected with the PCIE-to-serial port circuit.
Referring to fig. 3, the PCIE bus interface circuit of the implementation circuit of the method of the present invention includes a VPX connector, which is used to implement input of a power signal and input of an extended PCIE signal in a PCIE signal extension device to be tested, and specifically, the input of a +12V power supply may be implemented by using a CPCI Express 254018 connector of an ERNI company, and the input of a PCIE signal is implemented by using a CPCI Express 973028 connector.
Referring to fig. 4, the PCIE-to-serial port circuit of the implementation circuit of the method of the present invention is used to implement conversion from a PCIE bus protocol to a serial bus protocol, and includes a PCIE-to-serial port chip, an EEP chip, and a crystal oscillator, and specifically, a PI7C9X795 chip of the diode company may be used to complete conversion from a PCIE bus protocol of one path X1 to a serial bus protocol of 2 paths, the EEP chip is used to store software configuration of the PI7C9X795 chip, an AT93C56 chip of the ATMEL company may be specifically selected, and the crystal oscillator provides a clock input for the PI7C9X795 chip, and specifically, a ZPB-26-14.7456MHz crystal oscillator of the tangshan ruin company may be used.
Referring to fig. 5, the serial port test circuit of the circuit implementing method of the invention is used for implementing serial port signal test connection under different test modes, and includes a test connector, and specifically, a 2x2 2.54mm pin connector and a jumper cap can be used to implement switching of connection relation required by test, in the serial port test circuit, pin 1 of the 2x2 2.54mm pin connector is connected with serial port 0 sending signal, pin 2 is connected with serial port 0 receiving signal, pin 3 is connected with serial port 1 receiving signal, pin 4 is connected with serial port 1 receiving signal, during test: one jump cap is adopted to connect the pins 1 and 2, and the other jump cap is adopted to connect the pins 3 and 4, so that the communication self-test of the serial port 0 and the communication self-test of the serial port 1 can be realized; one jump cap is adopted to connect pins 1 and 3, and the other jump cap is adopted to connect pins 2 and 4, so that the communication pair test received by the serial port 1 sent by the serial port 0 and the communication pair test received by the serial port 0 sent by the serial port 1 can be realized;
referring to fig. 6, the power supply circuit of the implementation circuit of the method of the present invention is used to implement power supply of +1.8Vaux level, +1.8V level, and +3.3V level of a PCIE to serial port circuit, and includes a level conversion chip, an inductor, a resistor, and a capacitor, and specifically, may implement level conversion by using a TPS56428 chip of the company TI to respectively complete conversion from +12V level to +1.8V level and from +12V level to +3.3V level.
The self-testing method comprises the following steps:
the method comprises the following steps: referring to fig. 5, in a 2.54mm pin connector of a serial port test circuit 2x2, one jumper cap is used to connect 1, 2 pins and the other jumper cap is used to connect 3,4 pins.
Step two: referring to fig. 8, a PC is connected to the PCIE signal expansion device to be tested, and the PCIE signal expansion device to be tested is connected to the circuit of the present invention.
Step three: and installing PCIE signal expansion equipment software driver and serial port test software.
Step four: the method comprises the steps of opening serial port test software, sending any data to a serial port 0, checking data received by the serial port 0, sending any data to a serial port 1, checking data received by the serial port 1, and when the data received by the serial port 0 is the same as the data sent by the serial port 0 and the data received by the serial port 1 is the same as the data sent by the serial port 1, proving that the communication of the PCIEx1 channel of the PCIE signal expansion equipment is normal.
The opposite side test method of the invention comprises the following steps:
the method comprises the following steps: referring to fig. 4, in a 2.54mm pin connector of the serial port test circuit 2x2, one jumper cap is used to connect 1, 3 pins and the other jumper cap is used to connect 2,4 pins.
Step two: referring to fig. 6, a PC is connected to the PCIE signal expansion device to be tested, and the PCIE signal expansion device to be tested is connected to the circuit of the present invention.
Step three: and installing PCIE signal expansion equipment software driver and serial port test software.
Step four: the method comprises the steps of opening serial port test software, sending any data to a serial port 0, checking data received by a serial port 1, sending any data to the serial port 1, checking data received by the serial port 0, and when the data received by the serial port 1 is the same as the data sent by the serial port 0 and the data received by the serial port 0 is the same as the data sent by the serial port 1, proving that the communication of the PCIEx1 channel of the PCIE signal expansion equipment is normal.
Referring to fig. 2, according to the number of channels of the PCIE signal expansion device to be tested, multiple sets of the circuits of the present invention may be integrated on the same board card to implement the communication test of the multi-channel PCIE signal of the PCIE signal expansion device, where the implementation circuit of the integration method includes: the system comprises a PCIE bus interface circuit, a PCIE-to-serial port circuit, a serial port test circuit and a power supply circuit. The PCIE bus interface circuit is connected with the PCIE-to-serial port circuit, the PCIE-to-serial port circuit is connected with the serial port test circuit, and the power supply circuit is connected with the PCIE-to-serial port circuit.
The PCIE bus interface circuit of the implementation circuit of the method is used for realizing the input of the extended PCIE signals in the N paths of PCIE signal extension equipment to be tested, and particularly can adopt a CPCI Express 973028 connector of an ERNI company to realize the input of the PCIE signals.
The PCIE-to-serial port circuit of the implementation circuit is used for realizing the conversion from the N-path PCIE bus protocol to the serial port bus protocol, and particularly can adopt N pieces of PI7C9X795 chips of DIODES company to complete the conversion from the N-path PCIE X1 bus protocol to the 2N-path serial port bus protocol.
The serial port test circuit of the circuit is used for realizing 2N serial port signal test connection in different test modes, and particularly, a 2.54mm pin connector and a jump cap of 2x2 can be adopted to realize the switching of connection conversion systems required by test.
The power supply circuit of the implementation circuit of the method is used for realizing the power supply of the +1.8Vaux level, +1.8V level and +3.3V level of a PCIE-to-serial port circuit, specifically, a CPCI-E UPM 254018 connector of an ERNI company is adopted to realize the introduction of a +12V power supply, and TPS56428 chips of 3 TI companies are adopted to realize level conversion, so that the conversion from the +12V level to the +1.8Vaux level, the conversion from the +12V level to the +1.8V level and the conversion from the +12V level to the +3.3V level are respectively completed.
Claims (10)
1. A PCIE signal expansion device is characterized by comprising a PCIE bus interface circuit unit, a PCIE-to-serial port circuit unit, a serial port test circuit unit and a power supply circuit unit; the PCIE-to-serial port circuit unit is respectively in bidirectional connection with the PCIE bus interface circuit unit and the serial port test circuit unit; and the power supply circuit unit is connected with the PCIE-to-serial port circuit unit and provides a working power supply for the signal expansion equipment.
2. The PCIE signal expansion device according to claim 1, wherein the PCIE bus interface circuit unit is configured to implement input of an expansion PCIE signal in the PCIE signal expansion device to be tested, and is composed of two paths of VPX connectors; one of the connectors is a VPX P0 connector, which is used for realizing the input of a power supply signal, generating a +12V power supply voltage and connecting the power supply voltage with a PCIE-to-serial port circuit unit; the other is a VPX P1 connector which is used for realizing the communication of the extended PCIE signals in the PCIE signal extension equipment to be tested and is connected with the PCIE-to-serial port circuit unit.
3. The PCIE signal expansion device of claim 2 wherein the VPX P0 connector is a CPCI Express 254018 connector from ERNI corporation, which can realize the input of +12V power; the VPX P1 connector is a CPCI Express 973028 connector of ERNI company and realizes the input of PCIE signals.
4. The PCIE signal expansion device according to claim 1, wherein the PCIE-to-serial port circuit unit is configured to implement conversion from a PCIE-to-serial port protocol to a serial port bus protocol, and is composed of a PCIE-to-serial port chip, an EEP chip, and a crystal oscillator; one end of the PCIE-to-serial port chip is connected with a VPX P1 connector in a PCIE bus interface circuit unit to realize the communication of PCIE signals, and the other end of the PCIE-to-serial port chip is connected with a serial port test circuit to realize the communication of serial port signals; the EEP chip is connected with the PCIE-to-serial port chip and used for storing software configuration of the PCIE-to-serial port chip; the crystal oscillator is connected with the PCIE serial port chip and used for providing clock input.
5. The PCIE signal expansion equipment of claim 4, wherein the PCIE-to-serial port chip adopts a PI7C9X795 chip of DIODES company to complete the conversion from one path of PCIE bus protocol of X1 to a 2-path serial port bus protocol; the EEP chip is AT93C56 chip of ATMEL company; the crystal oscillator is a ZPB-26-14.7456MHz crystal oscillator of Tangshan finishing company.
6. The PCIE signal expansion device according to claim 1, wherein the serial port test circuit unit is used to implement serial port signal test connection in different test modes, and is composed of a test connector; the test connector is composed of 12 x2 2.54mm pin connector and 2 jump caps; the pin connector is provided with 4 terminals which are respectively marked as a serial port 0 sending signal 1 terminal, a serial port 0 receiving signal 2 terminal, a serial port 1 sending signal 3 terminal and a serial port 1 receiving signal 4 terminal; the 4 terminals can realize mutual data communication and test according to 1 jump cap respectively.
7. The PCIE signal expansion device according to claim 1, wherein the power supply circuit unit is composed of 2 power supply circuit modules, and is respectively configured to implement power supply to a +1.8V level and a +3.3V level of the PCIE-to-serial port circuit, and these power supply circuit modules are respectively referred to as a +1.8V level power supply circuit module and a +3.3V level power supply circuit module.
8. The PCIE signal expansion device of claim 7, wherein the +3.3V level power supply circuit module is composed of a level conversion chip U20, a capacitor C347, a capacitor C350, a capacitor C41, a resistor R502, a resistor R510, a capacitor N2, a capacitor C34, a resistor R499, a capacitor C35, a patch inductor L2, a capacitor C36, a resistor R494, a resistor R495, a capacitor C47, a capacitor C44, a capacitor C29 and a capacitor M29; the level conversion chip U20 is a level conversion chip TPS56428 chip of TI company, and is provided with an EN pin, a PG pin, 2 VREG5 pins, a PWPD pin, 4 GND pins, 2 VIN pins, 2 SW pins, a VBST pin and a VFB pin; one end of the resistor R502 is connected with a +12V power supply, and the other end of the resistor R is connected with the capacitor C41 and then grounded; the connecting point of the resistor R502 and the capacitor C41 is connected with an EN pin; one end of the resistor R510 is connected with the PG pin, and the other end of the resistor R is grounded after being connected with the capacitor N2; the 2 VREG5 pins are connected to the connection point of a resistor R510 and a capacitor N2 after being shorted; the 2 VIN pins are in short circuit and are connected to a +12V power supply; the capacitor C347 and the capacitor C350 are connected in parallel, one end of the capacitor C347 is connected with a +12V power supply, and the other end of the capacitor C347 is grounded; one end of the capacitor C34 is connected with the VBST pin, and the other end of the capacitor C34 is connected with the resistor R499; the 2 SW pins are short-circuited, +3.3V voltage is output, and the SW pins are connected to a resistor R499; the other end of the resistor R499 is connected with a capacitor C35, and then one end of the patch inductor L2 is connected with the resistor R499; the capacitor C36 and the resistor R494 are respectively connected in parallel between the other end of the chip inductor L2 and the VFB pin; one end of the resistor R495 is connected with the VFB pin, and the other end of the resistor R495 is grounded; the capacitor C47, the capacitor C44, the capacitor C29 and the capacitor M29 are connected in parallel, one end of each capacitor C47, one end of each capacitor C44, one end of each capacitor C29 and one end of each capacitor M29 are connected with the 2 SW pins which are mutually short-circuited, and the other end of each capacitor C44.
9. The PCIE signal expansion apparatus of claim 1, wherein the +1.8V level power supply circuit module is composed of a level conversion chip U21, a capacitor C346, a capacitor C349, a capacitor C42, a resistor R503, a resistor R511, a capacitor N3, a capacitor C37, a resistor R500, a capacitor C38, a patch inductor L3, a capacitor C39, a resistor R496, a resistor R497, a capacitor C48, a capacitor C45, a capacitor C30, and a capacitor M30; the level conversion chip U21 is a level conversion chip TPS56428 chip of TI company, and is provided with an EN pin, a PG pin, 2 VREG5 pins, a PWPD pin, 4 GND pins, 2 VIN pins, 2 SW pins, a VBST pin and a VFB pin; one end of the resistor R503 is connected with a +12V power supply, and the other end of the resistor R503 is connected with the capacitor C42 and then grounded; the connection point of the resistor R503 and the capacitor C42 is connected with the EN pin; one end of the resistor R511 is connected with the PG pin, and the other end of the resistor R511 is grounded after being connected with the capacitor N3; the 2 VREG5 pins are connected to the connection point of a resistor R511 and a capacitor N3 after being shorted; the 2 VIN pins are in short circuit and are connected to a +12V power supply; the capacitor C346 and the capacitor C349 are connected in parallel, one end of the capacitor C349 is connected with a +12V power supply, and the other end of the capacitor C349 is grounded; one end of the capacitor C37 is connected with the VBST pin, and the other end of the capacitor C37 is connected with the resistor R500; the 2 SW pins are short-circuited, +1.8V voltage is output, and the SW pins are connected to a resistor R500; the other end of the resistor R500 is connected with a capacitor C38 and then grounded; one end of the chip inductor L2 is connected with a resistor R500; the capacitor C39 and the resistor R496 are respectively connected in parallel between the other end of the chip inductor L2 and the VFB pin; one end of the resistor R497 is connected with the VFB pin, and the other end of the resistor R497 is grounded; the capacitor C48, the capacitor C45, the capacitor C30 and the capacitor M30 are connected in parallel, one end of each capacitor C48, one end of each capacitor C45, one end of each capacitor C30 and one end of each capacitor M30 are connected with the 2 SW pins which are mutually short-circuited, and the other end of each capacitor C45.
10. A communication test method of PCIE signal expansion equipment is characterized in that the test method comprises a serial port self test and a serial port opposite test; wherein,
the test method for the serial port self-test comprises the following steps:
(1) connecting a PC (personal computer) with the PCIE signal expansion equipment to be tested, and connecting the PCIE signal expansion equipment to be tested with the PCIE signal expansion equipment;
(2) driving PCIE signal expansion equipment to test serial port communication;
(3) the PCIE bus interface circuit unit is connected with the PCIE signal expansion equipment to be tested, and converts the PCIE signal into 2 paths of serial port signals which are a serial port 0 signal and a serial port 1 signal respectively through the PCIE-to-serial port circuit unit;
(4) connecting pin connector terminals in a serial port test circuit unit, wherein 1 hop caps are connected with a serial port 0 sending signal 1 terminal and a serial port 0 receiving signal 2 terminal, and the other hop cap is connected with a serial port 1 sending signal 3 terminal and a serial port 1 receiving signal 4 terminal;
(5) opening serial port test software, sending any data to a serial port 0 sending signal 1 terminal, and checking whether a serial port 0 receiving signal 2 terminal receives data or not; meanwhile, any data is sent to a signal 3 terminal of the serial port 1, and whether a signal 4 terminal of the serial port 1 receives the data is checked; if the data received by the serial port 0 signal receiving 2 terminal is the same as the data sent by the serial port 0 signal sending 1 terminal, and the data received by the serial port 1 signal receiving 4 terminal is the same as the data sent by the serial port 1 signal sending 3 terminal, the communication of the path of PCIEx1 channel of the PCIE signal expansion equipment is proved to be normal, and the serial port self-test is completed;
the serial port test method comprises the following steps:
(1) connecting a PC (personal computer) with the PCIE signal expansion equipment to be tested, and connecting the PCIE signal expansion equipment to be tested with the PCIE signal expansion equipment;
(2) driving PCIE signal expansion equipment to test serial port communication;
(3) the PCIE bus interface circuit unit is connected with the PCIE signal expansion equipment to be tested, and converts the PCIE signal into 2 paths of serial port signals which are a serial port 0 signal and a serial port 1 signal respectively through the PCIE-to-serial port circuit unit;
(4) connecting pin connector terminals in a serial port test circuit unit, wherein 1 hop caps are connected with a serial port 0 sending signal 1 terminal and a serial port 1 sending signal 3 terminal, and the other hop cap is connected with a serial port 0 receiving signal 2 terminal and a serial port 1 receiving signal 4 terminal;
(5) opening serial port test software, sending any data to a serial port 0 sending signal 1 terminal, and checking whether a serial port 1 receiving signal 4 terminal receives data or not; if the data received by the serial port 1 signal receiving 4 terminal is the same as the data sent by the serial port 0 signal sending 1 terminal, the communication of the path of the PCIEx1 channel of the PCIE signal expansion equipment is proved to be normal, and the serial port test is completed.
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Application publication date: 20190219 |