CN109358475A

CN109358475A - Alignment mark, mask plate and preparation method thereof

Info

Publication number: CN109358475A
Application number: CN201811476860.7A
Authority: CN
Inventors: 汪际军
Original assignee: Qualper Optoelectronics Technology (shanghai) Co Ltd
Current assignee: Quanpu Semiconductor Technology (shenzhen) Co Ltd
Priority date: 2018-12-05
Filing date: 2018-12-05
Publication date: 2019-02-19

Abstract

The present invention provides a kind of alignment marks, mask plate and preparation method thereof, and alignment mark and alignment are arranged in every layer of mask plate, realize layered mask plate overlay alignment；Further, it is provided in each exposure mask plate and at least connects an alignment mark, in alignment mark in each straton exposure mask plate, have one it is identical as the alignment mark of upper adjacent layer, it is identical as the alignment mark of lower adjacent layer there is one, so that precisely aligning for layered mask version is realized, under high integration small size figure, alignment precision is improved, device quality is improved.

Description

Alignment mark, mask and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to an alignment mark, a mask with the alignment mark and a preparation method of the mask.

Background

A conventional MEMS chip includes a scanning micro-mirror and a scanning platform. And a peripheral circuit board is arranged on the periphery of the MEMS chip structure, the peripheral circuit is electrically connected with the MEMS chip structure, and the peripheral circuit comprises a controller circuit and the like. In the MEMS chip structure, the scanning micro-mirror is coupled to the scanning platform. The scanning platform can move under the action of the driving excitation and the magnetic field, and the controller controls the moving direction and the position of the scanning platform. The scanning micromirror is capable of rotating along a rotation axis. In the traditional device, each peripheral circuit is exclusively provided with a circuit board and is electrically connected with the MEMS chip structure by adopting a lead or a metal wire, so that the volume of the final product device is larger. With the progress of modern science and technology life, miniaturized and portable products are more and more favored. Meanwhile, higher requirements are also put on the feedback rate, the image definition and the like of the electric device.

In addition, the MEMS chip structure inevitably employs a multi-layer structure and an overlay process, which easily causes overlay accuracy errors between multi-layer masks, and particularly, when the MEMS chip structure is integrated with the MEMS chip structure by removing peripheral circuits, the structure size of each functional region in the MEMS chip structure is greatly reduced, and a slight deviation during overlay may be unimportant compared to a conventional device.

Disclosure of Invention

In order to overcome the above problems, the present invention aims to provide an alignment mark and a method for manufacturing a mask using the alignment mark, thereby improving the alignment precision in chip manufacturing with improved integration.

In order to achieve the above object, the present invention provides an alignment mark for multi-layer mask overlay, wherein in the stacked arrangement of multi-layer mask layers, the alignment mark in each layer of mask from bottom to top is corresponding and aligned.

Preferably, the alignment marks adjacent up and down correspond to each other, and at least two alignment marks are arranged in each reticle layer.

Preferably, the alignment mark patterns in each reticle layer are different or the patterns are the same but different in size.

Preferably, in the stacking arrangement of the mask layers, the alignment marks in each mask layer from bottom to top are sequentially increased in size, each alignment mark in the same mask layer is sequentially increased in size, at least one alignment mark in the upper and lower adjacent mask layers has the same size, and the alignment marks with the same size are used for overlapping alignment.

Preferably, in the case that at least two alignment mark patterns in each reticle layer are different, at least one alignment mark pattern and the same size in the upper and lower adjacent reticle layers in the stacked arrangement of the reticle layers are used for overlapping alignment.

Preferably, when three or more alignment marks are provided in each reticle layer, one of the alignment marks is the same as the alignment mark of the upper adjacent layer, one of the alignment marks is the same as the alignment mark of the lower adjacent layer, and the remaining one or more alignment marks are the same as the alignment marks of the other non-adjacent layers.

Preferably, the pattern of alignment marks is a circular ring.

Preferably, the pattern of the alignment mark is a straight line.

Preferably, the pattern of alignment marks is composed of a word and a ring disposed around the word.

In order to achieve the above object, the present invention further provides a mask having the alignment mark of any one of the above aspects.

In order to achieve the above object, the present invention further provides a method for preparing a mask having the above alignment mark, comprising:

step I: forming a word pattern in the mask layer;

step II: and forming a circular ring pattern on the periphery of the straight pattern.

Preferably, the mask is etched in step I and step II by using an electron beam or a laser.

According to the alignment mark, the alignment mark is arranged in each layer of mask and aligned, so that the alignment of the registration of multiple layers of masks is realized; furthermore, at least two alignment marks are arranged in each mask layer, one alignment mark in each sub-mask layer is the same as that of the upper adjacent layer, and the other alignment mark in each sub-mask layer is the same as that of the lower adjacent layer, so that accurate alignment of the multi-layer masks is realized, the alignment precision is improved and the device quality is improved under high-integration small-size patterns.

Drawings

FIG. 1 is a schematic diagram of a MEMS chip structure according to an embodiment of the present invention

FIG. 2 is a schematic diagram of a mask of a MEMS chip structure according to an embodiment of the present invention

FIG. 3 is a schematic diagram of an alignment mark according to an embodiment of the present invention

FIG. 4 is a schematic diagram of an alignment mark according to another embodiment of the present invention

FIG. 5 is a schematic top view of a MEMS device of one embodiment of the present invention

FIG. 6 is a schematic cross-sectional structure diagram of a MEMS device according to an embodiment of the invention

Detailed Description

In order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.

The present invention will be described in further detail with reference to the accompanying drawings 1 to 6 and specific examples. It should be noted that the drawings are in a simplified form and are not to precise scale, and are only used for conveniently and clearly achieving the purpose of assisting in describing the embodiment.

Referring to fig. 1, in the MEMS chip structure of the present embodiment, the MEMS main device 01 and the MEMS auxiliary device 02 are both on the same chip 00.

The MEMS master 01 is used to reflect the light beam and scan the image. Specifically, the MEMS main element 01 has a mirror 103 and a magneto-electric element, the mirror 103 is connected to a first direction axis 101, and a second direction axis 102 is connected to a gimbal outside the mirror 103; the mirror 103 can rotate along the first direction axis 101 or rotate along the second direction axis 102 under the interaction of the magneto-electric component and the external magnetic field, and reflects light; the first direction is different from the second direction, and preferably, the first direction is perpendicular to the second direction. In the MEMS main element, the mirror 103 is deflected along the first direction axis 101 or deflected along the second direction axis 102 by the magnetic field and the driving circuit element, and the reflection is in a grating pattern. Essentially, the MEMS chip structure referred to in the present invention refers to a MEMS scanning micro-mirror structure chip in a narrow sense.

In this embodiment, the MEMS auxiliary element 02 may be, but is not limited to being, disposed around the MEMS main element 01. The MEMS auxiliary element 02 includes: the drive circuit element, the logic operation element, the CPU central processing element, the power supply, and in addition, the memory element can be further arranged.

Specifically, one end of the driving circuit element is connected to an external component, and the other end of the driving circuit element is electrically connected to a circuit of the MEMS mirror 103, so as to provide driving power and control the operation of the external component and the MEMS mirror 103. And the logic operation element is connected with the drive circuit element and is used for performing logic operation and controlling the on-off of the drive circuit element. The CPU central processing element has one end connected to the external element and the other end connected electrically to the drive circuit element, the logic operation element, the power supply and the memory element, and is used to send signal to the drive circuit element, the logic operation element, the memory element and the power supply and control the logic relation among the drive circuit element, the logic operation element, the memory element and the power supply; in addition, the CPU central processing element can also be used for controlling the logic relation of external components.

In this embodiment, one end of the power supply is connected to an external component, and the other end is electrically connected to the MEMS mirror 103, the driving circuit component, the logic operation component, and the CPU central processing component, and is configured to provide electric energy to each component or the outside. Here, one end of the storage element is connected with the power supply, and the other end of the storage element is connected with an external component and used for storing data sent by the external component.

It should be noted that, the MEMS chip structure of this embodiment has elements such as a processor, a logic operation, and a memory, and thus, a peripheral circuit board other than the conventional chip structure is not required, and the space of the device is significantly reduced.

The overall dimensions of the MEMS chip structure of the present embodiment, such as length or width, are not greater than 2cm, and the area is not greater than 4cm². Therefore, the MEMS chip structure of the embodiment greatly changes the occupied space of the existing MEMS-based device, reduces the volume of the device, and enables the miniaturization, ultra-thin and ultra-light of the device to be possible.

The MEMS auxiliary elements 02 are provided around the MEMS main element 01, that is, the scanning mirror micro-mirror structure, so that the influence of mutual interference between the respective circuits of the MEMS main element 01 and the MEMS auxiliary elements 02 around the MEMS main element 01 is avoided, and it is preferable that the distance between the edge of the MEMS main element 01 and the edge of the MEMS auxiliary element 02 is not less than 1/2 of the width of each MEMS auxiliary element 02. Further, since the MEMS main unit 01 is used for scanning and reflecting the light beam to form a grating, in order to improve the light scanning performance of the entire MEMS chip structure, the size of each MEMS auxiliary element 02 is smaller than that of the MEMS main element 01, which not only improves the chip performance but also improves the chip integration.

In this embodiment, the method for manufacturing the MEMS chip structure may include the following steps:

step 01: designing a target pattern mask;

specifically, referring to fig. 2, the target pattern mask includes a MEMS main device pattern 01 'and a plurality of MEMS auxiliary device patterns 02'. In the present embodiment, the MEMS auxiliary element pattern 02 'may be, but is not limited to, disposed around the MEMS main element pattern 01'. The wrap-around arrangement may be sufficiently arranged according to the MEMS main element pattern 01' to make the chip 00 more integrated. Referring to fig. 1, a first directional axis pattern 101 ', a second directional axis pattern 102', and a mirror pattern 103 'are disposed in the MEMS main element pattern 01' to correspond to the MEMS main element 01. The connection relationship of these patterns is the same as that of the corresponding components in fig. 1, and the description thereof is omitted.

The MEMS auxiliary element 02' pattern comprises: a drive circuit element pattern, a logical operation element pattern, a storage element pattern, a CPU central processing element pattern, a power supply pattern, and a storage element pattern; these patterns correspond to the MEMS auxiliary elements 02' in the MEMS chip structure described above. Specifically, one end of the driving circuit element pattern extends outward for connection with an external component, and the other end is electrically connected to the circuit of the MEMS mirror pattern 103'. The logic operation element pattern is connected with the driving circuit element pattern. One end of the storage element pattern is connected with the power supply pattern, and the other end of the storage element pattern extends outwards to be connected with an external component. One end of the CPU central processing element pattern is extended outwards for being connected with an external component, and the other end of the CPU central processing element pattern is electrically connected with the driving circuit element pattern, the logic operation element pattern, the storage element pattern and the power supply pattern. One end of the power supply pattern extends outwards and is used for being connected with an external component, and the other end of the power supply pattern is connected with the MEMS reflector pattern, the driving circuit element pattern, the logic operation element pattern, the storage element pattern and the CPU central processing element pattern.

In order to improve the etching precision and the auxiliary element pattern transfer precision of each part, the MEMS main element pattern 101 'and the MEMS auxiliary element pattern 102' are respectively disposed on different sub-mask layers, and the sub-mask layers are aligned and stacked to form a final target pattern. Preferably, the driving circuit element pattern, the logic operation element pattern, the storage element pattern, the CPU central processing element pattern, and the power supply pattern are respectively disposed on different sub-mask layers. In the sub-mask layers, each sub-mask layer is provided with an alignment mark for alignment of each sub-mask layer. These sub-reticle layers are stacked to obtain the final target pattern. It should be noted that, when the peripheral circuit is removed and integrated with the MEMS chip structure, the structure size of each functional area in the MEMS chip structure is greatly reduced, and a slight deviation during the alignment may be less important compared to the conventional device, however, for the chip structure integrated with many peripheral circuits, the alignment accuracy between the multi-layer masks is reduced and the quality of the final image product is reduced due to the slight deviation of the alignment accuracy and the deviation of the alignment accuracy.

Aiming at different sub-mask layers, in order to improve the alignment precision, the pattern of the alignment mark is a straight line, or a circular ring arranged around the straight line. The circular rings can provide multi-layer alignment, when one layer is not aligned, the circular rings can be partially overlapped to present a non-circular ring state, and the projected light spots are also in the non-circular ring state, so that the phenomenon is obviously seen; and further arranging a line mark in the circular ring, if the line mark is not aligned in the alignment of the multi-layer sub-mask layers, the multi-layer sub-mask layers are stacked, grids or discrete spots of radiation are formed under a light beam, and therefore the misalignment is obviously judged. Here, referring to FIG. 3, "one" may be located on the diameter of the ring, or in the region of diameters 1/3-1/2 and arranged parallel to the diameter, as shown in FIG. 4. In addition, the position corresponding relation between the first mark and the circular ring in the marks in the sub-mask layers in all the layers is the same.

In addition, in the stacking arrangement of the sub-masks, the alignment marks in each layer of sub-masks from bottom to top are corresponding and aligned one by one. In another embodiment of the present invention, each sub-mask of the MEMS auxiliary element pattern may also have at least two alignment marks disposed in each sub-mask layer. Furthermore, different alignment marks in each layer of the sub-mask layer can be set; the patterns may be different or the patterns may be the same but different sizes.

Aiming at the condition that the alignment mark patterns in each layer of the sub-mask layer are the same but different in size, in the stacking arrangement of the sub-mask layers, the alignment marks in each layer of the sub-mask from bottom to top are sequentially increased in size, all the alignment marks in the same sub-mask layer are sequentially increased in size, at least one alignment mark in the upper and lower adjacent sub-mask layers is the same in size, and the alignment marks with the same size are used for overlapping alignment.

In addition, aiming at the condition that at least two alignment mark patterns in each mask layer are different, at least one alignment mark pattern in the upper and lower adjacent mask layers in the stacking arrangement of the mask layers has the same size, and the alignment marks with the same pattern and size are used for overlapping alignment.

When three or more alignment marks are arranged in each layer of mask layer, one alignment mark is the same as that of the upper adjacent layer, one alignment mark is the same as that of the lower adjacent layer, and the remaining one or more alignment marks are the same as those of other non-adjacent layers, so that the alignment marks in one layer of mask layer can be aligned to not only the upper and lower adjacent layers but also other non-adjacent layers, thereby achieving the multi-layer alignment effect and further improving the alignment precision and the alignment quality.

In addition, the method for preparing the mask with the alignment mark of the ring arranged around the straight line can comprise the following steps: step I: forming a word pattern in the mask layer;

Specifically, the mask may be etched in step I and step II by, but not limited to, electron beam or laser. The material of the mask may be glass with a metal layer, such as chrome.

Step 02: and photoetching and etching processes are carried out by utilizing the target pattern mask plate, and the MEMS main element and the MEMS auxiliary element are formed on the chip.

Specifically, the method comprises a preparation process of the MEMS main element and a preparation process of the MEMS auxiliary element; here, the preparation order of the MEMS main element and the MEMS auxiliary element may be interchanged.

Before preparing the MEMS auxiliary element, shielding the prepared MEMS main element area by using a mask, and then preparing the MEMS auxiliary element; after preparing the MEMS auxiliary element, the mask is removed.

Or,

before preparing the MEMS main element, shielding the prepared MEMS auxiliary element area by using a mask, and then preparing the MEMS main element; after the MEMS main element is prepared, the mask is removed.

Here, the mask may be, but is not limited to, an organic material that is soluble in alcohol.

It should be noted that, because the driving circuit element pattern, the logic operation element pattern, the storage element pattern, the CPU central processing element pattern, and the power supply pattern are respectively disposed on different sub-mask layers; in the sub-mask layers, each sub-mask layer can be provided with an alignment mark for alignment of each sub-mask layer; these sub-reticle layers are stacked to obtain the final target pattern.

In the preparation process of the MEMS auxiliary element, photoetching and etching processes are carried out by adopting the corresponding sub-mask layer, and other areas are shielded by using masks; each layer is first searched and aligned with the alignment mark before photolithography and etching.

In addition, in the present embodiment, referring to fig. 5, a MEMS device is further provided, including: the MEMS chip structure and the field magnet 03 described above; for the structure of the MEMS chip, reference is made to the above description, which is not repeated here.

The field magnet 03 here is arranged at the periphery of the MEMS auxiliary element 02 for providing a magnetic field interaction with the magnetic field of the magneto-electric component. In the present embodiment, the magnetic generating component may be, but is not limited to, an inductive coil or a magnet, such as a magnet.

Specifically, the field magnet 03 is disposed around the periphery of the MEMS auxiliary element 02; in the horizontal plane, the spacing between the MEMS chip structure and the field magnet 03 is greater than the width of the MEMS auxiliary element 02. In this way, it is possible to avoid interference of the circuit in the MEMS auxiliary element 02 with the magnetic field generated by the field magnet 03 and the magnetic field generated by the magnetically-generated component, thereby further avoiding interaction between the magnetic field of the field magnet 03 and the magnetic field of the magnetically-generated component by the MEMS auxiliary element 02. In addition, the size of the MEMS auxiliary element 02 is smaller than the distance between the MEMS chip 00 and the field magnet 03, which in turn prevents the MEMS auxiliary element 02 from being disturbed by the structure of the field magnet and the MEMS main element 01.

In this embodiment, referring to fig. 6 in combination with fig. 1, the field magnet 03 has a vertical portion 301 and a horizontal portion 302. The horizontal part 302 has an upper surface for supporting the MEMS chip 00, and the vertical part 301 has a top higher than the top of the MEMS chip 00. In such an arrangement, when the MEMS chip 00 is not under the action of the magnetic field, the upper surface of the horizontal portion 302 is used for carrying the MEMS chip 00; when a magnetic field is applied to the MEMS chip 00, the MEMS main element 01 in the MEMS chip 00 deflects and starts scanning and reflecting the light beam to form a grating. The scanning process with respect to the deflection of the MEMS main element 01 can refer to the existing two-axis MEMS scanning micro-mirror structure and its operation principle, which are known to those skilled in the art and will not be described herein.

Since the MEMS chip 00 is a fine structure, and the MEMS chip 00 has not only the MEMS main element 01 but also the MEMS auxiliary element 02 in the present embodiment, the MEMS auxiliary element 02 is often disposed around the MEMS main element 01. In particular, the circuit in the MEMS auxiliary element 02 employs multiple interconnect layers, which easily causes the MEMS auxiliary element 02 to be damaged when the MEMS chip 00 falls on the field magnet 03, and affects the device performance, so that a multilayer structure is provided on the upper surface of the horizontal portion 302, and at least includes from bottom to top: buffer layer 3022, and absorbent layer 3021. The buffer layer 3022 plays a role of buffering when the MEMS chip 00 falls. Preferably, the material of the buffer layer 3022 is a flexible material, and the flexible material may be an organic material or a thin film layer having a plurality of pores. In addition, the adsorption layer 3021 is used to adsorb the MEMS chip 00, so as to prevent the MEMS chip 00 from sliding relatively. Preferably, the material of the adsorption layer 3021 may be a graphene film. The graphene thin film may be, but is not limited to, a single-layer graphene thin film. By adopting the single-layer graphene film, the surface energy and the adsorption force are improved by utilizing multiple suspension bonds on the surface of the graphene film, and the buffer force can be further improved and the impact force of the MEMS chip 00 in the moving process is reduced because the graphene film has a porous net-shaped structure.

Although the present invention has been described with reference to preferred embodiments, which are illustrated for the purpose of illustration only and not for the purpose of limitation, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. The alignment mark for the alignment of the multi-layer masks is characterized in that the alignment mark in each layer of masks from bottom to top corresponds and aligns in the stacking arrangement of the multi-layer masks.

2. The alignment mark of claim 1, wherein adjacent alignment marks correspond to each other, and at least two alignment marks are provided in each reticle layer.

3. The alignment mark of claim 2, wherein the alignment mark patterns in each reticle layer are different or the patterns are the same but different in size.

4. The alignment mark according to claim 3, wherein, for the case that the alignment mark patterns in each mask layer are the same but different in size, the mask layers are stacked such that the alignment marks in each mask layer from bottom to top sequentially increase in size, and the alignment marks in the same mask layer sequentially increase in size, and at least one alignment mark in the adjacent mask layers above and below has the same size, and the alignment marks having the same size are used for overlay alignment.

5. The alignment mark according to claim 3, wherein at least one alignment mark pattern and the same size in the adjacent reticle layers above and below the reticle layer are used for overlay alignment in the stacking arrangement of the reticle layers for the case that at least two alignment mark patterns in each reticle layer are different.

6. The alignment mark of claim 5, wherein when three or more alignment marks are disposed in each reticle layer, one alignment mark is the same as the alignment mark of an upper adjacent layer, one alignment mark is the same as the alignment mark of a lower adjacent layer, and the remaining one or more alignment marks are the same as the alignment marks of other non-adjacent layers.

7. The alignment mark of claim 1 wherein the pattern of the alignment mark is a circular ring.

8. The alignment mark of claim 1, wherein the pattern of the alignment mark is a straight line.

9. The alignment mark of claim 1, wherein the pattern of the alignment mark is composed of a word and a ring disposed around the word.

10. A mask having the alignment mark of any one of claims 1 to 10.

11. A method for preparing a mask having the alignment mark of claim 9, comprising:

step I: forming a word pattern in the mask layer;

12. The method according to claim 11, wherein the step I and the step II use electron beams or laser to etch the mask.