CN109358256B - Lightning arrester on-line monitoring system for realizing synchronous sampling in RS485 communication - Google Patents
Lightning arrester on-line monitoring system for realizing synchronous sampling in RS485 communication Download PDFInfo
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- CN109358256B CN109358256B CN201811565836.0A CN201811565836A CN109358256B CN 109358256 B CN109358256 B CN 109358256B CN 201811565836 A CN201811565836 A CN 201811565836A CN 109358256 B CN109358256 B CN 109358256B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
The invention provides an online lightning arrester monitoring system for realizing synchronous sampling in RS485 communication, which comprises a host and a plurality of slave machines, wherein the slave machines are used for respectively monitoring electric signals on a plurality of lightning arresters, the host reads data acquired by each slave machine and carries out analysis and calculation to obtain related parameters of the lightning arresters, the host is connected with each slave machine through an RS485 interface, a connecting line of the RS485 interface is not only used as a communication connecting line between the host and each slave machine, but also used as a synchronous signal line between the host and each slave machine, and used for controlling the sampling time of each slave machine by the host to realize synchronous sampling, and the configuration of the communication baud rate when being used as the RS485 communication connecting line has no influence on the synchronous sampling control when being used as the RS485 synchronous signal line. The system provided by the invention realizes communication between the master machine and the slave machine and synchronous sampling between the master machine and the slave machine only by arranging one RS485 channel, and has high synchronous accuracy.
Description
Technical Field
The invention relates to the technical field of communication application, in particular to an arrester on-line monitoring system for realizing synchronous sampling in RS485 communication.
Background
The lightning arrester on-line monitoring system is composed of a host and a plurality of slave machines. The plurality of arresters share one voltage signal, and generally, a master machine monitors the voltage signal on the arresters, and a monitor serves as a slave machine and simultaneously detects current signals of the plurality of arresters. The small deviation of the phase positions between the voltage signal and the current signal and between the current signals has a large influence on the calculation results of a plurality of main parameters, and further has a large influence on the judgment of the performance of the lightning arrester, so that the monitoring of the voltage signal and the current signals is strictly synchronous, namely the synchronous sampling of all the voltage and current signals is realized as far as possible.
In the existing lightning arrester, a host and a plurality of detectors form a network through RS485, and one RS485 signal line is used for communication between the host and the data of the detectors. In addition, the system also has an RS485 signal which is independently used for the host to control each monitor to realize the synchronous sampling of the monitor and the host.
Such two way RS485 signal lines have increased cable cost and human cost. When the synchronous sampling is controlled by adopting the communication command, the sampling is started after the sampling command is analyzed and processed, and the command analysis process causes overlarge time deviation of the synchronous sampling due to different hardware and software running parts of each slave machine. In addition, two RS485 signal lines mean that the single chip microcomputer in the master and the slave machines must be provided with two UART interfaces, the selection range of the single chip microcomputer is reduced, and the cost is increased.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide the lightning arrester on-line monitoring system for realizing synchronous sampling in RS485 communication, which can realize synchronous sampling of each data acquisition unit in the system.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
the on-line monitoring system for the lightning arrester for realizing synchronous sampling in RS485 communication comprises a host and a plurality of slave machines, wherein the slave machines are used for monitoring electric signals on the plurality of lightning arresters respectively, the host reads data acquired by each slave machine and carries out analysis and calculation to obtain related parameters of the lightning arrester, the host is connected with each slave machine through an RS485 interface, a connecting line of the RS485 interface is not only used as a communication connecting line between the host and each slave machine, but also used as a synchronous signal line between the host and each slave machine, and used for controlling the sampling time of each slave machine by the host to realize synchronous sampling, and the configuration of the communication baud rate when being used as the RS485 communication connecting line does not influence the synchronous sampling control when being used as the RS485 synchronous signal line.
The data transmission line of the host is connected with the external interrupt pin of the host, the host transmits a synchronous sampling command to each slave, the host immediately transmits a datum, and the start bit of the datum is used as a synchronous sampling signal to trigger the external interrupt pin of the host to be interrupted; and the data receiving line of the slave is connected with the external interrupt pin of the slave, the slave waits for receiving the data sent by the host after receiving the synchronous sampling command sent by the host, and the start bit of the data is used as a synchronous sampling signal to trigger the external interrupt pin of the slave to generate interrupt.
The host starts sampling in the external interrupt service program, and the slave starts sampling in the external interrupt service program.
The external interrupt priority of the CPU controller in the host is configured as the highest priority of all interrupts; the external interrupt priority of the CPU controller in the slave is configured to be the highest priority among all its interrupts.
The triggering of an interrupt signal on an external interrupt pin in the host is configured to trigger an interrupt from high to low; the triggering of the interrupt signal on the external interrupt pin in the slave is configured to trigger the interrupt from high to low.
The host computer samples a certain amount of data or a certain time length of data according to preset parameters; the slave computer samples a certain amount of data or a certain time length of data according to the parameters set for the slave computer in advance by the master computer.
The synchronous sampling command is one byte of data.
The synchronous sampling command is a plurality of bytes of data.
The host machine controls each slave machine through the RS485 channel so as to synchronize voltage sampling of the host machine and current sampling of each slave machine, and the method specifically comprises the following steps:
host sending synchronous sampling preparation command
When synchronous sampling is needed, a host sends a sampling preparation command, and the host needs to perform necessary preparation work after sending the command, wherein the preparation work comprises allowing external interruption and clearing an interruption flag;
receiving a sample preparation command from a slave
After receiving a sampling preparation command, the slave computer performs necessary preparation work, including allowing external interruption and clearing an interruption flag;
host sending sampling command
After the sampling command is sent out, the host computer generates external interrupt, generates an interrupt mark, triggers or starts sampling in the external interrupt, and prohibits the external interrupt from regenerating until a new sampling preparation command is sent again;
receiving a sampling command from a slave
After receiving the sampling command, the slave machine also generates external interruption, triggers or starts sampling in the external interruption, and forbids the external interruption from regenerating until receiving a new sampling preparation command sent by the host machine again;
each slave sends the data to the master for calculation processing. The calculation processing method is conventional in the art and includes fourier transform, convolution calculation and the like.
The slave machine comprises a voltage detector and a plurality of current detectors for respectively monitoring voltage signals and current signals on the plurality of lightning arresters.
The slave machine comprises a plurality of current detectors for respectively monitoring current signals on a plurality of lightning arresters, and voltage signals on the lightning arresters are monitored by the host machine.
Compared with the prior art, the invention has the following beneficial effects:
the invention discloses an arrester on-line monitoring system for realizing synchronous sampling based on RS485 communication, which comprises the following components:
1. the system realizes communication between a master machine and a slave machine and synchronous sampling between the master machine and the slave machine only by arranging one RS485 channel;
2. synchronous sampling adopts the same signal bit on the communication data line, for example, the start bit of data transmission is used as a synchronous signal, and the synchronous precision is more accurate.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a block diagram of a system architecture according to an embodiment of the present invention;
FIG. 2 is a block diagram of the hardware schematic of the present invention;
FIG. 3 is a schematic diagram of a synchronous sampling process according to the present invention;
FIG. 4 is a flowchart of a main process of the host computer according to the present invention;
FIG. 5 is a flowchart of the host external interrupt service routine of the present invention;
FIG. 6 is a flowchart of the slave external interrupt service routine of the present invention;
fig. 7 is a flow chart of the slave master program of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
The invention provides an online lightning arrester monitoring system for realizing synchronous sampling in RS485 communication, which comprises a host and a plurality of slave machines as shown in figure 1. The slave includes a voltage detector and a plurality of current detectors. The voltage detector is used for monitoring a voltage signal of the lightning arrester, and the current detector is used for monitoring a current signal flowing on the lightning arrester. And synchronous signals between the data sampling of the voltage signal and the data sampling of the current signal are completed through an RS485 signal wire between the master machine and the slave machine. The main CPU is arranged in the main machine and provided with a UART interface, and the UART interface is converted into an RS485 communication line through an RS485 chip. Each slave computer is internally provided with a slave CPU, the slave CPU is provided with a UART interface, and the UART interface is converted into an RS485 communication line through an RS485 chip; the host computer and the slave computer are connected through an RS485 line to realize communication. The data transmission line of the main CPU is also connected with an interrupt signal line of the main CPU, and the data receiving line of the slave CPU is also connected with an interrupt signal line of the slave CPU; when synchronous sampling is carried out, a synchronous signal is generated on a data sending line of the master CPU, the master CPU and the slave CPU are simultaneously interrupted, and respective ADC sampling is simultaneously started, so that synchronous sampling of the master and the slave is realized. And after sampling, the host reads the data of each slave machine for calculation to obtain the relevant parameters of the lightning arrester.
Principle of UART communication:
the UART sending data is sent according to bits, and sending an 8-bit data generally sends 10 bits, which also includes a start bit and a stop bit, and the specific data sending sequence is: start bit, 8-bit data bit, stop bit. The UART transmit signal is high when no data is transmitted, and the start bit is low when data is transmitted, and this start bit in the UART communication process can be used as a synchronization signal. According to this synchronization signal, the master CPU and the slave CPU are required to start respective sampling signals simultaneously.
Synchronous realization of hardware signals:
synchronous sampling is realized through a signal wire on hardware. The hardware connection structure of the master and the slave is shown in fig. 2. The host computer and the slave computer in the system communicate through RS485, and the interface connected with the RS485 chip and the CPU is a UART interface. In the communication process, signals generated by the transmitting data line TXD _ M of the master CPU and the receiving data line RXD _ S of the slave CPU are the same and synchronous, and the signal lines can be used as synchronous signal lines.
In an embodiment of the present invention, the main CPU uses an STM32F103VCT6 chip, and the system clock frequency: the clock of 72MHz, the slave CPU uses STM32F103C8T6 chip, the system frequency and the configuration of the timer are the same as the master CPU.
Configuration of the UART interface:
the UART is used for connecting the RS485 chip for communication. The main CPU uses UART1 to connect with RS485, configures baud rate 115200,8 bit data bit, 1 stop bit, without parity. The slave CPU uses UART3 to connect with RS485 chip, and configures baud rate 115200,8 bit data bit, 1 bit stop bit, and no parity.
Configuration and interrupt handling of external interrupts:
the host CPU external interrupt uses the PC0 pin to connect to the UART transmit signal line TX. Configured to trigger an interrupt on a falling edge. The PA2 pin is used for connection of the UART reception signal line RX from the CPU external interrupt. Configured to trigger an interrupt on a falling edge. The external interrupts of the master and slave CPUs can be set to be disabled and enabled, that is, the generation of the interrupt is disabled and the generation of the interrupt is enabled.
Sampling is initiated in an interrupt.
The specific implementation process, as shown in fig. 3, includes the following steps:
the host sends a preparation command: when synchronous sampling is needed, the host sends a synchronous sampling preparation command. After the command is sent, the host needs to do necessary preparation work, specifically, external interrupt is allowed, and the interrupt flag is cleared.
After the slave receives the preparation command, the same preparation work is carried out, external interruption is allowed, and the interruption flag is cleared.
The host sends a synchronous sampling command: when the synchronous command is sent out, the host computer can generate external interrupt, start sampling in the interrupt program and set the interrupt mark.
The slave machine simultaneously generates external interrupt, starts sampling in the interrupt program and collocates interrupt marks.
The host sends a synchronous preparation command packet, a 16-system packet: "55 AA 3154494D 450D 0A"
The host sends a synchronous sampling data packet, a 16-system data packet: "55 AA 32"
The working process is as follows:
the host main program flow chart is shown in fig. 4. The main flow of the host computer is a program execution flow from the beginning of preparation sampling to the end of final sampling in the synchronous sampling process of the host computer.
The host external interrupt routine, as shown in FIG. 5.
The slave master program flow chart is shown in fig. 6. The slave main flow is a program execution flow from the time when the slave receives the preparation sampling command to the time when the sampling processing is completed in the operation process.
The slave external interrupt service program: as shown in fig. 7.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (10)
1. An arrester on-line monitoring system for realizing synchronous sampling in RS485 communication is characterized by comprising a host and a plurality of slaves, wherein the slaves are used for respectively monitoring electric signals on the plurality of arresters, the host reads data acquired by each slave and analyzes and calculates the data to obtain related parameters of the arresters, the host is connected with each slave through an RS485 interface, the RS485 interface connecting line not only serves as a communication connecting line between the host and each slave, but also serves as a synchronous signal line between the host and each slave for controlling the sampling time of each slave by the host, the data transmitting line of the host CPU is connected with an interrupt signal line of the host CPU, the data receiving line of the slave CPU is also connected with an interrupt signal line of the slave CPU, synchronous signals are generated on the data transmitting line of the host CPU during synchronous sampling, the host CPU and the slave CPUs are simultaneously interrupted, and respective ADC sampling is simultaneously started, and furthermore, synchronous sampling of the host and the slave is realized, and the configuration of the communication baud rate when the RS485 communication connecting line is used does not influence the synchronous sampling control when the RS485 communication connecting line is used as an RS485 synchronous signal line.
2. The on-line monitoring system for the lightning arrester for realizing the synchronous sampling in the RS485 communication as claimed in claim 1, wherein a data transmission line of the host is connected with an external interrupt pin thereof, the host transmits a synchronous sampling command to each slave, the host immediately transmits a data, and a start bit of the data is used as a synchronous sampling signal for triggering the external interrupt pin of the host to be interrupted; and the data receiving line of the slave is connected with the external interrupt pin of the slave, the slave waits for receiving the data sent by the host after receiving the synchronous sampling command sent by the host, and the start bit of the data is used as a synchronous sampling signal to trigger the external interrupt pin of the slave to generate interrupt.
3. The on-line lightning arrester monitoring system capable of realizing synchronous sampling in RS485 communication as claimed in claim 2, wherein the external interrupt priority of the CPU controllers in the master and the slave are configured to be the highest priority of all the interrupts.
4. The on-line lightning arrester monitoring system capable of realizing synchronous sampling in RS485 communication as claimed in claim 2, wherein the triggering of the interrupt signal on the external interrupt pin in the master and slave is configured to trigger the interrupt from high to low.
5. The on-line monitoring system for the lightning arrester for realizing synchronous sampling in RS485 communication as claimed in claim 2, wherein the host machine samples a certain amount of data or a certain time length of data according to a parameter set in advance; the slave computer samples a certain amount of data or a certain time length of data according to the parameters set for the slave computer by the master computer in advance.
6. The on-line arrester monitoring system capable of realizing synchronous sampling in RS485 communication as claimed in claim 2, wherein the synchronous sampling command is one byte of data.
7. The on-line arrester monitoring system capable of realizing synchronous sampling in RS485 communication as claimed in claim 2, wherein the synchronous sampling command is data of a plurality of bytes.
8. The lightning arrester online monitoring system for realizing synchronous sampling in RS485 communication according to claim 2, wherein the synchronous realization of the host computer for sampling signals of the slave computers specifically comprises:
host sending synchronous sampling preparation command
When synchronous sampling is needed, a host sends a sampling preparation command, and the host needs to perform necessary preparation work after sending the command, wherein the preparation work comprises allowing external interruption and clearing an interruption flag;
receiving a sample preparation command from a slave
After receiving a sampling preparation command, the slave computer performs necessary preparation work, including allowing external interruption and clearing an interruption flag;
host sending sampling command
After the sampling command is sent out, the host computer generates external interrupt, generates an interrupt mark, triggers or starts sampling in the external interrupt, and prohibits the external interrupt from regenerating until a new sampling preparation command is sent again;
receiving a sampling command from a slave
After receiving the sampling command, the slave machine also generates external interruption, triggers or starts sampling in the external interruption, and forbids the external interruption from regenerating until receiving a new sampling preparation command sent by the host machine again;
each slave sends the data to the master for calculation processing.
9. The lightning arrester online monitoring system capable of realizing synchronous sampling in RS485 communication as claimed in claim 1, wherein the slave machine comprises a voltage detector and a plurality of current detectors for respectively monitoring voltage signals and current signals on a plurality of lightning arresters.
10. The lightning arrester online monitoring system capable of realizing synchronous sampling in RS485 communication as claimed in claim 1, wherein the slave computer comprises a plurality of current detectors for respectively monitoring current signals on a plurality of lightning arresters, and voltage signals on the lightning arresters are monitored by the host computer.
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| CN111856198A (en) * | 2020-07-28 | 2020-10-30 | 江西联智集成电路有限公司 | Batch test method for equipment to be tested |
| CN114443551B (en) * | 2021-12-25 | 2023-07-14 | 苏州浪潮智能科技有限公司 | Method, system, equipment and medium for realizing I2C communication by single line |
| CN114401182A (en) * | 2022-01-06 | 2022-04-26 | 浙江南都能源互联网有限公司 | RS485 power station based main and standby communication method and system |
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