CN113645322B - Address code identification method and device based on optical fiber serial communication and application thereof - Google Patents
Address code identification method and device based on optical fiber serial communication and application thereof Download PDFInfo
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- CN113645322B CN113645322B CN202110803525.9A CN202110803525A CN113645322B CN 113645322 B CN113645322 B CN 113645322B CN 202110803525 A CN202110803525 A CN 202110803525A CN 113645322 B CN113645322 B CN 113645322B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/50—Address allocation
- H04L61/5038—Address allocation for local use, e.g. in LAN or USB networks, or in a controller area network [CAN]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/25—Arrangements specific to fibre transmission
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2101/00—Indexing scheme associated with group H04L61/00
- H04L2101/60—Types of network addresses
- H04L2101/618—Details of network addresses
- H04L2101/645—Fibre channel identifiers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The invention provides an address code identification method and device based on optical fiber serial communication and application thereof, and the method and device comprise the following steps: s1, connecting 1 master controller and a plurality of sub controllers by using optical fibers; s2, serial communication is carried out between the 1 master controller and the plurality of sub controllers; s3, when power is on, the main controller sends an address code checking command to check the address code, and the address code of each sub-controller is stored in a communication control chip inside each sub-controller; s4, executing other control commands when the address code is checked to be correct; and when the address code is checked to be abnormal, executing an address code resetting command according to the requirement. The invention uses optical fiber connection to carry out serial communication between the main controller and each sub controller, and can be applied to occasions needing high voltage isolation, such as unit bypass control of a high voltage frequency converter; the sub controllers can be replaced at will, and address codes of the sub controllers are not required to be managed, so that the cost of manually setting the address codes is saved, and the occurrence of abnormality of address code setting errors is prevented.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to an address code identification method and apparatus based on optical fiber serial communications, and applications thereof.
Background
Serial communication technology is a communication scheme in which two parties of communication perform bit by bit and observe time sequence. In serial communication, data are sequentially transmitted according to bits, each bit of data occupies a fixed time length, and information exchange between systems can be completed by using a few communication lines, so that the serial communication method is particularly suitable for long-distance communication between computers and peripherals. Serial communication is used for serial transmission of data among systems (multi-master control system), devices (master control device and accessory device) and devices (master control CPU and functional chip), so as to realize data transmission and sharing.
The traditional serial communication scheme mostly uses wires as connecting media, and has no high-voltage isolation requirement in the use of unit bypass control of a high-voltage frequency converter and the like; the sub controllers are identified by a dial switch, and address codes of the sub controllers are required to be independently set. The disadvantages of this solution are: 1. the use capability in a high-voltage isolation environment is not provided; 2. the address code needs to be set manually and independently, is easy to make mistakes, and the sub controllers are inconvenient to exchange at will.
Disclosure of Invention
The invention solves the problems that: the traditional serial communication does not have the use condition under the high-voltage isolation environment, and the manual setting of the address code of the sub-controller is easy to make mistakes.
In order to solve the above problems, in one aspect, the present invention provides an address code identification method based on optical fiber serial communication, which includes the following steps:
s1, connecting 1 master controller and a plurality of sub controllers by using optical fibers;
s2, serial communication is carried out between the 1 master controller and the plurality of sub controllers;
s3, when power is on, the main controller sends an address code checking command to check the address code, and the address code of each sub-controller is stored in a communication control chip inside each sub-controller;
s4, executing other control commands when the address code is checked to be correct; and when the address code is checked to be abnormal, executing an address code resetting command according to the requirement.
Preferably, the serial communication shares 1 serial data channel, and the serial communication adopts a time-sharing multiplexing method for communication.
Preferably, the serial communication is in time slices, and 1 time slice is the sum of the time of packet transmission and the time of packet interval.
Preferably, the other control commands include identifying each sub-controller by an address code, and the sub-controller determines whether to be a control command for itself according to the address code of the master data packet.
Preferably, the main controller sends an address code checking command to check the address code, and the address code of each sub-controller is stored in a communication control chip inside each sub-controller, which comprises the following steps:
s31, the master controller sends an address code checking command data packet and delays, wherein the delay time is longer than n+1 time slices, n is the number of the sub controllers, and the master controller only receives data and does not send any data during the delay.
S32, after the main controller sends the address code checking command data packet, all the sub controllers simultaneously receive the data packet, after the sub controllers receive the data packet, the sub controllers execute data checking sum command analysis, and after the address code checking command sent by the main controller is analyzed, all the sub controllers wait for the completion of the current main controller data packet time slice.
S33, after the time slices of the data packets of the main controller are finished, all the sub controllers judge whether the address code of the sub controllers is 1, if the address code of the sub controllers is 1, the sub controllers send address code response data packets containing address code information of the sub controllers, the sub controllers 1# do not send data any more, according to the unidirectional data transmission principle, the sub controllers behind the sub controllers 1# can all receive the address code response data packets of the sub controllers 1# and store the address code of the address code response data packets, and the address code is 1 at the moment.
S34, after the address code response data packet time slices of the 1# sub-controllers are finished, all sub-controllers behind the 1# sub-controllers receive the address code +1 in the latest address code response data packet, which is 2 at the moment, and compare with the own address code, if the address code response data packets are equal, the address code response data packet containing the address code information of the sub-controllers is sent, the 2# sub-controllers do not send data any more, and the sub-controllers behind the 2# sub-controllers can receive the address code response data packet at the moment and store the address code of the address code response data packet at the moment, which is 2 at the moment.
S35, after the address code response data packet time slices of the 2# sub-controllers are finished, all the sub-controllers behind the 2# sub-controllers receive the address code +1 in the latest address code response data packet, which is 3 at the moment, and the latest address code response data packet is compared with the own address code, if the latest address code is equal to the latest address code response data packet, the address code response data packet containing the address code information of the sub-controllers is transmitted, the 3# sub-controllers do not transmit data any more, and the sub-controllers behind the 3# sub-controllers can receive the address code response data packet at the moment and store the address code of the address code response data packet at the moment, which is 3 at the moment.
S36, the same is done until the n# subcontroller completes address code response data and waits for a time slice to complete, namely all subcontroller address code response operations complete.
S37, waiting for the master controller in the step S31 to finish delaying n+1 time slices, and judging whether the number of address codes in the last address code response data packet is the same as the number of the set sub controllers by the master controller, if so, checking the address codes correctly; otherwise, the address code checks for errors.
Preferably, when the address code checks for abnormality, executing the address code resetting command according to the need includes the following steps:
s41, in the 1 st time slice, the main controller sends an address code resetting data packet, after the whole partial controllers receive the address code resetting data packet of the main controller, the whole partial controllers send interference data packets from the 2 nd time slice, and the interference data packets are used for enabling the partial controllers to always lighten the sending optical mode Tx of the partial controllers during the time slice data sending period and are used for shielding normal data backward transmission.
S42, the 2 nd time slice, the address code reset response data packet with the address code of 0 is sent by the main controller, the address code reset response data packet is used for triggering the 1# sub-controller, no data packet is sent until the address initialization of all the sub-controllers is completed after the main controller sends the address code reset response data packet, the data packet of the 2 nd time slice can be normally received only by the 1# sub-controller connected with the main controller sending the optical mode Tx, because all the sub-controllers send the interference data packet at the moment, all the sub-controllers after the 1# sub-controller only receive the interference data packet, the packet header, the packet tail and various check codes cannot be normally checked, the data packet can be discarded and not responded, the 1# sub-controller extracts the address code in the packet and adds 1 to be processed according to the received address code reset response data packet, and then the address code of the 1# sub-controller is used as the address code of the sub-controller to be stored, and the address code of the 1# sub-controller is successfully set at the moment.
S43, after the 3 rd time slice, the 1# sub-controller stops sending the interference data packet backwards after setting the own address code, and sends the address code resetting response data packet carrying the own address code backwards, at this time, only the 2# sub-controller, the physical position of which is connected with the 1 st sub-controller sending the optical mode Tx, can receive the address code resetting response data packet, the 2# sub-controller stores the address code of the received address code resetting response data packet together with 1 as the own address code, and the address code of the 2# sub-controller is successfully set, at this time, is 2.
S44, after the 4 th time slice, the 2# sub-controller stops sending the interference data packet backwards after setting the own address code, and sends the address code resetting response data packet carrying the own address code backwards, at this time, only the 3# sub-controller, the physical position of which is connected with the 2 nd sub-controller sending the optical mode Tx, can receive the address code resetting response data packet, the 3# sub-controller stores the address code of the received address code resetting response data packet together with 1 as the own address code, and the address code of the 3# sub-controller is successfully set, at this time, the 3.
S45, and so on until the nth sub-controller transmits the address code resetting response data packet.
S46, after the nth sub-controller sends out the own address code resetting response data packet, the main controller detects whether the number of the address codes carried in the address code resetting response data packet of the last sub-controller is the same as the number of the set sub-controllers, and if so, the address code resetting is successful; otherwise, the address code reset fails.
In another aspect, the present invention further provides an apparatus, which adopts the address code identification method based on optical fiber serial communication as described above, wherein the apparatus includes:
the 1 master controller is an active device for executing address code inspection, address code resetting and issuing control commands;
the plurality of sub controllers are passive devices for assisting the master controller to finish address code verification, address code resetting and master controller control command execution;
the optical fiber is a communication medium between the master controller and the sub-controllers and between the sub-controllers;
the master controller is in serial communication with the sub controllers through the optical fiber connection.
Preferably, the transmitting optical mode Tx of the master is connected to the receiving optical mode Rx of the 1 st slave, the transmitting optical mode Tx of the 1 st slave is connected to the receiving optical mode Rx of the 2 nd slave, the transmitting optical mode Tx of the 2 nd slave is connected to the receiving optical mode Rx of the 3 rd slave, and so on, and the transmitting optical mode Tx of the last 1 slave is connected to the receiving optical mode Rx of the master, thus forming 1 closed serial communication device.
Preferably, the transmitting optical mode Tx is responsible for converting an electrical signal into an optical signal so that the signal can be transmitted in an optical fiber; the receiving optical mode Rx is responsible for converting optical signals into electric signals so that communication control in the main controller and the sub controllers can be analyzed.
Preferably, the transmitting optical mode Tx of the master converts the electrical signal into an optical signal, and is controlled by the communication control circuit of the master to perform the operations of address code inspection, address code resetting and issuing control commands; the receiving optical mode Rx of the main controller converts the optical signal into an electric signal, monitors the correctness of the data in the serial data line and receives the feedback data of the sub-controllers; the receiving optical mode Rx of the sub-controller converts the optical signal into an electric signal, and the electric signal is directly converted into the optical signal through the transmitting optical mode Tx of the current sub-controller and transmitted to the next sub-controller, and the optical signal is transmitted into the communication control circuit of the current sub-controller, and the communication control circuit of the current sub-controller checks the correctness of the data, analyzes the data and makes judgment and execution.
In still another aspect, the present invention further provides an application of the address code identification method based on optical fiber serial communication, where the method is applied to unit bypass control of a high-voltage frequency converter.
Compared with the prior art, the address code identification method and device based on the optical fiber serial communication and the application thereof have the following beneficial effects:
(1) The address code identification method and device based on the optical fiber serial communication and the application thereof are that the optical fiber connection is used for serial communication between the main controller and each sub-controller, and the method and device can be applied to occasions needing high voltage isolation, such as the unit bypass control of a high-voltage frequency converter;
(2) According to the address code identification method and device based on the optical fiber serial communication and the application thereof, the address codes of the sub-controllers are not required to be set manually, the address codes of the sub-controllers are stored in the control chip of the sub-controllers, the correctness of the address codes of the sub-controllers is automatically detected through software when the main controller is electrified or before each control command is sent, if the correctness is incorrect, the main controller controls the execution of the resetting of the address codes of the sub-controllers through software, so that the sub-controllers can be replaced at will, the address codes of the sub-controllers do not need to be managed, the cost of manually setting the address codes is saved, the abnormal occurrence of the address code setting errors is prevented, and the situation that the error control is avoided when the position of the sub-controllers is replaced can be ensured;
(3) The address code verification method can judge all address code abnormality problems such as address repetition codes, inconsistent address codes and physical positions, abnormal non-response of the sub-controllers, abnormal communication and the like, and can obtain correct address code response information only when the address code setting of the sub-controllers is consistent with the physical positions of the sub-controllers.
(4) The interference data packet in the address code resetting command can enable the sub-controller to enable the self transmission optical mode Tx to be always on during the time slice data transmission period, and is used for shielding normal data from being transmitted backwards.
Drawings
FIG. 1 is a flow chart of the method of the present invention;
FIG. 2 is a flow chart of the address code verification procedure of the sub-controller according to the present invention;
FIG. 3 is a flowchart of a sub-controller address code resetting procedure according to the present invention;
fig. 4 is a schematic diagram of the hardware connection of the present invention.
Reference numerals illustrate:
1. 2, 3, … n, a sub-controller; A. a master controller; B. an optical fiber; tx, transmit optical mode; rx, receiving the optical mode.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Example 1
An address code identification method based on optical fiber serial communication is provided, as shown in fig. 1, wherein the method comprises the following steps:
s1, connecting 1 master controller and a plurality of sub controllers by using optical fibers;
s2, serial communication is carried out between the 1 master controller and the plurality of sub controllers;
s3, when power is on, the main controller sends an address code checking command to check the address code, and the address code of each sub-controller is stored in a communication control chip inside each sub-controller;
s4, executing other control commands when the address code is checked to be correct; and when the address code is checked to be abnormal, executing an address code resetting command according to the requirement.
Wherein the serial communications share 1 serial data lane; the serial communication adopts a time-sharing multiplexing method for communication. Time division multiplexing (Time Division Multiplexing, TDM) is to use different time periods of the same physical connection to transmit different signals, so as to achieve the purpose of multiplexing. In a network for transmitting multiple data lines. Since time division multiplexing uses time as a parameter for signal division transmission, it is necessary to prevent each signal from overlapping each other on the time axis, and to transmit different signals at different times. The entire transmission time is divided into time intervals, also called time slots, which do not overlap each other. The time division multiplexing technique allocates these time slots to each signal source for use, each time slot being occupied by only one signal. Time multiplexing achieves a circuit to transmit multiple signals by cross-transmitting a portion of each signal in time. Only one signal is present at each brief moment in the circuit. Time-division multiplexing is suitable for the transmission of digital signals. Because digital signals are of a finite number of discrete values, time division multiplexing techniques are widely used in digital communication systems, including computer networks.
Wherein, the serial communication takes time slices as a unit, and 1 time slice is the sum of the time of data packet transmission and the time of data packet interval. A time slice (timer), also known as a "quantum" or "processor slice," is a period of CPU time allocated by the time-sharing operating system to each running process microscopically (in the preemptive kernel: the time from the start of the running process until preempted). Modern operating systems (e.g., windows, linux, mac OS X, etc.) allow multiple processes to run simultaneously, for example, you can browse web pages and download files with a browser while opening a music player to listen to music. In fact, while a computer may typically have multiple CPUs, the same CPU may never actually run multiple tasks simultaneously. In the case of considering only one CPU, these processes "look like" running simultaneously, rather run alternately, since the time slices are typically very short (5 ms-800ms on Linux) and are not felt by the user.
The other control commands comprise identifying each sub-controller by using an address code, and judging whether the sub-controller is a control command for the sub-controller according to the address code of the data packet of the main controller.
The address code setting rule of the sub-controller is associated with the physical position of the sub-controller in the whole serial communication, for example: the address of the 1# sub-controller connected with the main controller transmitting the optical mode Tx is 1, the address of the next 2# sub-controller is 2, … …, the address of the n # sub-controller is n, and the number of the sub-controllers needs to be set in the main controller.
The working principle of address code verification is as follows:
1. the master controller sends an address code check command data packet and delays, wherein the delay time is greater than n+1 time slices, and n is the number of the sub controllers. The master only receives the data during the delay period and does not send any data.
2. After the master controller sends the address code verification command data packet, all the sub controllers simultaneously receive the data packet, after the sub controllers receive the data packet, the sub controllers execute data verification and command analysis, and after the address code verification command sent by the master controller is analyzed, all the sub controllers wait for the completion of the current master controller data packet time slice (namely protocol time, all the sub controllers know).
3. After the time slices of the data packets of the main controller are completed, all the sub controllers judge whether the address codes of the sub controllers are 1, if the address codes of the sub controllers are 1, the sub controllers send address code response data packets containing the information of the address codes of the sub controllers, and the sub controllers 1# do not send data. According to the unidirectional data transmission principle, the slave controllers behind the 1# slave controller can receive the address code response data packet of the 1# slave controller, and store the address code (1 at this time) of the address code response data packet.
4. After the address code response data packet time slice of the 1# sub-controller is finished, all sub-controllers behind the 1# sub-controller compare the address code +1 (2 at this time) in the latest received address code response data packet with the own address code, if the address code +1 is equal to the own address code, the address code response data packet containing the address code information (2 at this time) of the sub-controller is sent, and the 2# sub-controller does not send data any more. At this time, the subcontroller behind the # 2 subcontroller can receive the address code response packet, and store the address code (at this time, 2) of the address code response packet.
5. After the address code response data packet time slice of the 2# sub-controller is finished, all sub-controllers behind the 2# sub-controller compare the address code +1 (3 at this time) in the latest received address code response data packet with the own address code, if the address code response data packet is equal to the address code response data packet, the address code response data packet containing the address code information (3 at this time) of the sub-controller is sent, and the 3# sub-controller does not send data any more. At this time, the subcontroller after the 3# subcontroller can receive the address code response packet, and store the address code (at this time, 3) of the address code response packet.
6. And the like until the n # subcontroller finishes the address code response data and waits for the time slice to finish, namely the address code response operation of all subcontrollers is finished.
7. Waiting for the master controller in the step 1 to delay the completion of n+1 time slices, and judging whether the number of the address codes in the last address code response data packet is the same as the number of the set sub controllers by the master controller, if so, checking the address codes to be correct; otherwise, the address code checks for errors.
As shown in fig. 2, the program flow of address code verification specifically includes the following steps:
step 1: the procedure starts;
step 2: judging whether a new data packet is received, if yes, turning to the step 3, otherwise, turning to the step 2;
step 3: judging whether the data of the new data packet is checked correctly, if so, turning to the step 4, otherwise, turning to the step 2;
step 4: judging whether the data packet is an address code check data packet sent by the master controller, if so, turning to the step 5, otherwise, turning to the step 9;
step 5: judging whether the address code of the user is 1, if so, turning to the step 6, otherwise, turning to the step 2;
step 6: waiting for completion of the data packet time slice;
step 7: modifying the address of the data packet by using the address code 1, modifying the data packet into a response data packet of an address code check command, and sending the response data packet backwards;
step 8: waiting for the completion of data packet transmission, and turning to the step 2;
step 9: judging whether the packet is a response data packet of an address code check command sent by the sub-controller, if so, turning to the step 10, otherwise, turning to the step 11;
step 10: judging whether the address code +1 of the received response data packet is equal to the address code of the user, if so, turning to the step 12, otherwise, turning to the step 2;
step 11: processing other data packets;
step 12: waiting for completion of the data packet time slice;
step 13: modifying the address of the data packet by using the address code of the data packet, and sending a response data packet of the address code check command backwards;
step 14: and (5) waiting for the completion of data packet transmission, and turning to step 2.
The address code checking method can judge all address code abnormality problems such as address repetition codes, address codes inconsistent with physical positions, abnormal non-response of a sub controller, abnormal communication and the like. The correct address code response information is obtained only when the address code setting of the slave controller coincides with the physical position of the slave controller. Address code verification is the basis for resetting address codes using software.
When the result of the main controller executing the address code checking command is abnormal, the main controller executes the address code resetting command according to the user requirement, and the related words of the program are defined:
interference data packet: the sub-controller makes its own transmitting optical mode Tx always light during the time slice data transmission, and is used for shielding normal data from backward transmission, which is a core technical point of address code resetting.
Address code resetting response data packet: and after the address code of a certain sub-controller is successfully set, a response data packet containing the address code of the sub-controller is sent backwards.
The address code resetting working principle is as follows:
1. in the 1 st time slice, the master controller sends an address code resetting data packet, and after receiving the address code resetting data packet of the master controller, all partial controllers send interference data packets from the 2 nd time slice.
2. And the 2 nd time slice is used for sending an address code resetting response data packet with the address code of 0 by the main controller and triggering the 1# sub-controller to set the address code of the main controller. After the master controller transmits the address code resetting response data packet, the master controller does not transmit any data packet until the initialization of the address codes of all the partial controllers is completed. The data packet of the 2 nd time slice can be normally received only by the sub-controllers connected with the master controller transmitting the optical mode Tx, because all sub-controllers transmit the interference data packet at the moment, all sub-controllers after the 1# sub-controllers only receive the interference data packet, the packet header, the packet tail and various check codes can not be normally checked, and the data packet can be discarded and not responded. The 1# sub controller resets the response data packet according to the received address code, extracts the address code in the packet, adds 1 for processing, and then saves the address code as the own address code, and the address code of the 1# sub controller is successfully set.
3. And after the 3 rd time slice, the 1# sub-controller stops sending the interference data packet backwards after setting the own address code, and sends the address code resetting response data packet carrying the own address code (1 at the moment), only the sub-controller (namely the 2# sub-controller) with the physical position connected with the 1 st sub-controller sending optical mode Tx can receive the address code resetting response data packet, the 2# sub-controller adds 1 to the address code of the received address code resetting response data packet to serve as the own address code to be stored, and the 2# sub-controller address code setting is successful.
4. And after the 4 th time slice, the 2# sub-controller finishes setting the own address code, stopping sending the interference data packet backwards, and sending the address code resetting response data packet carrying the own address code (2 at the moment), wherein only the sub-controller (namely the 3# sub-controller) with the physical position connected with the 2 nd sub-controller sending optical mode Tx can receive the address code resetting response data packet, the 3# sub-controller adds 1 to the address code of the received address code resetting response data packet to serve as the own address code, and the 3# sub-controller address code setting is successful.
5. And so on until the nth sub-controller transmits the own address code resetting response data packet.
6. After the nth sub-controller sends out the own address code resetting response data packet, the main controller detects whether the number of the address codes carried in the address code resetting response data packet of the last sub-controller is the same as the number of the set sub-controllers, and if so, the address code resetting is successful; otherwise, the address code reset fails.
As shown in fig. 3, the program flow of resetting the address code of the sub-controller specifically includes the following steps:
step 1: the procedure starts;
step 2: judging whether a new data packet mark is set to 1, if so, turning to step 3, otherwise, turning to step 2;
step 3: judging whether the data CRC is correct, if so, turning to step 4, otherwise, turning to step 2;
step 4: judging whether the address code initialization command packet is sent by the master controller, if so, turning to step 5, otherwise, turning to step 10;
step 5: the interference data packet count is set as a set value;
step 6: judging whether the interference data packet count is greater than 0, if so, turning to the step 7, otherwise, turning to the step 2;
step 7: waiting for completion of the data packet time slice;
step 8: performing 1 subtracting treatment on the interference data packet count, and transmitting the interference data packet;
step 9: waiting for the completion of the transmission of the interference data packet, and turning to the step 2;
step 10: judging whether the data packet is a response data packet of the address code initialization command packet, if so, turning to the step 11, otherwise, turning to the step 12;
step 11: initializing an address by using the address code +1 of the response packet as the address code of the current sub-controller, and turning to the step 13;
step 12: processing other data packets;
step 13: waiting for completion of the data packet time slice;
step 14: the interference data packet count is set to 0, and a response data packet of the address code initialization command packet (the data packet is filled with the address code of the user) is sent;
step 15: and (3) waiting for the completion of the transmission of the response data packet of the address code initialization command packet, and turning to the step (2).
Example two
An apparatus is provided, which adopts the address code identification method based on optical fiber serial communication according to embodiment one, as shown in fig. 4, wherein the apparatus includes 1 master controller (abbreviated as master controller, which is an active device for executing address code verification, address code resetting, and issuing control commands), multiple sub controllers (abbreviated as sub controllers, which are passive devices for assisting the master controller to complete address code verification, address code resetting, and master controller control command execution), and optical fibers (which are communication media between the master controller and the sub controllers, between the sub controllers, and between the sub controllers and the sub controllers), and between the master controller and the sub controllers, which are in serial communication through the optical fiber connection.
The Tx (transmit optical mode) of the master is responsible for converting the electrical signal into an optical signal so that the signal can be transmitted in the optical fiber) connected to the Rx (receive optical mode) of the 1 st slave, and responsible for converting the optical signal into an electrical signal so that the communication control in the master and the slave can be resolved, the Tx (transmit optical mode) of the 1 st slave is connected to the Rx (receive optical mode) of the 2 nd slave, the Tx of the 2 nd slave is connected to the Rx (transmit optical mode) of the 3 rd slave, and so on, and the Tx (transmit optical mode) of the last 1 slave (denoted by n in fig. 4) is connected to the Rx (receive optical mode) of the master, thus forming 1 closed serial communication device.
The Tx of the master controller converts the electric signal into an optical signal, and the master controller is controlled by a communication control circuit to execute the operations of address code inspection, address code resetting and control command issuing; the Rx of the main controller converts the optical signal into an electric signal, monitors the correctness of the data in the serial data line and receives the feedback data of the sub-controller. The Rx of the sub-controller converts the optical signal into an electric signal, and the electric signal is directly converted into the optical signal through the Tx of the current sub-controller and transmitted to the next sub-controller, and the optical signal is transmitted into the communication control circuit of the current sub-controller, and the communication control circuit of the sub-controller checks the correctness of the data, analyzes the data and makes judgment and execution.
Thus, the device in the embodiment uses optical fiber connection to carry out serial communication between the main controller and each sub controller, and can be applied to high-voltage isolation occasions; the device does not need to manually set the address codes of the sub-controllers, the address codes of the sub-controllers are stored in the control chip of the sub-controllers, the correctness of the address codes of the sub-controllers is automatically detected through software when the main controller is electrified or before each control command is sent, if the correctness is incorrect, the main controller controls the resetting of the address codes of the sub-controllers through software, so that the sub-controllers can be arbitrarily replaced, the address codes of the sub-controllers do not need to be managed, the cost of manually setting the address codes is saved, the abnormal occurrence of the address code setting errors is prevented, and the error control can still be ensured not to occur when the sub-controllers are replaced.
Example III
There is provided an application of the address code identification method based on fiber serial communication according to embodiment one, wherein the method is applied to the unit bypass control of a high voltage frequency converter.
Although the invention is disclosed above, the scope of the invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications will fall within the scope of the invention.
Claims (8)
1. An address code identification method based on optical fiber serial communication is characterized by comprising the following steps:
s1, connecting 1 master controller and a plurality of sub controllers by using optical fibers;
s2, serial communication is carried out between the 1 master controller and the plurality of sub controllers;
s3, when power is on, the main controller sends an address code checking command to check the address code, and the address code of each sub-controller is stored in a communication control chip inside each sub-controller;
s4, executing other control commands when the address code is checked to be correct; when the address code is verified to be abnormal, executing an address code resetting command according to the requirement;
the main controller sends an address code checking command to check the address code, and the address code of each sub-controller is stored in a communication control chip inside each sub-controller, which comprises the following steps:
s31, the master controller sends an address code checking command data packet and delays, wherein the delay time is greater than n+1 time slices, n is the number of the sub controllers, and the master controller only receives data and does not send any data during the delay;
s32, after the main controller sends the address code verification command data packet, all sub controllers simultaneously receive the data packet, after the sub controllers receive the data packet, the sub controllers execute data verification and command analysis, and after the address code verification command sent by the main controller is analyzed, all the sub controllers wait for the completion of the current main controller data packet time slice;
s33, after the time slices of the data packets of the main controller are finished, all the sub controllers judge whether the address code of the sub controllers is 1, if the address code of the sub controllers is 1, the sub controllers send address code response data packets containing the address code information of the sub controllers, the sub controllers 1# do not send data any more, according to the unidirectional transmission principle of the data, the sub controllers behind the sub controllers 1# can all receive the address code response data packets of the sub controllers 1# and store the address code of the address code response data packets, and the address code is 1 at the moment;
s34, after the address code response data packet time slices of the 1# sub-controllers are finished, all sub-controllers behind the 1# sub-controllers receive the address code +1 in the latest address code response data packet, namely 2 at the moment, and compare the latest address code with the own address code, if the latest address code is equal to the latest address code, the address code response data packet containing the address code information of the sub-controllers is transmitted, the 2# sub-controllers do not transmit data any more, and the sub-controllers behind the 2# sub-controllers can receive the address code response data packet at the moment and store the address code of the address code response data packet at the moment, namely 2;
s35, after the address code response data packet time slices of the equal 2# sub-controllers are completed, all the sub-controllers behind the 2# sub-controllers receive the address code +1 in the latest address code response data packet, which is 3 at the moment, and compare with the own address code, if the address code response data packets are equal, the address code response data packet containing the address code information of the sub-controllers is sent, the 3# sub-controllers do not send data any more, and the sub-controllers behind the 3# sub-controllers can receive the address code response data packet at the moment and store the address code of the address code response data packet at the moment, which is 3 at the moment;
s36, the same is done until the n# sub-controllers complete address code response data, and the waiting time slices are completed, namely, all sub-controller address code response operations are completed;
s37, waiting for the master controller in the step S31 to finish delaying n+1 time slices, and judging whether the number of address codes in the last address code response data packet is the same as the number of the set sub controllers by the master controller, if so, checking the address codes correctly; otherwise, the address code checks for errors.
2. The method for identifying an address code based on optical fiber serial communication according to claim 1, wherein the serial communication shares 1 serial data channel, and the serial communication uses a time division multiplexing method for communication.
3. The address code identification method based on optical fiber serial communication according to claim 2, wherein the serial communication is in time slices, and 1 time slice is a sum of a time of data packet transmission and a time of data packet interval.
4. The method for identifying address codes based on optical fiber serial communication according to claim 1, wherein the other control commands comprise identifying each sub-controller with an address code, and the sub-controllers determine whether to be control commands for themselves according to the address code of the master data packet.
5. The method for identifying an address code based on optical fiber serial communication according to claim 1, wherein when the address code is checked for abnormality, executing the address code resetting command as needed comprises the steps of:
s41, in the 1 st time slice, the main controller transmits an address code resetting data packet, after receiving the address code resetting data packet of the main controller, all partial controllers transmit interference data packets from the 2 nd time slice, wherein the interference data packets are used for enabling a transmitting optical mode Tx of each partial controller to be always on during the data transmission of the time slice, and shielding normal data from being transmitted backwards;
s42, a 2 nd time slice, the main controller sends an address code resetting response data packet with an address code of 0, the address code resetting response data packet is used for triggering the 1# sub-controller to set own address codes, after the main controller sends the address code resetting response data packet, no data packet can be sent until the address initialization of all the sub-controllers is completed, the data packet of the 2 nd time slice can be normally received only by the 1# sub-controller connected with the main controller sending an optical mode Tx, because the all the sub-controllers send interference data packets at the moment, all the sub-controllers after the 1# sub-controller only receive the interference data packet, the packet head, the packet tail and various check codes can not be normally checked, the data packet can be discarded and not responded, the 1# sub-controller resets the response data packet according to the received address codes, extracts the address codes in the packet and adds 1 to be processed, and then the address codes in the packet are saved as own address codes, and the address codes of the 1# sub-controller are successfully set at the moment, and the address code setting of 1 is successful;
s43, after the 3 rd time slice, the 1# sub-controller stops sending the interference data packet backwards after setting the own address code, and sends the address code resetting response data packet carrying the own address code backwards, at the moment, only the 2# sub-controller with the physical position connected with the 1 st sub-controller sending optical mode Tx can receive the address code resetting response data packet, the 2# sub-controller stores the address code of the received address code resetting response data packet together with 1 as the own address code, and the address code of the 2# sub-controller is successfully set, at the moment, the 2;
s44, after the 4 th time slice, the 2# sub-controller stops sending the interference data packet backwards after setting the own address code, and sends the address code resetting response data packet carrying the own address code backwards, at the moment, only the 3# sub-controller, the physical position of which is connected with the 2 nd sub-controller sending optical mode Tx, can receive the address code resetting response data packet, the 3# sub-controller stores the address code of the received address code resetting response data packet together with 1 as the own address code, and the address code of the 3# sub-controller is successfully set, at the moment, the 3;
s45, analogically, until the nth sub-controller transmits the address code resetting response data packet;
s46, after the nth sub-controller sends out the own address code resetting response data packet, the main controller detects whether the number of the address codes carried in the address code resetting response data packet of the last sub-controller is the same as the number of the set sub-controllers, and if so, the address code resetting is successful; otherwise, the address code reset fails.
6. An apparatus employing the address code identification method based on optical fiber serial communication as claimed in any one of claims 1 to 5, characterized in that the apparatus comprises:
the 1 master controller is an active device for executing address code inspection, address code resetting and issuing control commands;
the plurality of sub controllers are passive devices for assisting the master controller to finish address code verification, address code resetting and master controller control command execution;
the optical fiber is a communication medium between the master controller and the sub-controllers and between the sub-controllers;
the master controller is in serial communication with the sub controllers through the optical fiber connection;
the main controller sends an address code checking command to check the address code, and the address code of each sub-controller is stored in a communication control chip inside each sub-controller, which comprises the following steps:
s31, the master controller sends an address code checking command data packet and delays, wherein the delay time is greater than n+1 time slices, n is the number of the sub controllers, and the master controller only receives data and does not send any data during the delay;
s32, after the main controller sends the address code verification command data packet, all sub controllers simultaneously receive the data packet, after the sub controllers receive the data packet, the sub controllers execute data verification and command analysis, and after the address code verification command sent by the main controller is analyzed, all the sub controllers wait for the completion of the current main controller data packet time slice;
s33, after the time slices of the data packets of the main controller are finished, all the sub controllers judge whether the address code of the sub controllers is 1, if the address code of the sub controllers is 1, the sub controllers send address code response data packets containing the address code information of the sub controllers, the sub controllers 1# do not send data any more, according to the unidirectional transmission principle of the data, the sub controllers behind the sub controllers 1# can all receive the address code response data packets of the sub controllers 1# and store the address code of the address code response data packets, and the address code is 1 at the moment;
s34, after the address code response data packet time slices of the 1# sub-controllers are finished, all sub-controllers behind the 1# sub-controllers receive the address code +1 in the latest address code response data packet, namely 2 at the moment, and compare the latest address code with the own address code, if the latest address code is equal to the latest address code, the address code response data packet containing the address code information of the sub-controllers is transmitted, the 2# sub-controllers do not transmit data any more, and the sub-controllers behind the 2# sub-controllers can receive the address code response data packet at the moment and store the address code of the address code response data packet at the moment, namely 2;
s35, after the address code response data packet time slices of the equal 2# sub-controllers are completed, all the sub-controllers behind the 2# sub-controllers receive the address code +1 in the latest address code response data packet, which is 3 at the moment, and compare with the own address code, if the address code response data packets are equal, the address code response data packet containing the address code information of the sub-controllers is sent, the 3# sub-controllers do not send data any more, and the sub-controllers behind the 3# sub-controllers can receive the address code response data packet at the moment and store the address code of the address code response data packet at the moment, which is 3 at the moment;
s36, the same is done until the n# sub-controllers complete address code response data, and the waiting time slices are completed, namely, all sub-controller address code response operations are completed;
s37, waiting for the master controller in the step S31 to finish delaying n+1 time slices, and judging whether the number of address codes in the last address code response data packet is the same as the number of the set sub controllers by the master controller, if so, checking the address codes correctly; otherwise, the address code checks for errors.
7. The apparatus of claim 6 wherein the primary master's transmit optical mode Tx is connected to the primary master's receive optical mode Rx, the primary master's transmit optical mode Tx is connected to the secondary master's receive optical mode Rx, the secondary master's transmit optical mode Tx is connected to the secondary master's receive optical mode Rx, and so on, the primary master's transmit optical mode Tx is connected to the primary master's receive optical mode Rx, thus forming 1 closed serial communication device.
8. The apparatus of claim 7, wherein the transmitting optical mode Tx of the master converts an electrical signal into an optical signal, and is controlled by the communication control circuit of the master to perform operations of address code checking, address code resetting, and issuing a control command; the receiving optical mode Rx of the main controller converts the optical signal into an electric signal, monitors the correctness of the data in the serial data line and receives the feedback data of the sub-controllers; the receiving optical mode Rx of the sub-controller converts the optical signal into an electric signal, and the electric signal is directly converted into the optical signal through the transmitting optical mode Tx of the current sub-controller and transmitted to the next sub-controller, and the optical signal is transmitted into the communication control circuit of the current sub-controller, and the communication control circuit of the current sub-controller checks the correctness of the data, analyzes the data and makes judgment and execution.
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| TWI459774B (en) * | 2011-04-29 | 2014-11-01 | Ind Tech Res Inst | Asynchronous master-slave serial communication systam, data transmission method, and control module using the same thereof |
| CN112104760A (en) * | 2020-08-13 | 2020-12-18 | 四川虹美智能科技有限公司 | Address code allocation method, host and slave |
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| CN105786753A (en) * | 2016-02-22 | 2016-07-20 | 上海斐讯数据通信技术有限公司 | Method and device for data transmission between master and slave devices on I2C bus |
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