CN109346514A - A kind of chip and manufacturing method of reverse blocking IGBT - Google Patents
A kind of chip and manufacturing method of reverse blocking IGBT Download PDFInfo
- Publication number
- CN109346514A CN109346514A CN201811305722.2A CN201811305722A CN109346514A CN 109346514 A CN109346514 A CN 109346514A CN 201811305722 A CN201811305722 A CN 201811305722A CN 109346514 A CN109346514 A CN 109346514A
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- chip
- area
- hole slot
- diffusion
- contact
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- 230000000903 blocking effect Effects 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052796 boron Inorganic materials 0.000 claims abstract description 9
- 238000005240 physical vapour deposition Methods 0.000 claims abstract description 9
- 230000035755 proliferation Effects 0.000 claims abstract description 6
- 238000009826 distribution Methods 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 238000002474 experimental method Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
Abstract
The present invention relates to the chips and manufacturing method of a kind of reverse blocking IGBT.The present invention is in contact in chip edge area production hole slot with the area chip back collector P+, using physical vapor deposition, chip is put into the gas full of boron ion, boron ion is set to carry out horizontal proliferation along hole slot inner wall, until the diffusion junctions between hole slot are in contact, diffusion isolated area is formed around termination environment.It is different from conventional reverse blocking IGBT using diffusion method production isolated area feature: diffusion time is short, do not influenced by substrate thickness, isolated area usable floor area is few, chip area utilization rate is high.Hole trench bottom is in contact with the area backside collector P+, high tension apparatus is solved because substrate is thicker, diffusion isolated area bottom is difficult the problem being in contact with backside collector, the diffusion junctions between hole slot are only needed to be in contact, form the whole diffusion area P+, chip terminal area is isolated with chip edge, avoids the generation of chip edge area leakage current.
Description
Technical field:
The present invention relates to the power semiconductor device structure in technical field of semiconductors, reverse blocking IGBT terminal isolated area knots
Structure design.
Background technique
Conventional IGBT is for the on-state voltage drop V that compromisesonWith turn-off power loss Eoff, generally all have buffer layer smaller to obtain
VonAnd Eoff, since the doping concentration of buffer layer and collector layer is all very high, while chip edge is due to lattice damage and stress meeting
Cause biggish leakage current, so routine IGBT does not have reverse blocking capability.And reverse blocking IGBT uses traditional non-break-through
Type (NPT) structure, while overleaf being improved with side, effective edge isolation area P+ is designed at chip edge, makes side
Edge isolated area P+ and the area back side P+ are shorted, and to avoid lattice damage and the stress of chip edge that larger leakage current is caused to generate, are made
It has two-way blocking-up ability.The traditional edge reverse blocking IGBT P+ isolated area design, generallys use and spreads isolated area from top to bottom
Design.Fig. 4 A is shown in traditional reverse blocking IGBT edge isolation plot structure design, and Terminal Design, P+ isolated area is isolated using this diffusion
Being in contact with bottom surface P+ is the difficult point place of total design, and the low pressure reverse blocking IGBT relatively thin for substrate is easier to realize,
But for high tension apparatus higher for pressure resistance, substrate is thicker, realize more difficult.The substrate of high pressure reverse blocking IGBT is thicker, needs
Diffusion time that will be very long, P+ isolated area could be combined with back side P+, due to the presence of horizontal proliferation, P+ isolated area be caused to expand
Scattered area is very wide, and chip terminal area is caused largely to waste.
Summary of the invention
In order to more effectively avoid chip edge larger leakage current as caused by lattice damage and stress, and reduce expansion
It dissipates chip area caused by isolated area to waste, the present invention proposes that a kind of punch in terminal edge area (111) diffuses to form P+ isolation
Area (2), and the continuous arranged distribution of hole slot of these cylindrical types forms circulating type package point around chip terminal area (110)
Cloth.Sectional view is shown in that Fig. 4 B, top view are shown in that the diffusion effect figure between Fig. 4 C, cylindrical hole slot is shown in Fig. 4 D.Cylindrical hole grooved ring around
It is wrapped in around chip, slot bottom is in contact with the back side area P+ (1).Good cylindrical hole slot chip will be dug and use physical vapor deposition,
Chip is entered in the gas full of B (boron) ion, so that boron ion gas is carried out horizontal proliferation along cylindrical hole slot inner wall, reach
Diffusion zone between cylindrical hole slot is in contact, and effect picture is shown in figure D, ultimately forms and surrounds P+ isolated area (2).Chip is in physics
In vapor deposition, in order in a short time, make the diffusion zone of cylindrical hole slot be in contact, between general cylinder hole slot away from
From at 1 μm -20 μm or so.Therefore, the design of this structure is within shorter diffusion time and the lower feelings of chip edge usable floor area
Under condition, new P+ diffusion isolated area (2) can be formed, the generation of chip edge leakage current is effectively prevented.(note: chip has
Source region and termination environment are not the emphasis of the design, so not explaining excessively, it should be understood by those skilled in the art that its structure).
A kind of chip of reverse blocking IGBT, it is characterised in that: hole slot between the chip terminal area of reverse blocking IGBT and chip edge
Array surrounds the distribution of terminal circulating type, and hole slot array is a circle or multi-turn；Hole slot array is around package termination environment, single side hole slot
Structure is the chip in IGBT from aperture above: hole trench bottom and back side P+ offset are from 0 μm -50 μm, 1 μm of adjacent holes separation -
1 μm -20 μm of spacing between 30 μm, multi-turn hole slot adjacent turn, two-sided hole slot structure is i.e. in the aperture simultaneously of the chip two sides of IGBT:
Lateral distance (121) 1 μm of -20 μm, hole slots of (122) 1 μm -30 μm of surface adjacent holes separation, surface hole slot and back side hole slot
Depth is the 40%-60% of substrate thickness.
Further, hole slot shape is cylindrical or is non-cylindrical.
Further, multi-turn is 2-3 circle.
Further, hole trench bottom and back side P+ offset open hole from 0 μm.
Chip edge area production hole slot is in contact with the area chip back collector P+, using physical vapor deposition, by chip
It is put into the gas full of boron ion, boron ion is made to carry out horizontal proliferation along hole slot inner wall, until the diffusion junctions between hole slot
It is in contact, forms diffusion isolated area around termination environment.
Advantage designed by the present invention: the present invention is greatly reduced chip terminal area area, can be by existing reverse blocking IGBT
Termination environment area reduces 65-85%.When making the isolated area area P+ of same effect, the present invention can be in shorter time divergent contour
At the isolation area P+, avoid that it is longer to make the area P+ diffusion time using conventional diffusion legal system, laterally expands because high tension apparatus substrate is thicker
It dissipates and occupies great amount of terminals area area, the top-down area diffusion P+, which is difficult to be in contact with the back side area P+, causes the area P+ not play protection
The effect of isolation.The present invention is not influenced by substrate thickness, using physical vapor deposition, realizes B (boron) ion from cylindrical hole slot
Inner wall horizontal proliferation, two neighboring cylindrical hole sinker-diffusion region domain are in contact to form diffusion isolated area P+, effectively prevent chip
The generation of marginal zone leakage current.In the case where realizing identical diffusion P+ isolated area, the present invention is not constrained by substrate thickness, effective real
Existing P+ diffusion isolated area is in contact with back side P+, while reducing the usable floor area in chip edge area, improves the utilization of chip area
Rate.
Detailed description of the invention
Above and other purpose of the invention, feature and advantage are become more fully apparent by attached drawing.Each area in figure
Domain is not necessarily drawn to scale but focuses on and illustrate structure of the invention, wherein in all figures " ... " represent it is unillustrated
Cylindrical hole slot.
Fig. 1 illustrates with single cylindrical hole grooved ring around distribution terminal area reverse blocking IGBT top view；
Fig. 2 illustrates the cylindrical hole grooved ring with double isosceles triangle array and overlooks around distribution terminal area reverse blocking IGBT
Figure.
Fig. 3 is illustrated with two-sided crossed-circle cylindricality hole slot terminal isolated area sectional structure chart, in which: 121-surfaces circle
Spacing between the lateral distance of cylindricality hole slot and rear cylindrical hole slot, 122-surface cylindrical hole slots.
Fig. 3 A is illustrated with two-sided crossed-circle cylindricality hole slot terminal isolated area top view.
Fig. 4 A illustrates conventional diffusion technology manufacture reverse blocking IGBT terminal isolated area diagrammatic cross-section；
Fig. 4 B illustrates the present invention and termination environment design profile schematic diagram is isolated with cylindrical hole slot, in which: 1-back side P+
Area's (collector), 2-P+ isolated areas (the diffusion isolated area that cylindrical hole slot diffuses to form), 3-field limiting rings, the cut-off of 4-n shapes
Ring, 5-N+ emitters, the 6-areas P-, 7-field oxides, 8-gate oxides, 110-terminal sector widths, 100-active areas are wide
Degree, 111-terminal edge areas.
Fig. 4 C illustrates the reverse blocking IGBT structure top view with cylindrical hole slot, in which: d-cylindrical hole separation,
R-cylinder hole slot internal diameter；
Fig. 4 D illustrates cylindrical hole slot diffusion junctions under physical vapor deposition and contacts the effect picture to be formed；
Specific embodiment:
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical solution in the embodiment of the present invention clearly and completely illustrated with structure.
The distance between cylindrical hole slot, by the method for physical vapor deposition, makes to justify between 1 μm -20 μm in Fig. 4 C
Diffusion junctions between cylindricality hole slot are in contact to form P+ isolated area.
Three kinds of reverse blocking IGBT terminal edge isolated areas, which are provided, based on the principle present invention makes embodiment.Specifically:
Embodiment one:
Single cylindrical hole slot array is used in the present embodiment as shown in Figure 1, N- substrate doping is 1e13cm-3—
5e13cm-3, 400 μm -550 μm of thickness (of different sizes according to pressure resistance).(100) 200 μm -400 μm of chip active sector width, eventually
(110) 200 μm -1000 μm of petiolarea width (according to the of different sizes of pressure resistance), 1 μm of -20 μm of left side of the distance between cylindrical hole slot
Right (depending on chip entirety size), 5 μm -30 μm of internal diameter (depending on chip area) of cylindrical hole slot, physical vapor
Deposit uses concentration 1e20cm-3-5e20cm-3B ionized gas.By experiment and emulation testing, obtain it is identical diffusion every
When from area P+, the present invention accounts for the 1%-10% of conventional diffusion method time required diffusion time.Chip side needed for the structure
Edge area area reduces 80%-95%, to effectively reduce device area.
Embodiment two:
Double isosceles triangle cylinder hole slot array is used in the present embodiment as shown in Fig. 2, N- substrate doping for
1e13cm-3—5e13cm-3, 400 μm -550 μm of thickness (of different sizes according to pressure resistance).(100) 200 μ of chip active sector width
M-400 μm, (110) 200 μm -1000 μm of terminal sector width (according to the of different sizes of pressure resistance), between outermost cylinder hole slot
10 μm -20 μm or so of distance (depending on chip entirety size), inside enclose cylindrical hole slot and two cylindrical holes of outermost
Slot formed isosceles triangle, outermost cylinder hole slot with it is interior enclose 1 μm -10 μm of the distance between cylindrical hole slot (it is small with it is peripheral
The distance between hole slot), 5 μm -30 μm of cylindrical hole slot internal diameter (depending on chip area), physical vapor deposition uses concentration
1e20cm-3-5e20cm-3B ionized gas, diffusion isolated area area increase 1.5-2 times.By experiment and emulation testing, obtaining
When to identical diffusion isolated area P+, the present invention accounts for the 1%-10% of conventional diffusion method time required diffusion time.The knot
Chip edge area area needed for structure reduces 70%-80%, to effectively reduce device area while increase isolated area P+
The generation of width reduction chip edge area leakage current.
Embodiment three:
In the present embodiment using two-sided non-break-through crossed-circle cylindricality hole slot array as shown in Fig. 3 chip profile, N- substrate is mixed
Miscellaneous concentration is 1e13cm-3—5e13cm-3, 400 μm -550 μm of thickness (of different sizes according to pressure resistance).Chip active sector width
200 μm -400 μm, 200 μm -1000 μm of terminal sector width (according to the of different sizes of pressure resistance), between chip surface cylinder hole slot
(122) 10 μm -20 μm or so of distance, it is (121) 1 μm -10 μm of lateral distance of back side hole slot and two hole slots in surface, cylindrical
5 μm -30 μm of hole slot internal diameter, hole groove depth accounts for the 40%-60% of substrate thickness, and physical vapor deposition uses concentration 1e20cm-3-
5e20cm-3B ionized gas, chip surface cylinder hole slot and die bottom surface cylindrical type hole slot cross-distribution top view are as schemed
Shown in 3A.By experiment and emulation testing, when obtaining identical diffusion isolated area P+, the present invention accounts for biography required diffusion time
The 1%-10% of system method of diffusion time.Chip edge area area needed for the structure reduces 80%-90%, to effectively subtract
Small device area increases isolated area P+ width simultaneously reduces the generation of chip edge area leakage current.
Claims (5)
1. a kind of chip of reverse blocking IGBT, it is characterised in that: hole slot battle array between the chip terminal area of reverse blocking IGBT and chip edge
Column surround the distribution of terminal circulating type, and hole slot array is a circle or multi-turn；Hole slot array is around package termination environment, single side hole slot knot
Structure is the chip in IGBT from aperture above: hole trench bottom and back side P+ offset are from 1 μm of -30 0 μm -50 μm, adjacent holes separation μ
M, 1 μm -20 μm of the spacing between multi-turn hole slot adjacent turn, two-sided hole slot structure is i.e. in the aperture simultaneously of the chip two sides of IGBT: table
(121) 1 μm -20 μm of lateral distance, the hole groove depth of (122) 1 μm -30 μm of face adjacent holes separation, surface hole slot and back side hole slot
Degree is the 40%-60% of substrate thickness.
2. chip according to claim 1, it is characterised in that: hole slot shape is cylindrical or is non-cylindrical.
3. chip according to claim 1, it is characterised in that: multi-turn is 2-3 circle.
4. chip according to claim 1, it is characterised in that: hole trench bottom and back side P+ offset open hole from 0 μm.
5. preparing a kind of method of the chip of reverse blocking IGBT as described in claim 1, it is characterised in that: chip edge area makes hole
Slot is in contact with the area chip back collector P+, using physical vapor deposition, chip is put into the gas full of boron ion, is made
Boron ion carries out horizontal proliferation along hole slot inner wall, until the diffusion junctions between hole slot are in contact, forms diffusion around termination environment
Isolated area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811305722.2A CN109346514A (en) | 2018-11-05 | 2018-11-05 | A kind of chip and manufacturing method of reverse blocking IGBT |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811305722.2A CN109346514A (en) | 2018-11-05 | 2018-11-05 | A kind of chip and manufacturing method of reverse blocking IGBT |
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| Publication Number | Publication Date |
|---|---|
| CN109346514A true CN109346514A (en) | 2019-02-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811305722.2A Pending CN109346514A (en) | 2018-11-05 | 2018-11-05 | A kind of chip and manufacturing method of reverse blocking IGBT |
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| Country | Link |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111293172A (en) * | 2020-02-19 | 2020-06-16 | 北京工业大学 | Reverse-blocking IGBT terminal structure |
| CN112133742A (en) * | 2020-10-29 | 2020-12-25 | 西安众力为半导体科技有限公司 | IGBT device back protection ring structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1581506A (en) * | 2003-08-08 | 2005-02-16 | 三菱电机株式会社 | Vertical semiconductor device and manufacturing method thereof |
| EP3142143A1 (en) * | 2015-09-11 | 2017-03-15 | ABB Technology AG | Method for manufacturing a power semiconductor device |
| CN106711037A (en) * | 2015-11-12 | 2017-05-24 | 上海联星电子有限公司 | Fabrication method of RB-IGBT (Reverse Blocking Insulated Gate Bipolar Transistor) chip and RB-IGBT (Reverse Blocking Insulated Gate Bipolar Transistor) chip |
| CN107665922A (en) * | 2016-07-29 | 2018-02-06 | 英飞凌科技奥地利有限公司 | Reverse blocking IGBT |
| US9922864B2 (en) * | 2015-11-20 | 2018-03-20 | Ixys Corporation | Trench separation diffusion for high voltage device |
-
2018
- 2018-11-05 CN CN201811305722.2A patent/CN109346514A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1581506A (en) * | 2003-08-08 | 2005-02-16 | 三菱电机株式会社 | Vertical semiconductor device and manufacturing method thereof |
| EP3142143A1 (en) * | 2015-09-11 | 2017-03-15 | ABB Technology AG | Method for manufacturing a power semiconductor device |
| CN106711037A (en) * | 2015-11-12 | 2017-05-24 | 上海联星电子有限公司 | Fabrication method of RB-IGBT (Reverse Blocking Insulated Gate Bipolar Transistor) chip and RB-IGBT (Reverse Blocking Insulated Gate Bipolar Transistor) chip |
| US9922864B2 (en) * | 2015-11-20 | 2018-03-20 | Ixys Corporation | Trench separation diffusion for high voltage device |
| CN107665922A (en) * | 2016-07-29 | 2018-02-06 | 英飞凌科技奥地利有限公司 | Reverse blocking IGBT |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111293172A (en) * | 2020-02-19 | 2020-06-16 | 北京工业大学 | Reverse-blocking IGBT terminal structure |
| CN111293172B (en) * | 2020-02-19 | 2023-10-10 | 北京工业大学 | Terminal structure of reverse-resistance IGBT |
| CN112133742A (en) * | 2020-10-29 | 2020-12-25 | 西安众力为半导体科技有限公司 | IGBT device back protection ring structure |
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Application publication date: 20190215 |