CN106684131A - Power device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a power device and a manufacturing method thereof. The power device comprises an N-well, an N-substrate, a P-base region, a polysilicon grid, an N+ source electrode region, a P+ ohmic contact region, an emitting metal electrode and a grid oxide layer. The power device uses a groove grid structure. The power device also comprises a P-well. The N+ source electrode region, the P-base region, the N-well and the P-well are arranged from the top to the bottom in turn. The P-well surrounds the groove bottom of the groove grid structure. As for the P-well, the intensity of the electric field of the groove bottom is reduced in disconnection of the power device by accelerating run-out of the carriers of the N-well. The technical problem of reduction of the voltage withstand characteristic of the device caused by the high concentration N-well can be solved, and the technical problems of high cost, high process difficulty and small range of doping concentration adjustment of the conventional manufacturing technology of the P-well can be solved so that the device is enabled to still maintain the great voltage withstand characteristic under the high concentration N-well, and thus the contradictory relationship between power consumption and voltage withstanding of the device can be optimized.

Description

A kind of power device and preparation method thereof

Technical field

The present invention relates to power semiconductor technologies field, more particularly, to a kind of IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) power device and preparation method thereof.

Background technology

In the prior art, in order to optimize the on-state voltage drop and turn-off power loss of power device, the power consumption of device is reduced, it is general to adopt Carrier accumulation layer (hole blocking layer) structure, this structure is otherwise known as " N-Enhancement Layer " (N- enhancement layers) And " Carrier Storage N Layer " (N-type carrier accumulation layer).As shown in Figure 1, it is based on carrier accumulation layer The IGBT of planar gate structure, the structure is surrounded in the lower section of P- bases one layer of N- enhancement layer 13, and 8 is emitter stage gold in figure Category electrode, 12 is collector electrode metal electrode.The applicant applies on December 07th, 2012, and in 2013 03 The moon 13 is open, and notification number is the Chinese invention patent of CN102969351B《A kind of plane grid-type igbt chip》I.e. Disclose said structure.Again as shown in Figure 2, it is the IGBT based on carrier accumulation layer trench gate structure, the structure is in P- The lower section of base arranges a N trap (N-type carrier accumulation layer 17) to surround P- bases, and the gesture in a hole is formed in this place Build, block hole under conducting state and be launched the extraction of pole electrode, and increase emitter stage electron injection, so as to enhance this The conductivity modulation effect at place, while reducing on-state voltage drop.In figure, 4 is polysilicon gate, and 8 is emitter metal electrode, 12 For collector electrode metal electrode, 17 is N-type carrier accumulation layer.The applicant applies on December 07th, 2012, and in On 03 13rd, 2013 open, the Chinese invention application of Publication No. CN102969350A《A kind of trench gate IGBT Chip》Disclose said structure.Because the hole that this structure is not relying on increasing back colelctor electrode is injected to realize, from And back hole injection efficiency can be optimized, and further reduce the turn-off power loss of device.Structure as shown in Figure 2 In, surrounding on the top of gate oxide 9 has layer of metal barrier layer 14, and P+ diffusion layers are provided between two grooves 15 and emission layer 16.

Generally, the doping content of N traps is higher than the concentration of N- substrate, and as the doping content of N traps is improved, can Further to reduce the on-state voltage drop of power device.However, with the increase of N trap concentration, under the voltage endurance capability of device occurs Drop, this is, because high concentration N trap have impact on device carrier depletion speed in the off case, to cause channel bottom position Electric field is concentrated (as shown in accompanying drawing 3,4 and 5), therefore generates high electric-field intensity, have impact on the pressure performance of device.

The content of the invention

In view of this, it is an object of the invention to provide a kind of power device and preparation method thereof, can solve the problem that high concentration N trap institute The technical problem that the device voltage endurance that brings declines so that device still can keep good resistance under high concentration N trap Pressure characteristic, so as to optimize device power consumption with pressure contradictory relation.

In order to realize foregoing invention purpose, the present invention specifically provides a kind of technic relization scheme of power device, a kind of power device Part, including：N traps, N- substrates, P- bases, polysilicon gate, N+ source areas, P+ ohmic contact regions, emitter metal electrode And gate oxide, power device adopts trench gate structure.Power device also includes p-well, N+ source areas, P- bases, N traps, P Trap is arranged in order from top to bottom, and the p-well surrounds the channel bottom of the trench gate structure.

Preferably, the dopant concentration peak of the p-well is located at the bottom of the groove.

Preferably, the p-well reduces the ditch when the power device is turned off by accelerating the exhausting for carrier of the N traps The electric-field intensity of trench bottom.

Preferably, doping content of the doping content of the p-well higher than the N traps.

Preferably, the p-well connects with the doping content curve of the N traps.

Preferably, when trench gate structure of the power device using effective grid, positioned at two p-wells of effective gate bottom From.

Preferably, when the trench gate structure of power device includes effective grid, and the two or more for being arranged at effective grid both sides During false grid, two p-wells positioned at effective gate bottom are from positioned at described false grid and effective gate bottom adjacent to each other P-well from or be connected, positioned at two false grid bottoms adjacent to each other p-well from or it is connected.

The present invention specifically provides a kind of technic relization scheme of power device preparation method as described above, power device preparation method, Comprise the following steps：

S101：N trap making is carried out on the basis of N- substrates；

S102：The making of P- bases is carried out on the N traps；

S103：On the basis of previous step, groove making is carried out；

S104：P-well injection is carried out by the groove, p-well is formed；

S105：Gate oxide making and polysilicon filling are carried out in the groove；

S106：N+ source area making is carried out between two grooves；

S107：Complete subsequent technique.

The present invention also specifically provides the technic relization scheme of another kind of power device preparation method as mentioned above, a kind of power device Preparation method, when the distance between effective grid is equal to the distance between false grid adjacent to each other and effective grid, the method bag Include following steps：

S111：P-well making is carried out on the basis of N- substrates；

S101：On the basis of previous step, N trap making is carried out；

S102：The making of P- bases is carried out on the N traps；

S103：On the basis of previous step, groove making is carried out；

S105：Gate oxide making and polysilicon filling are carried out in the groove；

S106：N+ source area making is carried out between two grooves；

S107：Complete subsequent technique.

Preferably, step S101 is further included：

S1011：By high-temperature oxydation, one layer of sacrificial oxide layer, institute are made to the front of device on the basis of the N- substrates The thickness for stating sacrificial oxide layer is 100A～600A；

S1012：One layer of photoresist is coated on the sacrificial oxide layer, is then exposed, and above removal devices effective district Photoresist, forms N traps injection window；

S1013：Carry out N-type ion implanting, and the photoresist of removal devices surface residual；

S1014：High temperature propulsion is carried out, N traps are ultimately formed, the doping content of the N traps is in 1e16/cm³It is described below magnitude The junction depth of N traps is 3 μm～8 μm.

Preferably, step S111 is further included：

S1111：By high-temperature oxydation, one layer of sacrificial oxide layer, institute are made to the front of device on the basis of the N- substrates The thickness for stating sacrificial oxide layer is 100A～600A；

S1112：One layer of photoresist is coated on the sacrificial oxide layer, is then exposed, and above removal devices effective district Photoresist, forms p-well injection window；

S1113：Carry out p-type ion implanting, and the photoresist of removal devices surface residual；

S1114：High temperature propulsion is carried out, p-well is ultimately formed, the doping content of the p-well is in 1e16/cm³It is described below magnitude The junction depth of p-well is 3 μm～8 μm.

Preferably, step S102 is further included：

S1021：By high-temperature oxydation, one layer of sacrificial oxide layer is made on the N traps, the thickness of the sacrificial oxide layer is 100A～600A；

S1022：One layer of photoresist is coated on the sacrificial oxide layer, is then exposed, and above removal devices effective district Photoresist, forms P- bases injection window；

S1023：Carry out p-type ion implanting, and the photoresist of removal devices surface residual, and the photoetching of removal devices surface residual Glue；

S1024：High temperature propulsion is carried out, P- bases are ultimately formed, the doping content of the P- bases is in 1e17/cm³It is more than magnitude, The junction depth of the P- bases is 3 μm～8 μm.

Preferably, step S103 is further included：

S1031：Perform etching window moulding：One layer of photoresist is first coated, is then exposed and is removed photoresist, form etching groove window Mouthful；

S1032：Etching groove is carried out, until target depth, junction depth of the target depth more than or equal to the N traps.

Preferably, step S104 is further included：

S1041：P-type ion implanting is carried out to device effective district；

S1042：High temperature propulsion is carried out, p-well is formed, the doping content of the p-well is higher than the doping content of the N traps.

Preferably, step S105 is further included：

S1051：High-temperature oxydation being carried out, makes trench wall grow one layer of gate oxide, the thickness of the gate oxide is 0.1 μm～ 0.5μm；

S1052：Polysilicon deposition is carried out, the polysilicon fills the inside of groove；

S1053：N-type doping is carried out to the polysilicon, doping content is 1e19/cm³It is more than magnitude；

Step S1053 is further included：

N-type ion implanting is carried out first, and doping, the surface shape of the polysilicon after propulsion are then realized by high temperature propulsion Into layer of oxide layer.

Preferably, step S106 is further included：

S1061：Perform etching window moulding：One layer of photoresist is first coated, is then exposed and is removed photoresist, form N+ source areas Injection window；

S1062：N-type ion implanting is carried out, and removes remaining photoresist；

S1063：High temperature propulsion is carried out, N+ source areas are formed, the doping content of the N+ source areas is 1e19/cm³It is more than magnitude, The junction depth of the N+ source areas is less than 1 μm.

The present invention specifically provides the technic relization scheme of the third power device preparation method as described above, a kind of power device system Make method, comprise the following steps：

S201：The making of P- bases is carried out on the basis of N- substrates；

S202：On the basis of previous step, etching groove is carried out；

S203：N trap injections are carried out by the groove, N traps are formed；

S204：Proceed etching groove until target depth；

S205：P-well injection is carried out by the groove, p-well is formed；

S206：Gate oxide making and polysilicon filling are carried out in the groove；

S207：N+ source area making is carried out between two grooves；

S208：Complete subsequent technique.

The present invention also specifically provides the technic relization scheme of the 4th kind of power device preparation method as described above, a kind of power device Preparation method, when the distance between described effective grid is equal to the distance between described false grid adjacent to each other and effective grid, The method comprising the steps of：

S211：P-well making is carried out on the basis of N- substrates；

S201：On the basis of previous step, the making of P- bases is carried out；

S202：On the basis of previous step, etching groove is carried out；

S203：N trap injections are carried out by the groove, N traps are formed；

S204：Proceed etching groove until target depth；

S206：Gate oxide making and polysilicon filling are carried out in the groove；

S207：N+ source area making is carried out between two grooves；

S208：Complete subsequent technique.

Preferably, step S201 is further included：

S2011：By high-temperature oxydation, one layer of sacrificial oxide layer is made to the front of device on the basis of N- substrates, it is described sacrificial The thickness of domestic animal oxide layer is 100A～600A；

S2012：One layer of photoresist is coated on the sacrificial oxide layer, is then exposed, and above removal devices effective district Photoresist, forms P- bases injection window；

S2013：Carry out p-type ion implanting, and the photoresist of removal devices surface residual；

S2014：High temperature propulsion is carried out, the P- bases are ultimately formed, the doping content of the P- bases is in 1e17/cm³Magnitude More than, the junction depth of the P- bases is 3 μm～8 μm.

Preferably, step S211 is further included：

S2111：By high-temperature oxydation, one layer of sacrificial oxide layer is made to the front of device on the basis of N- substrates, it is described sacrificial The thickness of domestic animal oxide layer is 100A～600A；

S2112：One layer of photoresist is coated on the sacrificial oxide layer, is then exposed, and above removal devices effective district Photoresist, forms p-well injection window；

S2113：Carry out p-type ion implanting, and the photoresist of removal devices surface residual；

S2114：High temperature propulsion is carried out, the p-well is ultimately formed, the doping content of the p-well is in 1e16/cm³Below magnitude, The junction depth of the p-well is 3 μm～8 μm.

Preferably, step S202 is further included：

S2021：Perform etching window moulding：One layer of photoresist is first coated, is then exposed and is removed photoresist, form etching groove window Mouthful；

S2022：Etching groove is carried out, until the first depth, junction depth of first depth more than or equal to the P- bases.

Preferably, step S203 is further included：

S2031：N-type ion implanting is carried out to whole device；

S2032：High temperature propulsion is carried out, N traps are formed, the doping content of the N traps is in 1e14/cm³～1e17/cm³Magnitude model In enclosing, the junction depth of the N traps is less than 3 μm.

Preferably, step S204 is further included：

S2041：Perform etching window moulding：One layer of photoresist is first coated, is then exposed and is removed photoresist, form etching groove window Mouthful；

S2042：Carry out etching groove, until the second depth, second depth for groove projected depth, the design depth of groove Degree is between 4 μm～8 μm.

Preferably, step S205 is further included：

P-type ion implanting is carried out to device effective district, the doping content of the p-well is less than the doping content of the N+ source areas.

Preferably, step S206 is further included：

S2061：High-temperature oxydation being carried out, makes trench wall grow one layer of gate oxide, the thickness of the gate oxide is 0.1 μm～ 0.5μm；

S2062：Polysilicon deposition is carried out, the polysilicon fills the inside of groove；

S2063：N-type doping is carried out to the polysilicon, doping content is 1e19/cm³It is more than magnitude.

Step S2063 is further included：

N-type ion implanting is carried out first, and doping, the surface shape of the polysilicon after propulsion are then realized by high temperature propulsion Into layer of oxide layer.

Preferably, step S207 is further included：

S2071：Perform etching window moulding：One layer of photoresist is first coated, is then exposed and is removed photoresist, form N+ source areas Injection window；

S2072：N-type ion implanting is carried out, and removes remaining photoresist；

S2073：High temperature propulsion is carried out, N+ source areas are formed, the doping content of the N+ source areas is 1e19/cm³It is more than magnitude, The junction depth of the N+ source areas is less than 1 μm.

By the technical scheme for implementing the power device that the invention described above is provided and preparation method thereof, have the advantages that：

(1) present invention improves the pressure performance of high concentration N trap trench-gate power devices, optimizes the on-state voltage drop (work(of IGBT Consumption) with pressure contradictory relation；

(2) p-well process costs of the invention are than energetic ion injection technology low cost；

(3) p-well diffusion technique of the invention does not affect the concentration and junction depth of N traps, P- bases and N+ source areas, reduces work Skill complexity and difficulty；

(4) present invention carries out autoregistration injection using groove, without the need for increasing photolithography plate newly；

(5) p-well concentration of the present invention adjusts easy, and it is big to adjust window ranges.

Description of the drawings

In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or prior art The accompanying drawing to be used needed for description is briefly described.It should be evident that drawings in the following description are only the one of the present invention A little embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can be with according to these Accompanying drawing obtains other embodiments.

Fig. 1 is the power device cross-sectional view in prior art based on carrier accumulation layer planar gate structure；

Fig. 2 is the power device cross-sectional view in prior art based on carrier accumulation layer trench gate structure；

Fig. 3 is the internal electric field distribution schematic diagram of prior art trench-gate power devices device；

Fig. 4 is the electric-field intensity schematic diagram in Fig. 3 at C4 tangent lines；

Fig. 5 is the electric-field intensity schematic diagram in Fig. 3 at C3 and C5 tangent lines；

Fig. 6 is a kind of cross-sectional view of specific embodiment of power device of the present invention；

Fig. 7 be Fig. 6 of the present invention device profile structural representation in doping content curve synoptic diagram at A-A ' tangent lines；

Fig. 8 is the schematic diagram that N trap making steps are carried out in a kind of specific embodiment of power device preparation method of the present invention；

Fig. 9 is the schematic diagram that P- bases making step is carried out in a kind of specific embodiment of power device preparation method of the present invention；

Figure 10 is the schematic diagram that groove making step is carried out in a kind of specific embodiment of power device preparation method of the present invention；

Figure 11 is the schematic diagram that p-well implantation step is carried out in a kind of specific embodiment of power device preparation method of the present invention；

Figure 12 is that gate oxide making and polysilicon filling are carried out in a kind of specific embodiment of power device preparation method of the present invention The schematic diagram of step；

Figure 13 is the schematic diagram that N+ source area making steps are carried out in a kind of specific embodiment of power device preparation method of the present invention；

Figure 14 is the schematic diagram that subsequent technique making step is carried out in a kind of specific embodiment of power device preparation method of the present invention；

Figure 15 is the schematic diagram that P- bases making step is carried out in power device preparation method another kind specific embodiment of the present invention；

Figure 16 is the schematic diagram that groove making step is carried out in power device preparation method another kind specific embodiment of the present invention；

Figure 17 is the schematic diagram that N trap implantation steps are carried out in power device preparation method another kind specific embodiment of the present invention；

Figure 18 is to carry out high temperature in power device preparation method another kind specific embodiment of the present invention to advance and formed N trap steps Schematic diagram；

Figure 19 is the signal that the secondarily etched step of groove is carried out in power device preparation method another kind specific embodiment of the present invention Figure；

Figure 20 is the schematic diagram that p-well implantation step is carried out in power device preparation method another kind specific embodiment of the present invention；

Figure 21 is to carry out gate oxide making in power device preparation method of the present invention another kind specific embodiment and polysilicon is filled out Fill the schematic diagram of step；

Figure 22 is the signal that N+ source area making steps are carried out in power device preparation method another kind specific embodiment of the present invention Figure；

Figure 23 is the signal that subsequent technique making step is carried out in power device preparation method another kind specific embodiment of the present invention Figure；

Figure 24 is the cross-sectional view of power device another kind specific embodiment of the present invention；

Figure 25 is the cross-sectional view of the third specific embodiment of power device of the present invention；

Figure 26 is the size marking schematic diagram of power device cross-section structure in the third specific embodiment of the invention；

Figure 27 is the cross-sectional view of 4th kind of specific embodiment of power device of the present invention；

Figure 28 is impact schematic diagram of the diffusion junction depth of p-well in the present invention to electric-field intensity；

Figure 29 is impact schematic diagram of the diffusion junction depth of p-well in the present invention to on-state voltage drop；

Figure 30 is the close-up schematic view of Figure 29 of the present invention；

Figure 31 is impact schematic diagram of the doping content of p-well in the present invention to on-state voltage drop；

Figure 32 is the close-up schematic view of Figure 31 of the present invention；

Figure 33 is the doping content of p-well in the present invention to pressure impact schematic diagram；

Figure 34 is the close-up schematic view of Figure 33 in the present invention；

Figure 35 is the partial structurtes enlarged diagram of part A in Figure 18；

In figure：1-N traps, 2-N- substrates, 3-P- bases, 4- polysilicon gates, 5-N+ source areas, 6-P traps, 7-P+ Europe Nurse contact zone, 8- emitter metal electrodes, 9- gate oxides, 10- photoresists, 11- sacrificial oxide layers, 11- colelctor electrodes Metal electrode, 13-N- enhancement layers, 14- metal barriers, 15-P+ diffusion layers, 16- emission layers, 17-N type carriers Accumulation layer, the effective grids of 20-, 30- vacation grid.

Specific embodiment

To make purpose, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention in it is attached Figure, to the technical scheme in the embodiment of the present invention clear, complete description is carried out.Obviously, described embodiment is only this A part of embodiment of invention, rather than the embodiment of whole.Based on the embodiment in the present invention, those of ordinary skill in the art The all other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.

As shown in accompanying drawing 6 to accompanying drawing 35, the specific embodiment of power device of the present invention and preparation method thereof is given, with reference to The invention will be further described for the drawings and specific embodiments.

Embodiment 1：

As shown in Figure 6, a kind of specific embodiment of power device, including：N traps 1, N- substrates 2, P- bases 3, polycrystalline Si-gate 4, N+ source areas 5, P+ ohmic contact regions 7, emitter metal electrode 8 and gate oxide 9, power device adopts groove Grid structure.Trench gate structure includes regular grid (effective grid) structure and dummy structure, the trench gate structure in the present embodiment Using conventional gate structure.P- bases 3, N traps 1, N- substrates 2 set gradually from top to bottom.N traps between two grooves 1 top is formed with P- bases 3, N+ source areas 5, P+ ohmic contact regions 7 and emitter metal electrode 8, wherein, P- bases 3 Positioned at the top of N traps 1, emitter metal electrode 8 is located at the middle part between two grooves, and P+ ohmic contact regions 7 are located at transmitting The bottom of pole metal electrode 8.N+ source areas 5 are located at the top of P- bases 3, and positioned at the both sides of emitter metal electrode 8. Groove further includes polysilicon gate 4, and positioned at the gate oxide 9 in the outside of polysilicon gate 4.Device front includes four doping, In the profile of power unit structure, N+ source areas 5, P- bases 3, N traps 1, p-well 6 are arranged in order from top to bottom.Work( Rate device also includes p-well 6, and p-well 6 surrounds the channel bottom of trench gate structure.The dopant concentration peak of p-well 6 is located at groove Bottom, to easily facilitate being embodied as the technical scheme.

P-well 6 exhausts reduction channel bottom when power device is turned off (under resistance to pressure condition) by the carrier of quickening N traps 1 Electric-field intensity.Meanwhile, the doping content of p-well 6 is higher than the doping content of N traps 1, to guarantee the load of the N traps 1 when pressure Stream all exhausts so that the pressure performance of device is optimal.

As shown in Figure 7, p-well 6 connects with the doping content curve of N traps 1, if the doping content of p-well 6 and N traps 1 Curve can not realize device on-state voltage drop from can not then realize the pressure optimum of device if two doping content curve curve intersections It is optimum.

When trench gate structure of the power device using effective grid, two p-wells 6 positioned at effective gate bottom are from device Electronics path is provided when part is turned on.P-well 6 from, refer to that the p-well 6 below adjacent two effectively grid is mutually isolated, It is discontiguous, as break-over of device when provide electronics path so that can enter into from the injected electrons of emitter metal electrode 8 The N- substrates 2 of device (device), participate in conductance modulation.

In order to improve the voltage endurance capability of the power device based on high concentration N trap 1, this specific embodiment draws in the bottom position of groove Enter p-well structure, accelerate exhausting for N trap carriers (under resistance to pressure condition) when device is turned off, reduce the electricity near channel bottom Field intensity, improves the voltage endurance capability of device.The technical scheme of the description of the specific embodiment of the invention 1 solves high concentration N trap institute band The technical problem that the device voltage endurance for coming declines, and solve the high cost of the conventional fabrication process of p-well, technology difficulty it is big, The technical problem such as doping content adjusting range is little so that device can still keep good voltage endurance under high concentration N trap, So as to optimize device power consumption and it is pressure between contradictory relation.

Embodiment 2：

The on-state voltage drop of trench gate IGBT is reduced with the raising of the doping content of N traps (carrier accumulation layer) 1, but The doping content of N traps 1 is improved to the pressure unfavorable of device, and main weak spot is the position that channel bottom is located.However, p-well 6 Manufacture craft there are many difficulties, such as：

In order to realize p-well structure, energetic ion injection technology can be adopted, but this can cause process costs higher.Meanwhile, Using the p-well 6 made by energetic ion injection technology, the peak value of its doping content is restricted, it is difficult to obtain the P of high concentration Well structure.Further, it is also possible to using conventional diffusion processes, but conventional diffusion processes need to carry out successively p-well 6, N traps 1, P- bases 3, and four diffusing, dopings of N+ source areas 5.This is accomplished by completing four diffusions in several microns of junction depth, Its technology difficulty is very big, and the collaboration optimization of four doping is extremely difficult, and the concentration that will finally cause p-well adjusts window Very little.

A kind of specific embodiment that the preparation method of power device described in example 1 is performed as described above, N traps 1 be using conventional diffusion processes come Make, the method is comprised the following steps：

S101：N traps 1 are carried out on the basis of N- substrates 2 to make, and using conventional diffusion processes, whole device (silicon chip) are entered Row injection, and high temperature propulsion technique is carried out, as shown in Figure 8.

Step S101 further includes procedure below：

S1011：By high-temperature oxydation, one layer of sacrificial oxide layer (SiO is made to the front of device on the basis of N- substrates 2₂, Silica) 11, the thickness of sacrificial oxide layer 11 is 100A～600A, preferred 300A；

S1012：One layer of photoresist 10 is coated on sacrificial oxide layer 11, is then exposed, and removal devices effective district (unit Born of the same parents area) above photoresist 10, form N traps injection window；

S1013：Carry out N-type ion implanting, and the photoresist 10 of removal devices surface residual；

S1014：High temperature propulsion (diffusion technique) is carried out, N traps 1 are ultimately formed, the doping content of N traps 1 is in 1e16/cm³Magnitude Hereinafter, preferred 1e15/cm³, the junction depth of N traps 1 is 3 μm～8 μm, preferably 5 μm.

S102：P- bases 3 are carried out on N traps 1 to make, and carry out the doping of P- bases 3 according to conventional diffusion processes and high temperature is advanced, As shown in Figure 9.

Step S102 further includes procedure below：

S1021：By high-temperature oxydation, (device front) makes one layer of sacrificial oxide layer 11, sacrificial oxide layer on N traps 1 11 thickness is 100A～600A, preferred 300A；

S1022：One layer of photoresist 10 is coated on sacrificial oxide layer 11, is then exposed, and removal devices effective district top The photoresist 10 in (device front), forms P- bases injection window；

S1023：Carry out p-type ion implanting, and the photoresist 10 of removal devices surface residual, and removal devices surface residual Photoresist 10；

S1024：High temperature propulsion (diffusion technique) is carried out, P- bases 3 are ultimately formed, the doping content of P- bases 3 is in 1e17/cm³ It is more than magnitude, preferred 1e17/cm³, the junction depth of P- bases 3 is 3 μm～8 μm, preferably 4 μm.

S103：On the basis of previous step, groove making is carried out, including etching groove window makes and etching, such as accompanying drawing 10 It is shown.

Step S103 further includes procedure below：

S1031：Perform etching window moulding：One layer of photoresist 10 is first coated, is then exposed and is removed photoresist, formed groove and carve Fenetre mouth；

S1032：Etching groove is carried out, until target depth, junction depth of the target depth more than or equal to N traps 1.

S104：P-well injection is carried out by groove, p-well 6 is formed, as shown in Figure 11.Due to the doping content of p-well 6 it is low In the doping content of N+ source areas 5, therefore p-well injection photolithography plate need not be set, whole device piece can all be injected.This When, high temperature propulsion first can not be carried out, but complete propulsion using the pyroprocess of subsequent technique.

Step S104 further includes procedure below：

S1041：P-type ion implanting is carried out to device effective district (cellular region)；

S1042：High temperature propulsion (diffusion technique) is carried out, p-well 6 is formed, the doping content of p-well 6 is dense higher than the doping of N traps 1 Degree.

S105：Carry out gate oxide 9 in groove to make and polysilicon filling, as shown in Figure 12.

Step S105 further includes procedure below：

S1051：High-temperature oxydation being carried out, makes trench wall grow one layer of gate oxide 9, the thickness of gate oxide 9 is 0.1 μm～ 0.5 μm, preferably 0.1 μm；

S1052：Polysilicon (Poly) deposition is carried out, polysilicon fills the inside of groove；

S1053：N-type doping is carried out to polysilicon, doping content is 1e19/cm³It is more than magnitude, preferred 1e20/cm³。

Step S1053 further includes procedure below：

N-type ion implanting being carried out first, doping then being realized by high temperature propulsion, the surface of polysilicon forms one after propulsion Layer oxide layer.

S106：Carry out N+ source areas 5 between two grooves to make, including N+ source areas injection window makes, injects and high temperature Propulsion, as shown in Figure 13.

Step S106 further includes procedure below：

S1061：Perform etching window moulding：One layer of photoresist 10 is first coated, is then exposed and is removed photoresist, form N+ source electrodes Window is injected in area；

S1062：N-type ion implanting is carried out, and removes remaining photoresist 10；

S1063：High temperature propulsion is carried out, N+ source areas 5 are formed, the doping content of N+ source areas 5 is 1e19/cm³It is more than magnitude, It is preferred that 1e20/cm³, the junction depth of N+ source areas 5 is less than 1 μm, preferably 0.5 μm.

S107：So far p-well 6, N traps 1, P- bases 3, and the making of N+ source areas 5, subsequent technique and routine are completed Manufacture craft is consistent, as shown in Figure 14.The common process of this part can be with specific reference to such as：CN102945804B China Its related production of the prior art such as patent of invention.

Realizing p-well structure, the diffusing, doping of p-well 6 exists the technique that the specific embodiment of the invention 2 is spread after etching groove Complete after remaining triple diffusion, and without the need for newly-increased photolithography plate, process costs inject low than energetic ion.Meanwhile, technique Difficulty declines to a great extent than four times conventional diffusions, and three doping contents above are not affected, without the need for being cooperateed with them Optimization, and the concentration of p-well 6 adjusts very easy, and it is big to adjust window.

Embodiment 3：

Another kind is performed as described above the specific embodiment of the preparation method of power device described in example 1, comprises the following steps：

S201：Carry out P- bases 3 on the basis of N- substrates 2 to make, routinely diffusion method carries out the doping of P- bases 3 and height Temperature propulsion, as shown in Figure 15.

Step S201 further includes procedure below：

S2011：By high-temperature oxydation, one layer of sacrificial oxide layer 11 is made to the front of device on the basis of N- substrates 2, it is sacrificial The thickness of domestic animal oxide layer 11 is 100A～600A, preferred 300A；

S2012：One layer of photoresist 10 is coated on sacrificial oxide layer 11, is then exposed, and removal devices effective district (unit Born of the same parents area) above photoresist 10, form P- bases injection window；

S2013：Carry out p-type ion implanting, and the photoresist 10 of removal devices surface residual；

S2014：High temperature propulsion (diffusion technique) is carried out, P- bases 3 are ultimately formed, the doping content of P- bases 3 is in 1e17/cm³ It is more than magnitude, preferred 1e17/cm³, the junction depth of P- bases 3 is 3 μm～8 μm, preferably 3 μm.

S202：On the basis of previous step, etching groove is carried out, including etching groove window makes and etching, etches into N Trap 1 peak concentration (the first depth a) places, as shown in Figure 16.

Step S202 further includes procedure below：

S2021：Perform etching window moulding：One layer of photoresist 10 is first coated, is then exposed and is removed photoresist, formed groove and carve Fenetre mouth；

S2022：Etching groove is carried out, until the first depth a, junction depth of first depth a more than or equal to P- bases 3.

S203：N trap injections are carried out by groove, as shown in Figure 17.Because the concentration of N traps 1 is less than N+ source areas 5 Concentration, and be shallow junction injection, therefore without the need for photolithography plate, directly whole wafer (device) can be injected.Then height is carried out Temperature propulsion, forms N traps 1, as shown in Figure 18.

Step S203 further includes procedure below：

S2031：N-type ion implanting is carried out to whole device, photoetching need not be carried out here, full wafer silicon chip (device) can be carried out Injection；

S2032：Carry out high temperature propulsion (diffusion technique), form N traps 1, the doping content of N traps 1 is regarded depending on designing, but dense Degree scope can be very big, typically in 1e14/cm³～1e17/cm³Order magnitude range in, preferred 1e17/cm³, the junction depth of N traps 1 is little In 3 μm, preferably 2 μm.And this is that common process method institute of the prior art is irrealizable.

S204：Proceed etching groove until target depth, as shown in Figure 19.

Step S204 further includes procedure below：

S2041：Perform etching window moulding：One layer of photoresist 10 is first coated, is then exposed and is removed photoresist, formed groove and carve Fenetre mouth；

S2042：Carry out etching groove, until the second depth b, the second depth b for groove projected depth, the design depth of groove Spend between 4 μm～8 μm, preferably 6 μm.

S205：P-well injection is carried out by groove, p-well 6 is formed, as shown in Figure 20.Due to the doping content of p-well 6 it is low In the doping content of N+ source areas 5, therefore p-well injection photolithography plate need not be set, whole silicon chip can all be injected.Now, High temperature propulsion first can not be carried out, but propulsion is completed using the pyroprocess of subsequent technique.

Step S205 further includes procedure below：

P-type ion implanting is carried out to device effective district (cellular region), the doping content of p-well 6 is less than the doping of N+ source areas 5 Concentration.Here high temperature propulsion is not first carried out, but is completed using subsequent high temperature process (pyroprocess that gate oxide 9 makes) Propulsion.

S206：Carry out gate oxide 9 in groove to make and polysilicon filling, as shown in Figure 21.

Step S206 is further included：

S2061：High-temperature oxydation being carried out, makes trench wall grow one layer of gate oxide 9, the thickness of gate oxide 9 is 0.1 μm～ 0.5 μm, preferably 0.1 μm；

S2062：Polysilicon (Poly) deposition is carried out, polysilicon fills the inside of groove；

S2063：N-type doping is carried out to polysilicon, doping content is 1e19/cm³It is more than magnitude, preferred 1e20/cm³。

Step S2063 further includes procedure below：

N-type ion implanting being carried out first, doping then being realized by high temperature propulsion, the surface of polysilicon forms one after propulsion Layer oxide layer.

S207：Carry out N+ source areas 5 between two grooves to make, including N+ source areas injection window makes, injects and high temperature Propulsion, as shown in Figure 22.

Step S207 further includes procedure below：

S2071：Perform etching window moulding：One layer of photoresist 10 is first coated, is then exposed and is removed photoresist, form N+ source electrodes Window is injected in area；

S2072：N-type ion implanting is carried out, and removes remaining photoresist 10；

S2073：High temperature propulsion is carried out, N+ source areas 5 are formed, the doping content of N+ source areas 5 is 1e19/cm³It is more than magnitude, It is preferred that 1e20/cm³, the junction depth of N+ source areas 5 is less than 1 μm, preferably 0.5 μm.

S208：So far p-well 6, N traps 1, P- bases 3, and the making of N+ source areas 5, subsequent technique and routine are completed Manufacture craft is consistent, as shown in Figure 23.The common process of this part can be with specific reference to such as：CN102945804B China Its related production of the prior art such as patent of invention.

In the present embodiment, the distance between two ditch groove centers of trench gate structure L is less than or equal to 2 μm, to guarantee Realize the N traps 1 of high concentration.The present embodiment forms N traps 1 using horizontal proliferation, and too wide groove pitch is difficult to ensure that less Laterally continuous N well structures are realized in the case of N trap junction depths.

In the present embodiment, the concentration of N traps 1 is more than normal concentration, and the doping content of the N traps 1 that common process makes is typically 1e15/cm³Magnitude, less than 1e16/cm³Magnitude.And the doping content of N traps 1 usually can exceed 1e16/cm in the present embodiment³ Magnitude, reaches 1e17/cm³Magnitude, even 1e18/cm³Magnitude.

In the present embodiment, the peak concentration of N traps 1 is located at the first depth a of groove, after being easy to power device using etching The manufacture craft of diffusing, doping.First depth a is equal to or slightly greater than the junction depth c of P- bases 3 and the junction depth of the monolateral diffusion of N traps 1 Sum, to guarantee the high-concentration dopant of N traps 1, and concentration is adjusted and does not interfere with P- bases 3.As shown in accompanying drawing 35, a For the first depth, c is the junction depth of P- bases 3, and d is the junction depth of N traps 1, and e is the monolateral diffusion junction depth of N traps 1.When first During the monolateral diffusion junction depth e of the junction depth c+N traps 1 of depth a=P- base 3, then P- bases 3 connect (be connected) with N traps 1. As the monolateral diffusion junction depth e of the junction depth c+N traps 1 of the first depth a ＞ P- bases 3, then P- bases 3 with N traps 1 from (phase Mutually isolation).

Embodiment 4：

When the trench gate structure of power device includes effective grid 20, and the two or more vacation for being arranged at the both sides of effective grid 20 During grid 30, positioned at the p-well 6 of the bottom of false grid 30 and the p-well 6 of effective grid 20 bottom adjacent with false grid 30 from or phase Even, positioned at the p-well 6 of the bottom of false grid 30 and the p-well 6 of another false grid 30 bottom adjacent with false grid 30 from or be connected. The p-well 6 of regular grid (effective grid) channel bottom is from (in break-over of device, offer electronics leads in the embodiment of the present invention 1 Road), and in the present embodiment, the p-well 6 of the channel bottom of false grid 30 is not limited, can from, connect or intersect.It is false Grid 30 can be two kinds of situations of floating or ground connection in electrical connection.Floating is that the polysilicon in false grid 30 is not drawn Process, surrounding is by gate oxide (SiO₂) surround.Ground connection then refers to that the polysilicon in false grid 30 is done into extraction is processed, and is led to Device surface is connected with the emitter metal electrode 8 of device.And the polysilicon effectively in grid 20 is the surface for leading to device, It is connected with the gate electrode of device.Any side of false grid 30 is all not provided with N+ source areas 5, therefore its any side is not also all sent out Emitter-base bandgap grading metal electrode 8.On technique is realized, the preparation method of false grid 30 is consistent with the preparation method of effective grid 20, its area It is not that effective grid 20 is led into the gate electrode of device in the extraction technique of grid, and by the floating of false grid 30 (being not brought up) Or lead to the emitter metal electrode 8 of device.

The effect of false grid 30 can be the size for reducing saturation current, and because the raceway groove overall width of device is reduced, then saturation current can To reduce, can be with the short-circuit capacity of adjusting means.Simultaneously as the addition of false grid 30, is provided with equivalent to the inside in device Field plate structure, the electric field that will be close to device surface is advanced into the inside of device, and the electric field concentration for solving the bottom of effective grid 20 is asked Topic, further improves the voltage endurance of device.

As shown in Figure 24, for the bottom of false grid 30 p-well 6 each other all from the case of, its manufacture craft can be by According to the preparation method in embodiment 2 and embodiment 3.

As shown in Figure 25, for the lower trench p-well 6 of false grid 30 and effective grid 20 lower trench p-well 6 in the case of of being connected, Then need to treat according to following two modes respectively.

As shown in Figure 26, if in a structure cell, the distance between two adjacent effective grids 20 are (i.e. adjacent The distance between two effective centers of grid 20) L1 is more than between effective grid 20 and other false grid 30 of arbitrary neighborhood During distance (the distance between other centers of Jia Shan 30 of i.e. effective center of grid 20 and arbitrary neighborhood) L2, i.e. during L1 ＞ L2, Still can be using the preparation method described in embodiment 2 and embodiment 3.By the diffusion time for controlling p-well 6, Ke Yishi The p-well 6 of existing vacation grid 30 bottom is connected, and ensure the p-well 6 of effective bottom of grid 20 from.As shown in Figure 27, when The distance between the effective grid 20 of adjacent two L1 more than the distance between effective grid 20 and adjacent false grid 30 L2, and During the distance between the false grid 30 of adjacent to each other two (the distance between two centers of Jia Shan 30 i.e. adjacent to each other) L3, i.e., During L1 ＞ L2=L3, remaining on can be using the preparation method described in embodiment 2 and embodiment 3.

If within a cellular, L1 (the distance between effective grid 20 of adjacent two)=L2 (effective grid 20 and phase The distance between adjacent vacation grid 30)=L3 (the distance between false grid 30 of adjacent to each other two), then can not adopt the He of embodiment 2 Preparation method described in embodiment 3, and the preparation method that following embodiments 5 and embodiment 6 must be adopted.First, carry out The technique for making p-well 6, then does again other techniques, and the p-well 6 of the otherwise left and right sides will link together, and have at two Just do not isolate between effect grid 20, so as to electronics path can not be formed.

Embodiment 5：

A kind of specific embodiment that the preparation method of power device described in example 4 is performed as described above, when the distance between effective grid is equal to When the distance between false grid and effective grid adjacent with false grid, method is comprised the following steps：

S111：Carry out p-well 6 on the basis of N- substrates 2 to make (diffusion)；

S101：On the basis of previous step, carry out N traps 1 and make；

S102：Carry out P- bases 3 on N traps 1 to make；

S103：On the basis of previous step, groove making is carried out；

S105：Carry out gate oxide 9 in groove to make and polysilicon filling；

S106：Carry out N+ source areas 5 between two grooves to make；

S107：Complete subsequent technique.

Step S111 further includes procedure below：

S1111：By high-temperature oxydation, one layer of sacrificial oxide layer 11 is made to the front of device on the basis of N- substrates 2, it is sacrificial The thickness of domestic animal oxide layer 11 is 100A～600A, preferred 300A；

S1112：One layer of photoresist 10 is coated on sacrificial oxide layer 11, is then exposed, and removal devices effective district (unit Born of the same parents area) above photoresist 10, formed p-well injection window；

S1113：Carry out p-type ion implanting, and the photoresist 10 of removal devices surface residual；

S1114：High temperature propulsion (diffusion technique) is carried out, p-well 6 is ultimately formed, the doping content of p-well 6 is in 1e16/cm³Magnitude Hereinafter, preferred 1e15/cm³, the junction depth of p-well 6 is 3 μm～8 μm, preferably 8 μm.

Wherein, in the present embodiment step S101, S102, S103, S105, S106 and S107 are corresponding with embodiment 2 Step S101, S102, S103, S105, S106 and S107 adopt identical process.

Embodiment 6：

Another kind is performed as described above the specific embodiment of the preparation method of power device described in example 4, when the distance between effective grid etc. When the distance between false grid and effective grid adjacent with false grid, the method is comprised the following steps：

S211：Carry out p-well 6 on the basis of N- substrates 2 to make；

S201：On the basis of previous step, carry out P- bases 3 and make；

S202：On the basis of previous step, etching groove is carried out；

S203：N trap injections are carried out by groove, N traps 1 are formed；

S204：Proceed etching groove until target depth；

S206：Carry out gate oxide 9 in groove to make and polysilicon filling；

S207：Carry out N+ source areas 5 between two grooves to make；

S208：Complete subsequent technique.

Step S211 further includes procedure below：

S2111：By high-temperature oxydation, one layer of sacrificial oxide layer 11 is made to the front of device on the basis of N- substrates 2, it is sacrificial The thickness of domestic animal oxide layer 11 is 100A～600A, preferred 300A；

S2112：One layer of photoresist 10 is coated on sacrificial oxide layer 11, is then exposed, and removal devices effective district top Photoresist 10, formed p-well injection window；

S2113：Carry out p-type ion implanting, and the photoresist 10 of removal devices surface residual；

S2114：High temperature propulsion is carried out, p-well 6 is ultimately formed, the doping content of p-well 6 is in 1e16/cm³Below magnitude, preferably 1e16/cm³, the junction depth of p-well 6 is 3 μm～8 μm, preferably 8 μm.

Wherein, in the present embodiment in step S201, S202, S203, S204, S206, S207 and S208 and embodiment 3 Corresponding step S201, S202, S203, S204, S206, S207 and S208 adopt identical process.

As shown in accompanying drawing 28,29 and 30, the diffusion junction depth of p-well 6 is reflected to device (device) on-state voltage drop and pressure Affect.The structure of p-well 6 can reduce the electric-field intensity of power device channel bottom, and the distance between p-well 6 and N traps 1 subtract Little (1x junction depths, 2x junction depths, 4x junction depths), contributes to reducing electric-field intensity, i.e.,：The diffusion junction depth of p-well 6 increases, and more has Beneficial to the electric-field intensity for reducing device trenches bottom, as shown in Figure 28 impact of the junction depth to electric-field intensity is spread for p-well 6, Wherein, C3：Y=5um, Vce=1800V.

The membership that adds of p-well 6 increases the on-state voltage drop of device.(p-well 6 and N when the junction depth of p-well 6 less (1x junction depths) Trap 1 from), its pressure drop is little with without p-well 6 phase difference.As the junction depth of p-well 6 is increased up (the 2x knots that just connect It is deep) when, the impact to device on-state voltage drop increases, i.e., on-state voltage drop increases.When p-well 6 intersects (4x junction depths) with N traps 1 When, the on-state voltage drop of device increases larger.That is the diffusion junction depth of p-well 6 is bigger, and the on-state voltage drop of device is bigger, such as accompanying drawing 29 With shown in 30.Therefore can draw, the diffusion junction depth of p-well 6 is bigger, and the pressure performance of device is better, but on-state voltage drop is bigger.

As shown in accompanying drawing 31 to accompanying drawing 34, the change in concentration of p-well 6 is reflected to device on-state voltage drop and pressure impact.Its In, such as accompanying drawing 31 and accompanying drawing 32 show the doping content impact pressure to device of p-well 6, and the concentration of p-well 6 increases meeting The slight on-state voltage drop for increasing device, but increasing degree is little.Doping as accompanying drawing 31 and accompanying drawing 32 show p-well 6 is dense Impact of the degree to device on-state voltage drop, the concentration of p-well 6 increases the impact very small (be slightly increased) pressure to device.Therefore can To draw, the change in concentration (within the specific limits) of p-well 6 is little on device on-state voltage drop and pressure impact, i.e. p-well 6 Doping content variable range it is big.

By the technical scheme for implementing the power device that the specific embodiment of the invention is described and preparation method thereof, following skill can be produced Art effect：

(1) power device of specific embodiment of the invention description and preparation method thereof improves high concentration N trap trench-gate power devices Pressure performance, optimize the on-state voltage drop (power consumption) of IGBT and pressure contradictory relation；

(2) the p-well process costs of power device of specific embodiment of the invention description and preparation method thereof inject work than energetic ion Skill low cost；

(3) the p-well diffusion technique of power device of specific embodiment of the invention description and preparation method thereof does not affect N traps, P- The concentration and junction depth of base and N+ source areas, reduces process complexity and difficulty；

(4) power device of specific embodiment of the invention description and preparation method thereof carries out autoregistration injection using groove, without the need for new Add lustre to mechanical；

(5) power device of specific embodiment of the invention description and preparation method thereof p-well concentration adjusts easy, and adjusts window model Enclose big.

Each embodiment is described by the way of progressive in this specification, and what each embodiment was stressed is and other embodiment Difference, between each embodiment identical similar portion mutually referring to.

The above, is only presently preferred embodiments of the present invention, and any pro forma restriction is not made to the present invention.Although this Invention is disclosed as above with preferred embodiment, but is not limited to the present invention.Any those of ordinary skill in the art, In the case of Spirit Essence and technical scheme without departing from the present invention, all using the methods and techniques content of the disclosure above to this Bright technical scheme makes many possible variations and modification, or the Equivalent embodiments for being revised as equivalent variations.Therefore, it is every not take off From the content of technical solution of the present invention, according to the technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent Replacement, equivalence changes and modification, still fall within the scope of technical solution of the present invention protection.

Claims (26)

1. a kind of power device, including：N traps, N- substrates, P- bases, polysilicon gate, N+ source areas, P+ ohmic contact regions, Emitter metal electrode and gate oxide, the power device adopts trench gate structure, it is characterised in that the power device is also Including p-well, the N+ source areas, P- bases, N traps, p-well are arranged in order from top to bottom, and the p-well surrounds the groove The channel bottom of grid structure.

2. power device according to claim 1, it is characterised in that：The dopant concentration peak of the p-well is located at the ditch The bottom of groove.

3. power device according to claim 2, it is characterised in that：The p-well passes through when the power device is turned off The carrier for accelerating the N traps exhausts the electric-field intensity for reducing the channel bottom.

4. the power device according to Claims 2 or 3, it is characterised in that：The doping content of the p-well is higher than the N The doping content of trap.

5. power device according to claim 4, it is characterised in that：The doping content curve of the p-well and the N traps Connect.

6. the power device according to any one of claim 1,2,3 or 5, it is characterised in that：When the power device Using effective grid trench gate structure when, positioned at effective gate bottom two p-wells from.

7. the power device according to any one of claim 1,2,3 or 5, it is characterised in that：When the power device Trench gate structure include effective grid, and be arranged at effective grid both sides two or more vacation grid when, have positioned at described Two p-wells of effect gate bottom from, positioned at described false grid adjacent to each other and effective gate bottom p-well from or be connected, Positioned at two false grid bottoms adjacent to each other p-well from or be connected.

8. a kind of power device preparation method as any one of claim 1 to 6, it is characterised in that including following step Suddenly：

S101：N trap making is carried out on the basis of N- substrates；

S102：The making of P- bases is carried out on the N traps；

S103：On the basis of previous step, groove making is carried out；

S104：P-well injection is carried out by the groove, p-well is formed；

S105：Gate oxide making and polysilicon filling are carried out in the groove；

S106：N+ source area making is carried out between two grooves；

S107：Complete subsequent technique.

9. a kind of power device preparation method as claimed in claim 7, it is characterised in that when between effective grid away from During from equal to the distance between described false grid adjacent to each other and effective grid, the method comprising the steps of：

S111：P-well making is carried out on the basis of N- substrates；

S101：On the basis of previous step, N trap making is carried out；

S102：The making of P- bases is carried out on the N traps；

S103：On the basis of previous step, groove making is carried out；

S105：Gate oxide making and polysilicon filling are carried out in the groove；

S106：N+ source area making is carried out between two grooves；

S107：Complete subsequent technique.

10. power device preparation method according to claim 8, it is characterised in that step S101 is further included：

S1011：By high-temperature oxydation, one layer of sacrificial oxide layer is made to the front of device on the basis of N- substrates, it is described sacrificial The thickness of domestic animal oxide layer is 100A～600A；

S1012：One layer of photoresist is coated on the sacrificial oxide layer, is then exposed, and above removal devices effective district Photoresist, forms N traps injection window；

S1013：Carry out N-type ion implanting, and the photoresist of removal devices surface residual；

S1014：High temperature propulsion is carried out, the N traps are ultimately formed, the doping content of the N traps is in 1e16/cm³Below magnitude, The junction depth of the N traps is 3 μm～8 μm.

11. power device preparation methods according to claim 9, it is characterised in that step S111 is further included：

S1111：By high-temperature oxydation, one layer of sacrificial oxide layer is made to the front of device on the basis of N- substrates, it is described sacrificial The thickness of domestic animal oxide layer is 100A～600A；

S1112：One layer of photoresist is coated on the sacrificial oxide layer, is then exposed, and above removal devices effective district Photoresist, forms p-well injection window；

S1113：Carry out p-type ion implanting, and the photoresist of removal devices surface residual；

S1114：High temperature propulsion is carried out, the p-well is ultimately formed, the doping content of the p-well is in 1e16/cm³Below magnitude, The junction depth of the p-well is 3 μm～8 μm.

The 12. power device preparation methods according to claim 10 or 11, it is characterised in that step S102 enters one Step includes：

S1021：By high-temperature oxydation, one layer of sacrificial oxide layer is made on the N traps, the thickness of the sacrificial oxide layer is 100A～600A；

S1022：One layer of photoresist is coated on the sacrificial oxide layer, is then exposed, and above removal devices effective district Photoresist, forms P- bases injection window；

S1023：Carry out p-type ion implanting, and the photoresist of removal devices surface residual, and the photoetching of removal devices surface residual Glue；

S1024：High temperature propulsion is carried out, the P- bases are ultimately formed, the doping content of the P- bases is in 1e17/cm³Magnitude More than, the junction depth of the P- bases is 3 μm～8 μm.

13. power device preparation methods according to claim 12, it is characterised in that step S103 is further wrapped Include：

S1031：Perform etching window moulding：One layer of photoresist is first coated, is then exposed and is removed photoresist, form etching groove window Mouthful；

S1032：Etching groove is carried out, until target depth, junction depth of the target depth more than or equal to the N traps.

The 14. power device preparation methods according to claim 8 or 10, it is characterised in that step S104 enters one Step includes：

S1041：P-type ion implanting is carried out to device effective district；

S1042：High temperature propulsion is carried out, p-well is formed, the doping content of the p-well is higher than the doping content of the N traps.

15. power device preparation methods according to claim 13, it is characterised in that step S105 is further wrapped Include：

S1051：High-temperature oxydation being carried out, makes trench wall grow one layer of gate oxide, the thickness of the gate oxide is 0.1 μm～ 0.5μm；

S1052：Polysilicon deposition is carried out, the polysilicon fills the inside of groove；

S1053：N-type doping is carried out to the polysilicon, doping content is 1e19/cm³It is more than magnitude；

Step S1053 is further included：

N-type ion implanting is carried out first, and doping, the surface shape of the polysilicon after propulsion are then realized by high temperature propulsion Into layer of oxide layer.

The 16. power device preparation methods according to claim 13 or 15, it is characterised in that step S106 enters one Step includes：

S1061：Perform etching window moulding：One layer of photoresist is first coated, is then exposed and is removed photoresist, form N+ source areas Injection window；

S1062：N-type ion implanting is carried out, and removes remaining photoresist；

S1063：High temperature propulsion is carried out, N+ source areas are formed, the doping content of the N+ source areas is 1e19/cm³It is more than magnitude, The junction depth of the N+ source areas is less than 1 μm.

17. a kind of power device preparation methods as any one of claim 1 to 6, it is characterised in that including following Step：

S201：The making of P- bases is carried out on the basis of N- substrates；

S202：On the basis of previous step, etching groove is carried out；

S203：N trap injections are carried out by the groove, N traps are formed；

S204：Proceed etching groove until target depth；

S205：P-well injection is carried out by the groove, p-well is formed；

S206：Gate oxide making and polysilicon filling are carried out in the groove；

S207：N+ source area making is carried out between two grooves；

S208：Complete subsequent technique.

18. a kind of power device preparation methods as claimed in claim 7, it is characterised in that when between effective grid When distance is equal to the distance between two described false grid adjacent to each other and effective grid, the method comprising the steps of：

S211：P-well making is carried out on the basis of N- substrates；

S201：On the basis of previous step, the making of P- bases is carried out；

S202：On the basis of previous step, etching groove is carried out；

S203：N trap injections are carried out by the groove, N traps are formed；

S204：Proceed etching groove until target depth；

S206：Gate oxide making and polysilicon filling are carried out in the groove；

S207：N+ source area making is carried out between two grooves；

S208：Complete subsequent technique.

19. power device preparation methods according to claim 17, it is characterised in that step S201 is further wrapped Include：

S2011：By high-temperature oxydation, one layer of sacrificial oxide layer is made to the front of device on the basis of N- substrates, it is described sacrificial The thickness of domestic animal oxide layer is 100A～600A；

S2012：One layer of photoresist is coated on the sacrificial oxide layer, is then exposed, and above removal devices effective district Photoresist, forms P- bases injection window；

S2013：Carry out p-type ion implanting, and the photoresist of removal devices surface residual；

S2014：High temperature propulsion is carried out, the P- bases are ultimately formed, the doping content of the P- bases is in 1e17/cm³Magnitude More than, the junction depth of the P- bases is 3 μm～8 μm.

20. power device preparation methods according to claim 18, it is characterised in that step S211 is further wrapped Include：

S2111：By high-temperature oxydation, one layer of sacrificial oxide layer is made to the front of device on the basis of N- substrates, it is described sacrificial The thickness of domestic animal oxide layer is 100A～600A；

S2112：One layer of photoresist is coated on the sacrificial oxide layer, is then exposed, and above removal devices effective district Photoresist, forms p-well injection window；

S2113：Carry out p-type ion implanting, and the photoresist of removal devices surface residual；

S2114：High temperature propulsion is carried out, the p-well is ultimately formed, the doping content of the p-well is in 1e16/cm³Below magnitude, The junction depth of the p-well is 3 μm～8 μm.

The 21. power device preparation methods according to claim 19 or 20, it is characterised in that step S202 enters one Step includes：

S2021：Perform etching window moulding：One layer of photoresist is first coated, is then exposed and is removed photoresist, form etching groove window Mouthful；

S2022：Etching groove is carried out, until the first depth, junction depth of first depth more than or equal to the P- bases.

22. power device preparation methods according to claim 21, it is characterised in that step S203 is further wrapped Include：

S2031：N-type ion implanting is carried out to whole device；

S2032：High temperature propulsion is carried out, N traps are formed, the doping content of the N traps is in 1e14/cm³～1e17/cm³Magnitude model In enclosing, the junction depth of the N traps is less than 3 μm.

23. power device preparation methods according to claim 22, it is characterised in that step S204 is further wrapped Include：

S2041：Perform etching window moulding：One layer of photoresist is first coated, is then exposed and is removed photoresist, form etching groove window Mouthful；

S2042：Carry out etching groove, until the second depth, second depth for groove projected depth, the design depth of groove Degree is between 4 μm～8 μm.

The 24. power device preparation methods according to claim 17 or 19, it is characterised in that step S205 enters one Step includes：

P-type ion implanting is carried out to device effective district, the doping content of the p-well is less than the doping content of the N+ source areas.

The 25. power device preparation methods according to claim 22 or 23, it is characterised in that step S206 enters one Step includes：

S2061：High-temperature oxydation being carried out, makes trench wall grow one layer of gate oxide, the thickness of the gate oxide is 0.1 μm～ 0.5μm；

S2062：Polysilicon deposition is carried out, the polysilicon fills the inside of groove；

S2063：N-type doping is carried out to the polysilicon, doping content is 1e19/cm³It is more than magnitude；

Step S2063 is further included：

N-type ion implanting is carried out first, and doping, the surface shape of the polysilicon after propulsion are then realized by high temperature propulsion Into layer of oxide layer.

26. power device preparation methods according to claim 25, it is characterised in that step S207 is further wrapped Include：

S2071：Perform etching window moulding：One layer of photoresist is first coated, is then exposed and is removed photoresist, form N+ source areas Injection window；

S2072：N-type ion implanting is carried out, and removes remaining photoresist；

S2073：High temperature propulsion is carried out, N+ source areas are formed, the doping content of the N+ source areas is 1e19/cm³It is more than magnitude, The junction depth of the N+ source areas is less than 1 μm.