CN109346472A - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
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- CN109346472A CN109346472A CN201810948486.XA CN201810948486A CN109346472A CN 109346472 A CN109346472 A CN 109346472A CN 201810948486 A CN201810948486 A CN 201810948486A CN 109346472 A CN109346472 A CN 109346472A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000012535 impurity Substances 0.000 claims abstract description 65
- 239000000463 material Substances 0.000 claims description 56
- 238000003860 storage Methods 0.000 claims description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 20
- 238000009825 accumulation Methods 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 300
- 239000000243 solution Substances 0.000 description 38
- 239000011799 hole material Substances 0.000 description 18
- 238000005530 etching Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 230000000994 depressogenic effect Effects 0.000 description 5
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000037237 body shape Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000012782 phase change material Substances 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a kind of semiconductor devices, the semiconductor devices includes: pipe gate；Wordline, the wordline are layered in pipe gate；First channel layer, first channel layer are configured to break-through wordline；And second channel layer, second channel layer are formed in pipe gate to connect the first channel layer, and have the impurity concentration higher than the first channel layer.
Description
The application be on 03 18th, 2013 to State Intellectual Property Office of the People's Republic of China submit application No. is
201310085518.5, the division Shen of the Chinese invention patent application of entitled " semiconductor devices and its manufacturing method "
Please.
Technical field
Present invention is generally directed to a kind of semiconductor devices and its manufacturing methods, more specifically, are related to a kind of three-dimensional
(3D) nonvolatile semiconductor memory member and its manufacturing method.
Background technique
Nonvolatile semiconductor memory member is one kind even if the storage that can also retain the data wherein stored in dump
Device.Recently, with memory cell with single layer formed two dimension (2D) memory device on substrate integrated level improvement
It is reached capacity, proposes three-dimensional (3D) nonvolatile semiconductor memory member of memory cell stacking on substrate.
Storage is laminated and being arranged vertically storage string on substrate or arranging storage string in a manner of " u "-shaped on substrate
Device unit, to manufacture 3D nonvolatile semiconductor memory member, wherein each storage string includes the drain electrode selection crystal being all connected in series
Pipe, drain side memory cell, tunnel transistor, source side memory unit and drain selection transistor.
Drain side memory cell is connect by tunnel transistor with source side memory unit.However, due to pipeline crystal
Pipe is located at below the drain side memory cell and source side memory unit of stacking, therefore it is difficult to manufacture tunnel transistor.Especially
Its, during manufacturing process, the channel layer of tunnel transistor may be cut off or threshold voltage may be subjected to it is incorrect
Control, thus reduce memory device operating reliability.
Summary of the invention
The present invention relates to a kind of semiconductor devices and its manufacturing method with improved operating reliability.
One aspect of the present invention provides a kind of semiconductor devices, and the semiconductor devices includes: pipe gate；Wordline,
The wordline is layered in pipe gate；First channel layer, first channel layer are configured to break-through wordline；And second channel
Layer, second channel layer are formed in pipe gate to connect the first channel layer, and are had more higher than the first channel layer
Impurity concentration.
Another aspect of the present invention provides a kind of semiconductor devices, and the semiconductor devices includes: source side storage
Device unit, the source side memory unit is along the first source side channel layer stackup；Drain side memory cell, the drain electrode
Side memory cell is along the first drain side channel layer stackup；And conductive layer, the conductive layer are configured to the first source electrode
Lateral sulcus channel layer is connect with the first drain side channel layer.
Another aspect provides a kind of methods of manufacturing semiconductor devices, the described method comprises the following steps:
Groove is formed by the first conductive layer of etching；Sacrificial layer is formed in the trench；On the first conductive layer for being formed with sacrificial layer
Alternately form first material layer and second material layer；By etching first material layer and second material layer formed channel hole with
Groove connection；Remove the sacrificial layer exposed via the bottom surface in channel hole；By forming channel layer in channel hole and groove,
The first channel layer is formed in channel hole, and forms the second channel layer in the trench；Pass through first between etching channel hole
Material layer and second material layer form gap；And impurity is injected into the second channel layer via gap.
Detailed description of the invention
Describe various embodiments of the present invention in detail by referring to accompanying drawing, above and other feature of the invention and excellent
Point will become more obviously for those skilled in the art, in which:
Figure 1A to Fig. 1 D is the sectional view of the semiconductor devices of different embodiment according to the subject invention；
Fig. 2A and Fig. 2 B is the part for illustrating the cell array of semiconductor devices of different embodiment according to the subject invention
Circuit diagram；
Fig. 3 A to Fig. 3 D is the sectional view of the method according to an embodiment of the invention being used for producing the semiconductor devices；
Fig. 4 is the block diagram of storage system according to another embodiment of the invention；And
Fig. 5 is the block diagram of computing system according to another embodiment of the invention.
Specific embodiment
Hereinafter, various embodiments of the present invention are more fully described with reference to the accompanying drawings.In the accompanying drawings, for clarity
For the sake of, the interval between the thickness and layer and region of layer and region has been carried out exaggerating processing.In the following description, it is known that
If function or structure make the present invention fuzzy due to unnecessary details, without detailed description.In the accompanying drawings, Mei Dangxiang
When same element occurs again in subsequent attached drawing, indicated by identical appended drawing reference.
Figure 1A to Fig. 1 D is the sectional view of the semiconductor devices of different embodiment according to the subject invention.
Referring to Figure 1A, semiconductor devices according to an embodiment of the invention includes: pipe gate 11；Wordline 12, it is described
Wordline 12 is layered in pipe gate 11；First channel layer 14, first channel layer 14 are formed break-through wordline 12；And the
Two channel layers 15, second channel layer 15 are formed in pipe gate 11 to connect with the first channel layer 14, and have than
The high impurity concentration of first channel layer 14.
First channel layer 14 may be used as the channel layer of the memory cell of stacking, and each first channel layer 14 can be with
It is formed by undoped polysilicon layer.
Second channel layer 15 is formed to connect the first adjacent channel layer 14.For example, the second channel layer 15 will all exist
The lower part connection of the first drain side channel layer and the first source side channel layer adjacent to each other in first channel layer 14.
Second channel layer 15 may include the first area 15A contacted with the first channel layer and be arranged between the first area 15A
The second area 15B, and the second channel layer 15 can be formed by the polysilicon layer adulterated.Second channel layer 15A includes than first
The impurity of impurity higher concentration in channel layer 14, and the second area 15B may include higher than the impurity in the first area 15A
The impurity of concentration.For example, the first area 15A can not include impurity, and the second area 15B may include N-type or p type impurity.As
Another example, the first area 15A may include the N-type or p type impurity of low concentration, and the second area 15B may include the N of high concentration
Type or p type impurity.
First channel layer 14 and the second channel layer 15 each can have tube shape, and be collectively form open center
Region.The open center region of first channel layer 14 and the second channel layer 15 can be filled with insulating layer 18.
Pipe gate 11 is formed to surround the second channel layer 15.For example, pipe gate 11 can be formed to surround the second ditch
All or some in the upper surface of channel layer 15, side surface and lower surface.Pipe gate 11 can be by conductive layer such as polysilicon
Layer is formed.
Semiconductor devices can also include the first accumulation layer 16 for surrounding the first channel layer 14 and the second channel layer 15.First
Accumulation layer 16 may include that the first channel layer 14 and the second channel layer 15 and tunnel insulation layer, the charge among wordline 12 is arranged in
All or some in storage layer and electric charge barrier layer.Electric charge storage layer may include for store the floating gate of charge (for example,
Floating gate), at least one of the trap layer (for example, nitride layer) for capturing charge and nano dot.Semiconductor devices can
Electric charge storage layer is replaced to include phase-change material layers.
Semiconductor devices can also include being arranged between the first accumulation layer 16 and wordline 12 and surrounding the upper of wordline 12
Second accumulation layer 17 on surface and lower surface.Second accumulation layer 17 may include tunnel insulation layer, electric charge storage layer and charge
All or some in barrier layer.For example, the second accumulation layer 17 may include by stacking oxide skin(coating) and high-k dielectric material
Layer and obtain electric charge barrier layer.
Semiconductor devices can also include the first gap S1, the first gap S1 break-through wordline 12 and be alternately laminated
Interlayer insulating film 13 between wordline 12.First gap S1 is arranged between channel hole, and the of the second channel layer 15
On two area 15B.First gap S1 can be formed into so that exposing the depth on the surface of pipe gate 11 via the first gap S1
Degree, or make the upper surface of pipe gate 11 by the depth of over etching (over-etch).Then, is filled with insulating layer 19
One gap S1.
Referring to Figure 1B, semiconductor devices according to another embodiment of the invention includes the first channel layer 14 and the second ditch
Channel layer 15, first channel layer 14 and the second channel layer 15 are each using cylinder body shape mode --- whole region includes not open
The central area put --- to be formed.The structure of the other structures of the semiconductor devices of Figure 1B and semiconductor devices shown in figure 1A
It is substantially similar.
Referring to Fig. 1 C, semiconductor devices according to another embodiment of the invention includes: pipe gate 11, the pipe gate
11 surround the side surface and lower surface of the second channel layer 15.Difference feature compared with the embodiment described in Figure 1A is,
It surrounds in the pipe gate 11 of the upper surface of the second channel layer 15 and is formed with illusory pipe gate 20.
In fig. 1 c, pipe gate 11 can be formed by the polysilicon layer of conductive layer such as doping, and illusory pipe gate 20
It can be formed by for example undoped polysilicon layer of non-conductive layer.Since illusory pipe gate 20 is formed by non-conductive layer, so only
11 essence of pipe gate plays grid.Illusory pipe gate 20 can be used as etching barrier layer during the etching of the first gap S1.
Wordline 12 and interlayer insulating film 13 are alternately laminated in illusory pipe gate.Although Fig. 1 C shows interlayer insulating film 13
It is sequentially and alternately layered in pipe gate 11 with wordline 12, but wordline 12 and interlayer insulating film 13 can be sequentially and alternately
It is layered in illusory pipe gate 20.It, can be in illusory pipe when one in wordline 12 is directly layered in illusory pipe gate 20
Second accumulation layer 17 is set between gate 20 and wordline 12 to play interlayer insulating film.
The other structures of the semiconductor devices of Fig. 1 C and the structure of semiconductor devices shown in figure 1A are substantially similar.
Referring to Fig. 1 D, in semiconductor devices according to another embodiment of the invention, the of the second channel layer 15
Included impurity concentration all having the same in one area 15A and the second area 15B.
For example, the first area 15A and the second area 15B each include the N-type or p type impurity of low concentration.In this case, it manages
The threshold voltage of road transistor reduces, to improve the variation for the threshold voltage that may occur during program/erase operation.
As another example, the first area 15A and the second area 15B each may include the impurity of high concentration.In this feelings
Under condition, the second channel layer 15 shows conductive properties, thus keeps adjacent the first drain side channel layer 14 and the first source side
Connectivity between 14 pairs of channel layer.In other words, tunnel transistor is held on.
When the second channel layer 15 shows conductive properties, the first drain side channel layer 14 and the first source side channel layer 14
Holding is connected, and then pipe gate 11 can be replaced with insulating layer.
As noted previously, as the impurity in the second channel layer 15 can be than the impurity concentration in the first channel layer 14 more
Height, so the threshold voltage of tunnel transistor can reduce, to improve the threshold value that may occur during program/erase operation
The variation of voltage.In addition, the second area 15B of the second channel layer 15 is configured to have conduction due to high concentration impurities therein
Attribute, so that even if some parts when the second channel layer 15 are assembled to prevent the adequate relief during the manufacture of semiconductor devices
When at the second channel layer 15, electric current can also be easily through the second area 15B of the second channel layer 15.
Fig. 2A and Fig. 2 B is the part for illustrating the cell array of semiconductor devices of different embodiment according to the subject invention
Circuit diagram.
A and Fig. 2 B referring to fig. 2, the semiconductor devices of embodiment according to the present invention include being arranged using U-shape mode
Storage string.Each storage string includes: at least one drain electrode the selection transistor DST, drain side memory list being all connected in series
First D_MC, tunnel transistor P_Tr and D_PTr (or tunnel transistor S_PTr), source side memory cell S _ MC and at least
One drain selection transistor SST.
Drain side memory cell D_MC is --- along via second ditch as shown in one into 1D of Figure 1A
The first channel layer that channel layer 15 connects is to the first drain side channel layer 14 --- the memory cell of stacking among 14.Source side
Memory cell S_MC is the memory cell along other first source side channel layer 14 stackings.
As shown in Figure 2 A, a storage string may include multiple tunnel transistor D_PTr and S_PTr.
Above by reference to a described semiconductor devices in Figure 1A to Fig. 1 C, in the second channel layer 15
Second area 15B in impurity can be higher than the impurity concentration in the first area 15A.In particular, when the second area 15B includes highly concentrated
When spending impurity, the second area 15B has conductive properties.In addition, the first area 15A of the second channel layer 15 include low concentration impurity or
Do not include impurity, and there are semiconductor properties.
Thus, the first area 15A connecting with the first drain side channel layer 14 includes drain side tunnel transistor D_PTr, and
The first area 15A connecting with the first source side channel layer 14 includes source side tunnel transistor S_PTr.Drain side tunnel transistor
First area's channel layer of D_PTr is connected with first area's channel layer of source side tunnel transistor S_PTr via second area's conductive layer.
In addition, drain side tunnel transistor D_PTr and source side tunnel transistor S_PTr shares pipe gate shown in Figure 1A to Fig. 1 D
11 are used as gate electrode, and are controlled simultaneously.
As shown in Figure 2 B, a storage string may include the tunnel transistor P_Tr of a conducting.
In the case where the semiconductor devices described above by reference to Fig. 1 D, the first area 15A of the second channel layer 15 and second
Area 15B may include the impurity of high concentration.In this case, entire second channel layer 15 has conductive properties.Thus, pipeline
Transistor P_Tr is held on.
Fig. 3 A to Fig. 3 D is the sectional view of the method for manufacturing semiconductor devices according to another embodiment of the invention.
Referring to Fig. 3 A, the first conductive layer 31 for being used for pipe gate is formed, etches the first conductive layer 31 then to form groove
T.Then, groove T is substantially filled with sacrificial layer 32.For example, sacrificial layer 32 may include in nitride layer and titanium nitride layer
At least one.
Then, it is formed on first conductive layer 31 with the groove T filled with sacrificial layer 32 and is used for the second of pipe gate
Conductive layer 33.Alternatively, the non-conductive layer for illusory pipe gate can be formed to be substituted for the second of pipe gate the conduction
Layer 33.For example, the non-conductive layer for illusory pipe gate can be formed by undoped polysilicon layer.
First material layer 34 and second material layer 35 are alternately formed on the second conductive layer 33 for pipe gate.It is formed
First material layer 34, to form wordline or for the conductive layer of selection line.Second material layer 35 is formed the conduction that will be laminated
Layer is isolated from each other.For example, being initially formed second material layer 35 on the second conductive layer 33 for pipe gate, and in the second material
Second material layer 34 is formed on the bed of material 35.As another example, first is formed in the non-conductive layer for illusory pipe gate
Material layer 34, and second material layer 35 is formed in first material layer 34.
First material layer 34 and second material layer 35 are formed by the material relative to each other with high etch selectivity.Example
Such as, first material layer 34 can each be formed by conductive layer such as polysilicon layer, and second material layer 35 each can be by insulating
Layer such as oxide skin(coating) is formed.As another example, first material layer 34 each can be by the polycrystalline of conductive layer such as doping
Silicon layer or the amorphous silicon layer of doping are formed, and second material layer 35 each can by for example undoped polysilicon layer of sacrificial layer or
Undoped amorphous silicon layer is formed.As another example, first material layer 34 each can be by sacrificial layer such as nitride layer
It is formed, and second material layer 35 can each be formed by insulation layers such as oxide skin(coating).
Then, first material layer 34 and second material layer 35 are etched to form the channel hole H connecting with groove T.For example, shape
At channel hole H, so that each groove T is connect with a pair of channel hole H.
Referring to Fig. 3 B, the sacrificial layer 32 exposed via the bottom surface of channel hole H is removed.Then, T and channel along groove
The inner surface of hole H forms the first accumulation layer 36.For example, the first accumulation layer 36 includes electric charge storage layer, tunnel insulation layer and can
The electric charge barrier layer of selection.
Channel layer 37 is formed in the first accumulation layer 36.Channel layer 37 can be formed by polysilicon layer etc..It is formed in ditch
The part of channel layer 37 in the H of road hole is used as the first channel layer 37A of selection transistor or memory cell, and is formed in ditch
The part of channel layer 37 in slot T is used as the second channel layer 37B of tunnel transistor.
Alternatively, channel layer 37 can be formed using the open tube shape mode in central area, or using whole
The central area in region nonopen cylinder body shape mode forms channel layer 37.The central area of the opening of channel layer 37 can be with
It is filled with insulating layer 38.
First material layer 34 and second material layer 35 are etched to form the first gap S1.First gap S1 is formed shape
The gate electrode of source side memory unit and drain side memory cell in Cheng Yi storage string is isolated from each other.Thus, the
One gap S1 is located between the H of channel hole, and specifically, on the second channel layer 37B.First gap S1 be formed into so that
Via the first gap S1, the depth on the surface of the second conductive layer 33 for pipe gate is exposed.In this case, available
Over etching technique etches the first gap S1, so that a part of the second conductive layer 33 is etched.
Referring to Fig. 3 C, as shown by arrows, via the first gap S1 implanted dopant.For example, impurity can be N-type or p-type is miscellaneous
Matter.Plasma doping or ion implantation technology be can use to execute the injection of impurity.In this case, impurity is injected
Into the second channel layer 37B positioned at the bottom surface of the first gap S1, and can be controlled according to the condition of impurity injection technology
The depth and concentration of impurity injection processed.
For example, impurity is injected into the second area 37BB of the second channel layer 37B using ion implantation technology.It can use
Impurity is injected into the second area 37BB of the second channel layer 37B by high concentration or low concentration.In this case, the second channel layer
37B includes the first area 37BA formed by undoped polysilicon layer, and by comprising high concentration impurities or low concentration impurity
The second area 37BB that polysilicon layer is formed.
As another example, impurity is injected into the second area 37BB of the second channel layer 37B using ion implantation technology
In, and the impurity diffusion in the second area 37BB will be injected into the first area 37BA using heat treatment process.In such case
Under, the second channel layer 37B includes the first area 37BA containing low concentration impurity and the second area 37BB containing high concentration impurities.Separately
Outside, the second channel layer 37B includes the first area 37BA and the second area 37BB, and the firstth area 37BA and the second area 37BB each include
Low concentration impurity or high concentration impurities.
Referring to Fig. 3 D, first material layer 34 and second material layer 35 are etched to form the second gap S2.By the second gap S2
Form the depth that first material layer 34 is fully exposed via the second gap S2.
Then, the first material layer 34 exposed via the first gap S1 and the second gap S2 is removed, to form each quilt
The depressed area that conductive layer 41 is filled.The conductive layer 41 of stacking at least one of uppermost conductive layer 41 may be used as selecting
Line, and other conductive layers 41 may be used as wordline.In this case, before filling each depressed area with conductive layer 41,
The second accumulation layer 40 can also be formed in depressed area.Second accumulation layer 40 each may include electric charge barrier layer.
The first gap S1 is filled with insulating layer 39, and the second gap S2 is filled with insulating layer 42.Although using independent
Technique form the first gap S1 and the second gap S2, but they can be formed simultaneously.Second gap S2 can use insulation
Layer is filled, and can execute impurity injection technology to resulting structures.In addition, by forming the seam of the first gap S1 and second
Gap S2 come use conductive layer 41 replace first material layer 34 after, can be via the first gap S1 implanted dopant.
Above-mentioned technique can partly be changed according to the material for being used to be formed first material layer 34 and second material layer 35.
Specifically, the technique after forming the second gap S2 can partly be changed.
For example, formed by conductive layer when first material layer 34, and when second material layer 35 is formed by interlayer insulating film, in shape
After the second gap S2,34 silication of first material layer that can will be exposed in the second gap S2, the then shape in the S2 of gap
At insulating layer 42.
As another example, when first material layer 34 is formed by conductive layer, and second material layer 35 is formed by sacrificial layer
When, the second material layer 35 exposed in the second gap S2 is removed to form depressed area.Will exposed in second gap S2
One material layer, 34 silication, and insulating layer 42 is formed in depressed area and the second gap S2.
It can be easily by the way that impurity is injected into the second channel layer 37B via the first gap S1 according to above-mentioned technique
Control the threshold voltage of tunnel transistor.Specifically, since the second area 37BB of the second channel layer 37B is configured to have conduction
Attribute, so the part of tunnel transistor corresponding with the second area 37BB of the second channel layer 37B can be held on.Cause
And even if the first channel layer 37A can also be via tool if the second channel layer 37B assembles during the manufacture of semiconductor devices
There is the second area 37BB of conductive properties and is easy connection.
Fig. 4 is the block diagram of storage system 100 according to an embodiment of the invention.
Referring to fig. 4, storage system 100 includes nonvolatile semiconductor memory member 120 and Memory Controller 110.
Nonvolatile semiconductor memory member 120 can have the structure as described in an embodiment of the present invention, or be rendered as
Multi-chip package including multiple flash memory chips.
Memory Controller 110 is configured to control nonvolatile semiconductor memory member 120, and may include that static random is deposited
Access to memory (SRAM) 111, central processing unit (CPU) 112, host interface 113, error correcting code (ECC) unit 114 and storage
Device interface 115.SRAM 111 is used as the operation memory of CPU 112.CPU 112 executes whole control operation in memory control
The swapping data of device 110 and nonvolatile semiconductor memory member 120 processed.Host interface 113 includes the master connecting with storage system 100
The data exchange agreement of machine.ECC Unit 114 detects and corrects the mistake from the data read in nonvolatile semiconductor memory member 120
Accidentally.Memory interface 115 and 120 interface of nonvolatile semiconductor memory member.Memory Controller 110 can also include being configured to store up
Deposit the read-only memory (ROM) etc. for the code data with host interface.
Storage system 100 with above structure can be in conjunction with nonvolatile semiconductor memory member 120 and Memory Controller
110 storage card or solid-state disk (SSD).For example, if storage system 100 is SSD, Memory Controller 110 can be via
Various interface protocols, for example, universal serial bus (USB), multimedia card (MMC), peripheral component interconnection express delivery (PCI-E), string
It is row Advanced Technology Attachment (SATA), parallel advanced technology annex (PATA), small computer system interface (SCSI), reinforced small
One of type equipment interface (ESDI) and electronic integrated driver (IDE) and main-machine communication.
Fig. 5 is the block diagram of computing system 200 according to an embodiment of the invention.
Referring to Fig. 5, computing system 200 may include the CPU 220 connected via system bus 260, random access memory
Device (RAM) 230, user interface 240, modem 250 and storage system 210.Although being not shown, work as computing system
200 when being mobile device, computing system 200 can also include for supply operation voltage to computing system 200 battery, apply
Chipset, camera images processor (CIS) and mobile dynamic random access memory (DRAM).
Storage system 210 may include nonvolatile memory 212 and Memory Controller as described with reference to fig. 4
211。
As described above, can be improved by the threshold voltage for reducing tunnel transistor can send out during program/erase process
The variation of raw threshold voltage.Furthermore, it is possible to improve cell current by the way that tunnel transistor to be kept on.
In the accompanying drawings and the description, various embodiments of the present invention have been disclosed, although specific embodiment is utilized,
But they are only general and illustrative senses, not for purposes of limitation.It, will be appended for the scope of the present invention
It is displayed in claim.Therefore, for those skilled in the art it will be appreciated that being limited not departing from appended claims such as
Various changes can be carried out in the case where fixed the spirit and scope of the present invention in form and details.
It can be seen from the above embodiments that, this application provides technical solutions below.
A kind of semiconductor devices of technical solution 1., comprising: pipe gate；Multiple wordline, the multiple wordline are layered in described
In pipe gate；Multiple first channel layers, the multiple first channel layer are configured to wordline described in break-through；And second channel
Layer, second channel layer are formed in the pipe gate to connect the multiple first channel layer, and are had than institute
State the high impurity concentration of multiple first channel layers.
The semiconductor devices as described in technical solution 1 of technical solution 2., wherein each of the multiple first channel layer packet
It includes undoped polysilicon layer and second channel layer includes the polysilicon layer of doping.
The semiconductor devices as described in technical solution 2 of technical solution 3., wherein second channel layer includes N-type polycrystalline
Silicon layer or p-type polysilicon layer.
The semiconductor devices as described in technical solution 1 of technical solution 4., wherein second channel layer includes: multiple
One area, the multiple firstth area are contacted with the multiple first channel layer；And secondth area, secondth area are arranged on described
Between multiple firstth areas, and there is the impurity concentration higher than the multiple firstth area.
The semiconductor devices as described in technical solution 4 of technical solution 5., wherein the multiple firstth area each includes low
The N-type impurity or p type impurity of concentration, and, secondth area includes the N-type impurity or p type impurity of high concentration.
The semiconductor devices as described in technical solution 4 of technical solution 6., wherein the multiple firstth area has semiconductor category
Property, and, secondth area has conductive properties.
The semiconductor devices as described in technical solution 1 of technical solution 7., wherein second channel layer has conductive belong to
Property.
The semiconductor devices as described in technical solution 1 of technical solution 8., further includes gap, the gap is configured to break-through
The wordline, and be arranged on second channel layer.
The semiconductor devices as described in technical solution 1 of technical solution 9., wherein the pipe gate is configured to surround described
The side surface and lower surface of second channel layer.
The semiconductor devices as described in technical solution 9 of technical solution 10., further includes illusory pipe gate, the illusory pipeline
Grid are formed in the pipe gate, and are configured to surround the upper surface of second channel layer.
The semiconductor devices as described in technical solution 10 of technical solution 11., wherein the illusory pipe gate includes undoped
Polysilicon layer.
The semiconductor devices as described in technical solution 1 of technical solution 12., wherein the pipe gate is configured to surround institute
State the upper surface, side surface and lower surface of the second channel layer.
A kind of semiconductor devices of technical solution 13., comprising: source side memory unit, the source side memory unit
Along the first source side channel layer stackup；Drain side memory cell, the drain side memory cell is along the first drain side
Channel layer stackup；And conductive layer, the conductive layer are configured to the first source side channel layer and first drain electrode
The connection of lateral sulcus channel layer.
Semiconductor devices of the technical solution 14. as described in technical solution 13, further includes:
Source side tunnel transistor, the source side tunnel transistor be connected to the source side memory unit with it is described
Between conductive layer；And drain side tunnel transistor, the drain side tunnel transistor are connected to the drain side memory list
It is first between the conductive layer.
Semiconductor devices of the technical solution 15. as described in technical solution 14, wherein the source side tunnel transistor and institute
Stating drain side tunnel transistor includes with more higher than the first source side channel layer and the first drain side channel layer
Second channel layer of impurity concentration.
A kind of method of the manufacturing semiconductor devices of technical solution 16., comprising the following steps: by etching the first conductive layer come
Form groove；
Sacrificial layer is formed in the trench；It is alternately formed on first conductive layer for being formed with the sacrificial layer
First material layer and second material layer；It forms first material layer and the second material layer described in break-through and connects with the groove
The channel hole connect；Remove the sacrificial layer exposed via the bottom surface in the channel hole；In the channel hole and the ditch
Channel layer is formed in slot, wherein the channel layer includes the first channel layer being formed in the channel hole and is formed in described
The second channel layer in groove；Form the seam of the first material layer and the second material layer between channel hole described in break-through
Gap；And impurity is injected into second channel layer via the gap.
Method of the technical solution 17. as described in technical solution 16, wherein the channel layer includes undoped polysilicon
Layer.
Method of the technical solution 18. as described in technical solution 16, wherein the impurity is N-type impurity or p type impurity.
Method of the technical solution 19. as described in technical solution 16, further includes: after adulterating the impurity, execute at heat
Science and engineering skill.
The semiconductor devices as described in technical solution 1 of technical solution 20., further includes the first accumulation layer, first storage
Layer includes tunnel insulation layer, the electric charge storage layer being arranged among first channel layer and second channel layer and wordline
And all or some in electric charge barrier layer.
Claims (19)
1. a kind of semiconductor devices, comprising:
Multiple wordline, the multiple wordline are layered on top of each other；
Multiple first channel layers, the multiple first channel layer are configured to wordline described in break-through；And
Second channel layer, second channel layer under the multiple wordline with by the multiple first channel layer connect, and
And there is the impurity concentration higher than the multiple first channel layer.
2. semiconductor devices as described in claim 1, wherein the multiple first channel layer each includes undoped more
Crystal silicon layer, and
Second channel layer includes the polysilicon layer of doping.
3. semiconductor devices as claimed in claim 2, wherein second channel layer includes N-type polycrystalline silicon layer or p-type polycrystalline
Silicon layer.
4. semiconductor devices as described in claim 1, wherein second channel layer includes:
Multiple firstth areas, the multiple firstth area are contacted with the multiple first channel layer；And
Secondth area, secondth area are arranged between the multiple firstth area, and are had higher than the multiple firstth area
Impurity concentration.
5. semiconductor devices as claimed in claim 4, wherein the N-type that the multiple firstth area each includes low concentration is miscellaneous
Matter or p type impurity, and
Secondth area includes the N-type impurity or p type impurity of high concentration.
6. semiconductor devices as claimed in claim 4, wherein the multiple firstth area has semiconductor properties and described
Secondth area has conductive properties.
7. semiconductor devices as described in claim 1, wherein second channel layer has conductive properties.
8. semiconductor devices as described in claim 1 further includes gap, the gap is configured to wordline described in break-through, and
And it is arranged on second channel layer.
9. semiconductor devices as described in claim 1, further includes:
Pipe gate, the pipe gate is under the wordline, wherein the pipe gate is configured to surround second channel layer
Side surface and lower surface.
10. semiconductor devices as claimed in claim 9 further includes illusory pipe gate, the illusory pipe gate is formed on institute
It states in pipe gate, and is configured to surround the upper surface of second channel layer.
11. semiconductor devices as claimed in claim 10, wherein the illusory pipe gate includes undoped polysilicon layer.
12. semiconductor devices as claimed in claim 9, wherein the pipe gate is configured to surround second channel layer
Upper surface, side surface and lower surface.
13. semiconductor devices as described in claim 1 further includes the first accumulation layer, first accumulation layer includes that setting exists
Tunnel insulation layer, electric charge storage layer and charge among the multiple first channel layer and second channel layer and wordline hinder
All or some in barrier.
14. a kind of semiconductor devices, comprising:
Multiple wordline, the multiple wordline are layered on top of each other；
Multiple first polysilicon layers, the multiple first polysilicon layer are configured to wordline described in break-through；And
Second polysilicon layer, second polysilicon layer is under the multiple wordline to connect the multiple first polysilicon layer
It connects, and there is the impurity concentration higher than the multiple first polysilicon layer.
15. a kind of semiconductor devices, comprising:
First memory unit, the first memory unit is along the first channel layer stackup；
Second memory unit, the second memory unit is along the second channel layer stackup；And
Conductive layer, the conductive layer are configured to for first channel layer connecting with second channel layer；
The first transistor, the first transistor are connected between the first memory unit and the conductive layer；And the
Two-transistor, the second transistor are connected between the second memory unit and the conductive layer,
Wherein, the first transistor and the second transistor include third channel layer, and the third channel layer has than institute
State the first channel layer and the higher impurity concentration of the second channel layer.
16. a kind of method of manufacturing semiconductor devices, comprising the following steps:
Form sacrificial layer；
First material layer and second material layer are alternately formed on the sacrificial layer；
Form the first channel layer of first material layer and the second material layer described in break-through；
The second channel layer is formed to connect first channel layer by replacing the sacrificial layer with second channel layer；
The gap of first material layer and the second material layer described in break-through is formed between first channel layer；And
Impurity is injected into second channel layer via the gap.
17. the method described in claim 16, wherein first channel layer and second channel layer include undoped
Polysilicon layer.
18. the method described in claim 16, wherein the impurity is N-type impurity or p type impurity.
19. the method described in claim 16, further includes: after adulterating the impurity, execute heat treatment process.
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| KR1020120114868A KR20140048653A (en) | 2012-10-16 | 2012-10-16 | Semiconductor device and method of manufacturing the same |
| KR10-2012-0114868 | 2012-10-16 | ||
| CN201310085518.5A CN103730471B (en) | 2012-10-16 | 2013-03-18 | Semiconductor devices and its manufacturing method |
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| KR20150067811A (en) | 2013-12-09 | 2015-06-19 | 에스케이하이닉스 주식회사 | Semiconductor device and method of manufacturing the same |
| EP3158588A4 (en) * | 2014-06-23 | 2018-01-17 | Intel Corporation | Techniques for forming vertical transistor architectures |
| KR20160025842A (en) | 2014-08-28 | 2016-03-09 | 에스케이하이닉스 주식회사 | Method of manufacturing semiconductor device |
| CN105226066B (en) * | 2015-08-20 | 2018-05-15 | 中国科学院微电子研究所 | Method, semi-conductor device manufacturing method |
| KR20170027571A (en) * | 2015-09-02 | 2017-03-10 | 에스케이하이닉스 주식회사 | Semiconductor device and manufacturing method of the same |
| KR102594494B1 (en) * | 2016-02-17 | 2023-10-27 | 에스케이하이닉스 주식회사 | Semiconductor device and manufacturing method thereof |
| US10096610B1 (en) * | 2017-09-29 | 2018-10-09 | Intel Corporation | Polysilicon doping controlled 3D NAND etching |
| CN109037318B (en) * | 2018-07-26 | 2019-12-13 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of fabricating the same |
| US10714491B2 (en) * | 2018-08-16 | 2020-07-14 | Macronix International Co., Ltd. | Memory device and manufacturing method thereof |
| CN109473440B (en) * | 2018-10-26 | 2020-09-11 | 长江存储科技有限责任公司 | Preparation method of semiconductor device channel layer and semiconductor device |
| KR20210106670A (en) * | 2020-02-21 | 2021-08-31 | 삼성전자주식회사 | Vertical memory devices |
| CN113471212B (en) * | 2021-06-30 | 2022-05-03 | 长江存储科技有限责任公司 | Storage device and manufacturing method thereof |
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| CN103730471B (en) | 2018-09-21 |
| CN103730471A (en) | 2014-04-16 |
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