CN109346116B - SRAM prevents SSO's output self-regulating circuit - Google Patents

SRAM prevents SSO's output self-regulating circuit Download PDF

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CN109346116B
CN109346116B CN201811060347.XA CN201811060347A CN109346116B CN 109346116 B CN109346116 B CN 109346116B CN 201811060347 A CN201811060347 A CN 201811060347A CN 109346116 B CN109346116 B CN 109346116B
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output
delay
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CN109346116A (en
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何宏瑾
刘雯
胡晓明
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protecting against loss of information

Abstract

The invention relates to an output self-adjusting circuit for preventing SSO of an SRAM (static random access memory), which relates to the field of integrated circuit design and comprises n output data sensing modules, a clock signal generating module and a control module, wherein the n output data sensing modules are used for detecting whether the output data D [ n-1,0] of the SRAM is overturned relative to the last clock state; the turnover counting module is used for receiving the n data turnover judging signals D [ i ] _ sensor output by the n output data sensing modules and calculating the n data turnover judging signals D [ i ] _ sensor to obtain corresponding sum signals and carry signals; a logic encoding module, configured to encode the sum signal and the carry signal provided by the flip counting module, and provide control signals S [ i ] (0 ≦ i ≦ z-1) for different delay stages, where z is an integer greater than or equal to 1; and the delay control module controls different delay gears through the control signal Si (0 ≦ i ≦ z-1) provided by the logic coding module, so that the data time sequence which is simultaneously overturned is output, and the output time sequence of the data which is simultaneously overturned and output can be automatically readjusted.

Description

SRAM prevents SSO's output self-regulating circuit
Technical Field
The invention relates to the field of integrated circuit design, in particular to an SSO (stress tolerance) preventing output self-adjusting circuit of an SRAM (static random access memory).
Background
In the field of integrated circuit design, Static Random-Access Memory (SRAM) is a common device.
However, the current SRAM has a problem that a large current is caused by a plurality of IO simultaneous flip outputs, and further a large resistance Drop (IR Drop) is caused. Referring to fig. 1, a circuit for preventing Simultaneous Switching Output (SSO) commonly used in the art is shown in fig. 1. As shown in fig. 1, a delay control signal S in the prior art is externally controlled, and whether half of the output data is delayed to be output is determined by a switch controlled by S. One of the disadvantages of this method is that the control signal is controlled from outside, which is difficult to realize precise control and is not beneficial to avoid SSO in time; the other defect is that only one delayed output data interval exists, and if the influence caused by SSO cannot be solved by delaying and outputting the data of the interval, the circuit also fails, which is not beneficial to purposefully avoiding the SSO.
How to effectively prevent simultaneous flip output (SSO) in SRAM is an urgent problem to be solved in the industry.
Disclosure of Invention
The invention aims to provide an SSO-proof output self-adjusting circuit of an SRAM, which comprises n output data sensing modules, wherein the n output data sensing modules are used for detecting the output data D [ n-1: 0, whether the state of the previous clock is inverted or not is judged, wherein n is an integer larger than or equal to 4, n data inversion judging signals D [ i ] _ sensor are output, and 0 ≦ i ≦ n-1; the turnover counting module is used for receiving the n data turnover judging signals D [ i ] sensor output by the n output data sensing modules and calculating the n data turnover judging signals D [ i ] sensor to obtain corresponding sum signals J _ S [ x-1:0] and carry signals J _ C [ y-1:0 ]; a logic encoding module, configured to encode the sum signal J _ S [ x-1:0] and the carry signal J _ C [ y-1:0] provided by the flip counting module, and provide a control signal S [ i ] of different delay stages, where i ≦ 0 ≦ z-1, and z is an integer greater than or equal to 1; and the delay control module controls different delay gears through the control signal Si provided by the logic coding module so as to output the data time sequence which is simultaneously overturned.
Furthermore, each output data sensing module comprises two clock-controlled flip-flops, wherein the data input of one flip-flop is the data output of the other flip-flop, and the outputs of the two flip-flops respectively represent the states of data D [ i ] in two adjacent clocks, wherein 0 ≦ i ≦ n-1.
Furthermore, each output data sensing module further includes at least one combinational logic gate, and performs logic operation on output data of the data D [ i ] in two adjacent clocks to determine whether the D [ i ] is flipped, where a level output by the combinational logic gate when the flipping occurs is different from an output level when the flipping does not occur, so as to obtain the n data flipping determination signals D [ i ] _ sensor, where 0 ≦ i ≦ n-1.
Furthermore, the combinational logic gate is an exclusive or gate, and performs exclusive or operation on output data of the data D [ i ] in two adjacent clocks, and for input data with inversion, the data inversion determination signal D [ i ] _ sensor at the output of the exclusive or gate is high level, otherwise, the data inversion determination signal D [ i ] _ sensor is low level, where i ≦ 0 ≦ n-1.
Furthermore, the plurality of output data sensing modules are a plurality of same output data sensing modules.
Furthermore, the flip counting module comprises at least one adder, and the n data flip decision signals D [ i ] _ sensor are added by the adder, so as to obtain the sum signal J _ S [ x-1:0] and the carry signal J _ C [ y-1:0 ].
Furthermore, the flip counting module receives the n data flip determination signals D [ i ] _ sensor output by the n output data sensing modules, and calculates the n data flip determination signals D [ i ] _ sensor to obtain the number of data flipped in the n data.
Further, the logic encoding module includes at least one combinational logic gate for encoding the sum signal J _ S [ x-1:0] and the carry signal J _ C [ y-1:0], so as to generate the control signal S [ i ] for controlling the delay of z data intervals, where 0 ≦ i ≦ z-1.
Furthermore, the delay control module comprises a delay circuit and a transmission gate circuit, wherein the delay circuit comprises a plurality of delay modules with fixed delay; the transmission gate circuit comprises a plurality of switch units, and each delay data interval is connected to two branches: the first branch circuit is a series structure formed by serially connecting a switch unit and a delay module, the second branch circuit is a switch unit, whether the data in the data interval is delayed is determined by controlling the switch units in the first branch circuit and the second branch circuit respectively by control signals Si and Si', and when the control signal Si controls the switch unit of the first branch circuit to be conducted, the delay data interval is delayed; when the control signal S [ i ]' controls the switch unit of the second branch to be turned on, the delay data interval is not delayed, where 0 ≦ i ≦ z-1.
Furthermore, each of the control signals si and si' controls a corresponding data interval, and each delayed data interval includes at least one data, where 0 ≦ i ≦ z-1.
Further, the delay module is composed of at least one inverter.
Furthermore, the delay control scheme of the delay control module is to directly divide data that are simultaneously flipped equally according to an ideal data interval, and each control signal si independently controls the delay or conduction of one data interval, so as to provide different delay gears for each data interval, where 0 ≦ i ≦ z-1, where the ideal data interval is the data interval that a designer wants to reach.
Furthermore, the delay control scheme of the delay control module is to divide data that is simultaneously flipped into ideal final-stage data intervals step by step, the delay modules selected in the data intervals of each stage are the same, each control signal S [ i ] individually controls the delay or conduction of one data interval, and different delay gears are provided for each final-stage data interval through the combination of step-by-step delay and conduction, where 0 ≦ i ≦ z-1, where the ideal final-stage data interval is the final-stage data interval that a designer wants to reach.
Furthermore, the delay of the delay module of the first stage is larger than the sum of the delay of each delay module of the following stages.
In an embodiment of the invention, the output timing sequence of the simultaneously inverted output data can be automatically readjusted by the SSO-proof output self-adjusting circuit comprising n output data sensing modules, the inversion counting module, the logic coding module and the delay control module, and the large current caused by the simultaneous inverted output of a plurality of IOs is reduced, so that the IR Drop is avoided.
Drawings
FIG. 1 is a schematic diagram of a prior art SSO prevention circuit.
FIG. 2 is a schematic diagram of an SSO-proof output self-adjusting circuit according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of an output data sensing module according to an embodiment of the invention.
Fig. 4 is a schematic structural diagram of a flip counting module according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a logic encoding module according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a delay coding algorithm according to an embodiment of the present invention.
Fig. 7 is a schematic diagram of a delay control scheme of the delay control module according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of a delay control scheme of a delay control module according to another embodiment of the present invention.
FIG. 9 is a waveform diagram illustrating the operation of the output self-regulating circuit of SRAM against SSO provided by the present invention.
FIG. 10 is a waveform diagram illustrating the operation of the SSO-proof output self-adjusting circuit of SRAM provided by the present invention.
The reference numerals of the main elements in the figures are explained as follows:
100. an output data sensing module; 200. a turnover counting module; 300. a logic encoding module; 400. and a delay control module.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In an embodiment of the present invention, an output self-adjusting circuit for preventing SSO of an SRAM is provided to reduce a large current caused by simultaneous output inversion of a plurality of IOs, thereby avoiding IR Drop. Specifically, referring to fig. 2, fig. 2 is a schematic diagram of an output self-adjusting circuit for preventing SSO according to an embodiment of the present invention. As shown in fig. 2, an output self-adjusting circuit of SRAM for preventing SSO according to an embodiment of the present invention includes: n output data sensing modules 100(n sensors) for detecting the output data D [ n-1: 0, whether the state of the previous clock is inverted or not is judged, wherein n is an integer larger than or equal to 4, n data inversion judging signals D [ i ] _ sensor are output, and 0 ≦ i ≦ n-1; a reverse COUNTING module 200 (reverse COUNTING) for receiving n data reverse determination signals D [ i ] _ sensors outputted from the n output data sensing modules 100 and operating the n data reverse determination signals D [ i ] _ sensors to obtain corresponding sum (S) signals J _ S [ x-1:0] and Carry (CO) signals J _ C [ y-1:0], wherein x and y are integers greater than or equal to 1; a LOGIC encoding module 300(LOGIC CODING) for encoding a sum (S) signal J _ S [ x-1:0] and a Carry (CO) signal J _ C [ y-1:0] provided by the rollover count module 200, and providing a control signal S [ i ] at different delay stages, where 0 ≦ i ≦ z-1 and z is an integer greater than or equal to 1; the DELAY CONTROL module 400(DELAY CONTROL) CONTROLs different DELAY stages according to a CONTROL signal S [ i ] provided by the logic encoding module 300, so that a data timing sequence output that is simultaneously inverted is output, where 0 ≦ i ≦ z-1.
Specifically, please refer to fig. 3, in which fig. 3 is a schematic diagram of an output data sensing module according to an embodiment of the present invention. As shown in fig. 3, each output data sensing module 100 includes two clocked flip-flops 110, wherein the data input of one flip-flop 110 is the data output (Q0) of the other flip-flop 110, and the outputs (Q0, Q1) of the two flip-flops 110 respectively represent the states of data D [ i ] in two adjacent clocks, where 0 ≦ i ≦ n-1. Furthermore, each output data sensing module 100 further includes at least one combinational logic gate, and performs a logic operation on output data (Q0, Q1) of the data D [ i ] in two adjacent clocks to determine whether the D [ i ] is flipped, where a level output by the combinational logic gate when the data D [ i ] is flipped is different from an output level when the data D [ i ] is not flipped, so as to obtain n data flip determination signals D [ i ] _ sensor, where 0 ≦ i ≦ n-1, and the n data flip determination signals D [ i ] _ sensor are sent to the flip counting module 200, where 0 ≦ i ≦ n-1.
Specifically, referring to fig. 3, the combinational logic gate is an xor gate 120, and performs xor operation on output data (Q0, Q1) of data D [ i ] in two adjacent clocks, and for input data with inversion, a data inversion determination signal D [ i ] _ sensor at the output of the xor gate 120 is high, and vice versa, so as to detect whether output data of the SRAM is inverted, where 0 ≦ i ≦ n-1. Of course, in an embodiment of the present invention, a specific structure of each output sensing module is not limited, and as long as an output signal of the output sensing module outputs a signal when the output data of the SRAM is inverted, which is different from a signal when the output data of the SRAM is not inverted, whether the output data of the SRAM is inverted or not can be detected.
More specifically, in an embodiment of the present invention, the plurality of output data sensing modules 100 are a plurality of identical output data sensing modules 100. Each output data sensing module 100 receives output data D [ i ] of an SRAM, where 0 ≦ i ≦ n-1, and outputs a data inversion determination signal (D [ i ] _ sensor,0 ≦ i ≦ n-1) indicating whether or not the corresponding output data D [ i ] is inverted.
Referring to fig. 2, the flip COUNTING module 200 (reverse COUNTING) receives n data flip determination signals D [ i ] sensor outputted from the n output data sensing modules 100, and performs an operation on the n data flip determination signals D [ i ] sensor to obtain corresponding sum (S) signals J _ S [ x-1:0] and Carry (CO) signals J _ C [ y-1:0 ]. Specifically, referring to fig. 4, fig. 4 is a schematic structural diagram of a flip-flop counting module according to an embodiment of the present invention, as shown in fig. 4, the flip-flop counting module 200 includes at least one adder, and n data flip determination signals D [ i ] _ sensors are added by the adder to obtain a sum (S) signal J _ S [ x-1:0] and a Carry (CO) signal J _ C [ y-1:0 ].
In one embodiment, when the circuit is operating, the output sensing module simultaneously detects whether 16 output signals are inverted with respect to the previous clock state, and the output is D [ 15: 0] _ sensor; rollover count module 200 compares D [ 15: 0] sensor addition, the implementation of providing sum (S) and Carry (CO) signals is as follows: carrying out first round addition on 16data through 8 1-bit adders to obtain 8 groups of 2-bit outputs S0, CO; carrying out second round addition on 8 groups of 2-bit data through 4 2-bit adders to obtain 4 groups of 3-bit outputs S0, S1 and CO; carrying out third round addition on 4 groups of 3-bit data by 2 3-bit adders to obtain 2 groups of 4-bit outputs S0, S1, S2 and CO; the fourth addition is performed by 1 4-bit adder to obtain 1 group of 5-bit outputs S0, S1, S2, S3, CO. The 8S 0 resulting from the first round are added in a similar manner to yield 1 set of 4 bit outputs S0, S1, S2, CO.
Furthermore, in an embodiment of the present invention, the flip COUNTING module 200 (reverse COUNTING) receives n data flip determination signals D [ i ] sensor output by the n output data sensing modules 100, and performs an operation on the n data flip determination signals D [ i ] sensor to obtain the number of data flipped in the n data. The output of the last-stage adder in the turnover counting module is the number of the turned data.
Referring to FIG. 2, the LOGIC encoding module 300(LOGIC CODING) encodes the sum (S) signal J _ S [ x-1:0] and the Carry (CO) signal J _ C [ y-1:0] provided by the rollover count module 200 to provide the control signal Si for different delay stages, where 0 ≦ i ≦ z-1 and z is an integer greater than or equal to 1. Specifically, referring to fig. 5, fig. 5 is a schematic structural diagram of a LOGIC encoding module according to an embodiment of the present invention, as shown in fig. 5, a LOGIC encoding module 300(LOGIC CODING) includes at least one combinational LOGIC gate for encoding J _ S [ x-1:0] and J _ C [ y-1:0] so as to generate a control signal S [ i ] for controlling delay of z data intervals, where 0 ≦ i ≦ z-1. Specifically, J _ S [ x-1:0] and J _ C [ y-1:0] are used according to a delay coding algorithm, and signals J _ S [ x-1:0] and J _ C [ y-1:0] are coded to obtain delay control signals S [ z-1,0] of a data interval. In an embodiment of the present invention, please refer to fig. 6, fig. 6 is a schematic diagram of a delay coding algorithm according to an embodiment of the present invention, and the delay coding algorithm shown in fig. 6 encodes corresponding sum (S) and Carry (CO) signals to obtain 3 delay control signals S [2:0 ].
Referring to fig. 2, the DELAY CONTROL module 400(DELAY CONTROL) CONTROLs different DELAY stages according to a CONTROL signal S [ i ] provided by the logic encoding module 300, so that a data timing output that is flipped simultaneously is output, where 0 ≦ i ≦ z-1. Therefore, the output data which are simultaneously overturned are finally output in a time sequence delay way at different gears, and the generation of SSO is avoided.
Specifically, in an embodiment of the present invention, referring to fig. 7, fig. 7 is a schematic diagram of a delay control scheme of the delay control module according to an embodiment of the present invention. As shown in fig. 7, the delay control scheme of the delay control module 400 is to directly divide the data turned over at the same time equally according to an ideal data interval, and each control signal S [ i ] independently controls the delay or conduction of one data interval, so as to provide different delay steps for each data interval, where 0 ≦ i ≦ z-1. Wherein, the ideal data interval is the data interval that the designer wants to reach.
Specifically, in another embodiment of the present invention, referring to fig. 8, fig. 8 is a schematic diagram of a delay control scheme of a delay control module according to another embodiment of the present invention. As shown in fig. 8, the delay control scheme of the delay control module 400 may further divide the data that is simultaneously flipped into two stages (e.g., divide the data into four …) to an ideal final-stage data interval, where the delay modules selected in the data interval of each stage are the same, each control signal S [ i ] independently controls the delay or conduction of one data interval, and different delay stages are provided for each final-stage data interval by combining the stage-by-stage delay and the conduction, where i is less than or equal to 0 and less than or equal to z-1. In an embodiment of the present invention, the delay of the first stage delay module is greater than the sum of the delays of each of the following stages of delay modules. Wherein the ideal final data interval is the final data interval that the designer wants to reach.
Specifically, referring to fig. 7 and 8, the delay control module 400 includes a delay circuit and a transmission gate circuit, wherein the delay circuit includes a plurality of delay modules 410 with fixed delay; the transmission gate circuit includes a plurality of switching elements, each delay data interval being connected to two branches: the first branch is a serial structure of a switch unit and a Delay module 410(Delay Block), and the second branch is a switch unit, and whether the data Delay in the data interval is determined by controlling the switch units in the first branch and the second branch respectively by S [ i ] and S [ i ] ', where S [ i ]' is a signal obtained by inverting the signal S [ i ], and where 0 ≦ i ≦ z-1. Specifically, when the switch unit of the first branch is controlled to be switched on by the Si, the delay data interval is delayed, wherein i is less than or equal to 0 and z-1; when the switch unit of the second branch circuit is controlled to be conducted by the S [ i ]', the delay data interval is not delayed, wherein 0 ≦ i ≦ z-1. In an embodiment of the present invention, each of the control signals si and si' controls a corresponding data interval, and each of the delayed data intervals includes at least one data, where 0 ≦ i ≦ z-1. In one embodiment of the present invention, the delay module 410 is composed of at least one inverter.
Taking 16 outputs ([16Data ]) as an example, adopting the delay control scheme shown in fig. 8, firstly dividing the 16 outputs into two groups of Data intervals ([8Data ]) respectively containing 8Data, and delaying the delay time of the corresponding delay module 410 by 20 n; then, the 8Data are divided into two groups of Data intervals ([4Data ]) containing 4Data, respectively, and the delay time corresponding to the delay module 410 is 10 n. 4 delay gears of 4 groups [4Data ] are realized by 3 delay control signals: 0n,10n,20n,30 n.
Referring to fig. 9 and 10, fig. 9 and 10 are waveform diagrams illustrating the operation of the output self-regulating circuit of SRAM for preventing SSO according to the present invention. As shown in fig. 9, four adjacent data form a data interval, and if four data turned over at the same time are sequentially added, the delay control signal S corresponding to the data interval is turned on, so that the data in the interval is output in a delayed manner, thereby effectively avoiding SSO. As shown in FIG. 10, when D [2i +1] is not flipped and D [2i ] is flipped one by one, whenever there are four data flipped simultaneously, the corresponding delay control signal S is triggered to turn on to ensure that the data flipped simultaneously is less than 4, thereby avoiding SSO, where 0 ≦ i ≦ 7.
Thus, in an embodiment of the present invention, the output self-adjusting circuit for preventing SSO, which includes n output data sensing modules, a flip counting module, a logic coding module, and a delay control module, can automatically readjust the output timing sequence of simultaneously flipped output data, and reduce the large current caused by the simultaneous flip output of a plurality of IOs, thereby avoiding IR Drop.
Furthermore, the delay time sequence of the output data is automatically detected and adjusted under the current output, and for different quantities of simultaneously turned output data, the circuit can pertinently enable the corresponding data interval to be reasonably delayed and output without any additional operation outside, so that the intelligence of the circuit is greatly improved.
Particularly, as the number of output data bits of the SRAM increases, and a large number of output data bits exist, the method of increasing the external signal control delay in the prior art becomes increasingly difficult to operate and implement, which makes it difficult to avoid SSO.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (14)

1. An output self-adjusting circuit of SRAM for preventing SSO, comprising:
n output data sensing modules for detecting the output data D [ n-1: 0, whether the state of the previous clock is inverted or not is judged, wherein n is an integer larger than or equal to 4, n data inversion judging signals D [ i ] _ sensor are output, and 0 ≦ i ≦ n-1;
the turnover counting module is used for receiving the n data turnover judging signals D [ i ] sensor output by the n output data sensing modules and calculating the n data turnover judging signals D [ i ] sensor to obtain corresponding sum signals J _ S [ x-1:0] and carry signals J _ C [ y-1:0], wherein x and y are integers more than or equal to 1;
a logic encoding module, configured to encode the sum signal J _ S [ x-1:0] and the carry signal J _ C [ y-1:0] provided by the flip counting module, and provide a control signal S [ i ] of different delay stages, where i ≦ 0 ≦ z-1, and z is an integer greater than or equal to 1; and
and the delay control module controls different delay gears through the control signal Si provided by the logic coding module, so that the data time sequence which is simultaneously overturned is output, wherein 0 ≦ i ≦ z-1.
2. The SRAM SSO-proof output self-tuning circuit of claim 1, wherein each of the output data sensing modules comprises two clocked flip-flops, wherein a data input of one flip-flop is a data output of the other flip-flop, and outputs of the two flip-flops respectively represent states of data D [ i ] in two adjacent clocks, where 0 ≦ i ≦ n-1.
3. The SRAM SSO-proof output self-adjusting circuit of claim 1, wherein each of the output data sensing modules further comprises at least one combinational logic gate, and the output data of data Di in two adjacent clocks is logically operated to determine whether Di is flipped, and the output level of the combinational logic gate when flipped is different from the output level when flipped is not generated, so as to obtain the n data flip determination signals Di _sensor, where i is less than 0 and less than n-1.
4. The SRAM SSO-proof output self-adjusting circuit of claim 3, wherein the combinational logic gate is an XOR gate, which XOR-operates the output data of data Di [ i ] in two adjacent clocks, and for the input data with inversion, the data inversion decision signal Di [ i ] _ sensor at the output of the XOR gate is high, and vice versa, where 0 ≦ i ≦ n-1.
5. The SRAM SSO-proof output self-adjusting circuit of claim 1, wherein the plurality of output data sensing modules are a plurality of identical output data sensing modules.
6. The SRAM SSO-proof output self-adjusting circuit of claim 1, wherein the flip-counting module comprises at least one adder, and the n data flip-decision signals D [ i ] _ sensors are added by the adder to obtain the sum signal JSx-1: 0 and the carry signal JcY-1: 0.
7. The output self-adjusting circuit of claim 1, wherein the flip counting module receives the n data flip determination signals D [ i ] _ sensor output by the n output data sensing modules, and operates on the n data flip determination signals D [ i ] _ sensor to obtain the number of data flipped in the n data.
8. The SRAM SSO-proof output self-tuning circuit of claim 1, wherein the logic encoding module comprises at least one combinational logic gate for encoding the sum signal J _ S [ x-1:0] and the carry signal J _ C [ y-1:0] to generate the control signal Si that controls a delay of z data intervals, where 0 ≦ i ≦ z-1.
9. The SRAM SSO-proof output self-adjusting circuit of claim 1, wherein the delay control module comprises a delay circuit and a transmission gate circuit, the delay circuit comprising a plurality of fixed-delay modules; the transmission gate circuit comprises a plurality of switch units, and each delay data interval is connected to two branches: the first branch circuit is a series structure formed by serially connecting a switch unit and a delay module, the second branch circuit is a switch unit, whether the data in the data interval is delayed is determined by controlling the switch units in the first branch circuit and the second branch circuit respectively by control signals Si and Si', and when the control signal Si controls the switch unit of the first branch circuit to be conducted, the delay data interval is delayed; when the control signal S [ i ]' controls the switch unit of the second branch to be turned on, the delay data interval is not delayed, where 0 ≦ i ≦ z-1.
10. The SRAM SSO-proof output self-tuning circuit of claim 9, wherein each of the control signals Si and Si' controls a corresponding data interval, each of the delayed data intervals comprises at least one data, and wherein 0 ≦ i ≦ z-1.
11. The SRAM SSO-proof output self-adjusting circuit of claim 9, wherein the delay module is comprised of at least one inverter.
12. The output self-adjusting circuit of claim 9, wherein the delay control scheme of the delay control module is to directly divide the data that is flipped simultaneously equally according to an ideal data interval, and each of the control signals si individually controls the delay or conduction of one data interval, so as to provide different delay steps for each data interval, where 0 ≦ i ≦ z-1, where the ideal data interval is the data interval that a designer wants to achieve.
13. The output self-adjusting circuit of claim 9, wherein the delay control scheme of the delay control module is to divide data that is flipped simultaneously step by step until an ideal final data interval, the delay modules selected for the data interval of each step are the same, each of the control signals si independently controls the delay or conduction of one data interval, and different delay steps are provided for each final data interval by combining the step-by-step delay and the conduction, where 0 ≦ i ≦ z-1, and the ideal final data interval is the final data interval that a designer wants to reach.
14. The output self-adjusting circuit of claim 13, wherein the delay of the first stage of delay module is greater than the sum of the delays of each of the following stages of delay modules.
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