TWI501563B - Digital-to-analog converter and clock controller thereof - Google Patents

Description

Digital analog converter and its clock controller

The present invention relates to a digital analog converter and a clock controller thereof, and more particularly to a digital analog converter that can control a clock signal by the clock controller and trigger actuation according to the clock signal.

Compared with analog signal processing, digital signal processing has higher reliability and lower cost. However, most of the signals in nature still exist in a continuous and analog way. Therefore, when performing signal processing, it is often used. A digital to analog converter (DAC) converts a digital signal into an analog signal.

The digital analog converter has several circuit architectures, wherein the current-steering has a plurality of current cells and can output a large current to directly drive the back-end load without additional high speed. Amplifiers are more operationally fast than digital analog converters in other architectures. Therefore, the current steering architecture is widely used in the transmission end of high speed wireless communication systems, such as IEEE 802.11, LTE, WiMax, DVB-T, and the like.

In the operation of the digital-to-analog converter of the current-guided architecture, a clock signal is received first, and in each trigger state of the clock signal, the switching circuit in the plurality of current units is controlled according to an input signal. It is turned on or off to control the output current signal of the digital analog converter. However, even if the input signal is not updated, each current unit continues to receive the clock signal, and continuously enables the power in the trigger state of each clock signal. The switching circuit of the flow unit performs an action of opening or closing, and the unnecessary opening and closing operation also generates excessive power consumption. In addition, when the current unit continuously receives the clock signal, the output current signal of each current unit is interfered by the clock noise due to the clock feedthrough factor, causing the digital position. The output current signal quality of the analog converter is degraded.

The main object of the present invention is to provide a digital analog converter and a clock controller thereof, and reduce the unnecessary switching action of the digital analog converter through the clock controller to reduce the overall power consumption.

Another object of the present invention is to provide a digital analog converter and a clock controller thereof, and control the clock signal of the digital analog converter through the clock controller to improve the quality of the output signal.

In order to achieve the foregoing object, the present invention provides a digital analog converter comprising: a decoding module comprising a column of decoders and a row of decoders, the column decoder having a plurality of column elements arranged in M columns a line, the row decoder has a plurality of row bit lines arranged in N rows, wherein M and N are positive integers greater than 0, and the decoding module decodes an input signal by a decoding program and decodes a column. The signal is outputted by the plurality of column bit lines, and a row of decoding signals is outputted by the plurality of row bit lines; and a plurality of current units are arranged in M columns and N rows, wherein M and N are greater than a positive integer of 0, each of the current units includes a determination circuit and a current switch circuit, each of the determination circuits being electrically connected to the corresponding column bit line and the row bit line, each of the current switch circuits includes a variable clock signal input port and a current output end, each of the current switch circuits is electrically connected to each of the judging circuits, and the current output end of each current switch circuit can be controlled by the signals output by the judging circuits One output a current pulse signal generator for generating a clock signal, wherein the clock signal generator is electrically connected to the decoding module to transmit the clock signal to the column decoder and the row decoder; and Clock control The plurality of clock controllers are arranged in N rows, and the plurality of clock controllers of the i-th row correspond to the row of the row lines of the i-th row and the plurality of current units of the i-th row, wherein N and i are positive integers greater than 0, and i=1, 2, . . . , N, each of the clock controllers has a clock signal input port, a first signal input port, and a second signal input. And a clock signal output 埠, the clock signal input of each clock controller is electrically connected to the clock signal generator to receive the clock signal, and the clock controller of the ith line The first signal input is electrically connected to the row bit line of the i-th row, and the second signal input of the clock controller of the i-th row is electrically connected to the row bit of the i+1th row a line, and the first signal input of the clock controller of the Nth row is electrically connected to the row bit line of the Nth row, and the second signal input of the clock controller of the Nth row is received by the line a low level signal, the variable clock signal output of the clock controller of the i-th row is electrically connected to the variable clock signal input of each current unit of the i-th row, the clock The controller determines the signal received by the first signal input port and the second signal input port. If the signal of the first signal input port and the second signal input port are the same, the variable clock signal output is determined according to Receiving the clock signal, the output has only one clock pulse change pulse signal. If the signal of the first signal input port and the second signal input port are different, the variable clock signal output is based on The received clock signal outputs the variable clock signal having a continuous clock cycle.

In the digital analog converter of the present invention, each of the clock controllers comprises a line of signal determining circuit, an inverter and a variable clock switching circuit, wherein the three input terminals of the signal determining circuit are the clock signal input ports. The first signal input port and the second signal input port, the output end of the signal determining circuit is electrically connected to one of the control terminals of the variable clock switch circuit, and one of the input terminals of the inverter is the time The pulse signal input port is electrically connected to one of the input terminals of the variable clock switch circuit, and one of the output terminals of the variable clock switch circuit is the variable clock signal output port.

The digital analog converter of the present invention, wherein the line signal judging circuit comprises a peer judging circuit, a row judging circuit, a double row judging switch and a total judging circuit, the same The second input end of the line judging circuit is the first signal input and the time pulse signal input port respectively, and the second input end of the line judging circuit is the second signal input, the time pulse signal input port, and the double line judgment. One of the input ends of the switch is the first signal input port, and the second control end of the two-line determination switch is the second signal input port, and the peer determination circuit, the second line determination circuit and the double line determination switch respectively have an output And each of the output terminals is electrically connected to the three input ends of the total judging circuit, and an output end of the total judging circuit is an output end of the signal judging circuit.

In the digital analog converter of the present invention, the peer judging circuit includes a register and a mutex or a gate, and the input terminals of the register are the clock signal input port and the first signal input port respectively. One of the outputs of the register is electrically connected to one of the mutex or gate inputs, and the other input of the mutex or gate is the first signal input port, one of the mutually exclusive or gates The output is the output of the peer judgment circuit.

In the digital analog converter of the present invention, the second line judging circuit includes a register and a mutex or a gate, and the input terminals of the register are the clock signal input port and the second signal input, respectively. The output of one of the registers is electrically connected to one of the mutex or gate inputs, and the other input of the mutex or gate is the second signal input port, the mutual exclusion or gate An output is the output of the line determination circuit.

The digital analog converter of the present invention, wherein the two-line determination switch relationship is a CMOS switch, and when the two control terminals of the two-line determination switch receive a low level signal, the output end of the two-line determination switch outputs the The signal input by the first signal is received; when the second control terminal of the two-line determination switch receives a high level signal, the output of the two-line determination switch outputs a low level signal.

The digital analog converter of the present invention, wherein the total judgment circuit is an OR gate, and the three input terminals of the OR gate are electrically connected to the output terminals of the peer judgment circuit, the second row judgment circuit and the double row judgment switch, respectively, The output end of the gate is the output end of the signal judging circuit, and the gate receives the signal at the output end of the peer judging circuit, the second line judging circuit and the double line judging switch. Then, performing a logic judgment, and outputting a judgment signal to the output end of the signal judging circuit, and the output end of the OR gate includes a forward output port and a reverse output port, and the forward output port directly outputs the The judgment signal, the reverse output is outputting the complementary judgment signal.

The digital analog converter of the present invention, wherein the variable clock switching circuit is a a CMOS switch, and the control end of the variable clock switch circuit includes a first control port and a second control port, the first control device is electrically connected to the positive output port of the total determining circuit, and the second control device is electrically connected Sexually connecting the reverse output of the total decision circuit, when the first control 该 of the time varying switch circuit receives the high level signal from the positive output 埠, and the second control 埠 receives the low level from the reverse output 埠In the signal, the output of the variable clock switch circuit outputs the clock signal passing through the inverter.

The digital analog converter of the present invention, wherein the clock controller has a protection power The protection circuit is a transistor, and one of the protection circuits is electrically connected to the output end of the variable clock switch circuit, and one of the protection circuits is electrically connected to the variable clock switch circuit In the second control port, one of the protection circuits is connected to a ground terminal.

The digital analog converter of the present invention, wherein the judgment circuit package of each current unit a row of bit input port, a row bit input port, a row bit bit input port, and a switching signal output port, and the column bit input lines of each of the determining circuits of the M column are electrically connected to the Mth column The row bit line, the row bit input line of each of the judging circuits of the i-th row is electrically connected to the row bit line of the i-th row, and the sub-line bit input system of each judging circuit of the i-th row Electrically connected to the row bit line of the (i+1)th row, and the row bit input line of each of the determining circuits of the Nth row is electrically connected to the row bit line of the Nth row, the Nth row The sub-line input of each of the judging circuits receives a low-level signal, where i is a positive integer greater than 0, and i=1, 2, . . . , N, the current switch of each current unit The circuit further has a switching signal input port, and the switching signal input of the current switching circuit is electrically connected to the switching signal output port.

The digital analog converter of the present invention, wherein the determining circuit of each current unit The system includes a gate and a gate, and the input terminals of the gate are respectively the column input port and the row bit input port, and one of the output terminals of the gate is connected to one of the input terminals of the gate The other input terminal of the OR gate is the row bit input port, and one of the outputs of the OR gate is the switch signal output port.

The digital analog converter of the present invention, wherein the decoding program is a thermometer decoder.

A clock controller of the present invention comprises: a clock signal input port, a first signal input port, a second signal input port, and a variable clock signal output port, wherein the clock signal input port is used for receiving a time. a pulse signal, the clock controller determines a signal received by the first signal input port and the second signal input port, and if the signal of the first signal input port and the second signal input port are the same, the time change The output of the pulse signal is based on the received clock signal, and the output has only one clock pulse of one clock period. If the signal of the first signal input and the second signal input is different, the time is changed. The pulse signal output system outputs the variable clock signal having a continuous clock cycle according to the received clock signal.

1‧‧‧Decoding module

11‧‧‧ column decoder

111‧‧‧ column line

12‧‧‧ line decoder

121‧‧‧ row line

2‧‧‧current unit

21‧‧‧ judgment circuit

211‧‧‧ Column entry 埠

212‧‧‧ row bit input埠

213‧‧‧Secondary row input埠

214‧‧‧Switch signal output埠

21a‧‧‧ and gate

21b‧‧‧ or gate

22‧‧‧ Current Switch Circuit

221‧‧·Variable clock signal input埠

222‧‧‧Switch signal input埠

223‧‧‧current output

3‧‧‧clock signal generator

4‧‧‧clock controller

41‧‧‧clock signal input埠

42‧‧‧First signal input埠

43‧‧‧Second signal input埠

44‧‧‧Variable clock signal output埠

45‧‧‧Signal Judgment Circuit

451‧‧‧ peer judgment circuit

451a‧‧‧ register

451b‧‧‧mutual exclusion or gate

452‧‧‧Second line judgment circuit

452a‧‧‧ register

452b‧‧‧mutual exclusion or gate

453‧‧‧Double line judgment switch

454‧‧‧General judgment circuit

46‧‧‧ reverser

47‧‧‧Variable clock switching circuit

48‧‧‧Protection circuit

Figure 1 is a block diagram of a digital analog converter of the present invention.

Figure 2: Circuit diagram of the current unit of the digital analog converter of the present invention.

Figure 3: Circuit diagram of the clock controller of the digital analog converter of the present invention.

Figure 4a is a schematic diagram of the variable clock signal output of the clock controller of the present invention.

Figure 4b is a schematic diagram of the variable clock signal output of the clock controller of the present invention.

The above and other objects, features and advantages of the present invention will become more apparent and obvious. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. Referring to FIG. 1 , which is a block diagram of a digital analog converter of the present invention, the digital analog converter includes a decoding. a module 1, a plurality of current units 2, a clock signal generator 3, and a plurality of clock controllers 4, wherein the plurality of current units 2 are electrically connected to the decoding module 1, and the clock signal generator 3 is electrically The plurality of clock controllers 4 are electrically connected to the decoding module 1, the plurality of current units 2, and the clock signal generator 3.

The decoding module 1 includes a row of decoders 11 and a row of decoders 12 having a row of bit lines arranged in M columns, the row decoders having N rows arranged a plurality of row bit lines, wherein M and N are positive integers greater than 0, and the decoding module decodes an input signal by a decoding program, and outputs a column of decoded signals from the plurality of column bit lines. The row of decoded signals is outputted by the plurality of row bit lines. In this embodiment, the column decoding signal has a plurality of column bits, and each of the column bits is sequentially output by each of the column bit lines 111. The row decoding signal has a plurality of row bits, and each row bit is sequentially output by each row bit line 121. The decoding program of the decoding module 1 can be any conventional decoding method. In this embodiment, the decoding program is a Thermometer decoder.

The plurality of current units 2 are electrically connected to the decoding module 1, and the plurality of current units are arranged in M columns and N rows, wherein M and N are positive integers greater than 0. In this embodiment, the plurality of The current unit 2 forms a two-dimensional one-current current cell array in a row-column arrangement, and the number of columns of the current cell array corresponds to the number of columns of the plurality of column bit lines 111 of the decoding module 1. The number of rows of the current cell array is the number of rows corresponding to the plurality of row bit lines 121 of the decoding module 1.

Referring to FIG. 2, each of the current units 2 includes a determining circuit 21 and a current switching circuit 22. Each of the determining circuits 21 is electrically connected to the corresponding bit line 111 and the row. The bit line 121, each of the determining circuits 21 is electrically connected to each of the determining circuits 22, and the output current of each of the current switch circuits 22 can be controlled by the signals output by the judgment circuits 21. In more detail, the determining circuit 21 includes a column of bit input ports 211, a row of bit input ports 212, a row bit bit input port 213, and a switching signal output port 214, and each of the determining circuits 21 of the Mth column The column bit input 211 is electrically connected to the column bit line 111 of the Mth column, and the row bit input port 212 of each of the judging circuits 21 of the i-th row is electrically connected to the row bit of the i-th row. The line 121, the sub-line input port 213 of each of the judging circuits 21 of the i-th row is electrically connected to the row bit line 121 of the i+1th row, and the row of the judging circuit 21 of the Nth row The bit input port 212 is electrically connected to the row bit line 121 of the Nth row, and the second row bit input port 213 of the determining circuit 21 of the Nth row receives a low level signal, and the binary signal is For example, the low level signal is 0, where i is a positive integer greater than 0, and i=1, 2, . . . , N. The current switch circuit 22 has a variable clock signal input port 221, a switch signal input port 222, and a current output terminal 223. The switch signal input port 222 of the current switch circuit 22 is electrically connected to the switch signal output port 214. The determining circuit 21 determines the input data of the row bit input port 211, the row bit element input port 212, and the row bit bit input port 213, and thereby turns on or off the current output of the current switch circuit 22. The output current of terminal 223. In this embodiment, the determining circuit 21 includes an AND gate 21a and an OR gate 21b. The input terminals of the gate 21a are the column bit input 211 and the row bit, respectively. The input port 212 is connected to one of the input terminals of the OR gate 21b, and the other input terminal of the OR gate 21b is the row bit input port 213, and one of the OR gates 215 outputs The end is the switching signal output 埠214.

The clock signal generator 3 is configured to generate a clock signal, and the clock signal has a plurality of clock cycles. The clock signal generator 3 is electrically connected to the decoding module 1 to transmit the clock signal to the column decoder 11 and the row decoder 12, so that the column decoder 11 and the row decoder 12 can receive the The data is calculated by triggering the clock signal.

Please refer to Figures 1 and 3, the several clock controllers 4 are arranged in N And the plurality of clock controllers 4 of the i-th row correspond to the row of bit lines of the i-th row and the plurality of current cells of the i-th row, wherein N and i are positive integers greater than 0, and i=1, 2, ..., N. Each of the clock controllers 4 has a clock signal input port 41, a first signal input port 42, a second signal input port 43, and a variable clock signal output port 44. The clock signal input 41 of each clock controller 4 is electrically connected to the clock signal generator 3 to receive the clock signal, and the first signal input of the clock controller 4 of the i-th row is 42 The row is connected to the row bit line 121 of the i-th row, and the second signal input port 43 of the clock controller 4 of the i-th row is electrically connected to the row bit line 121 of the i+1th row. And the first signal input port 42 of the clock controller 4 of the Nth row is electrically connected to the row bit line 121 of the Nth row, and the second signal input of the clock controller 4 of the Nth row The 埠43 system receives a low level signal, taking the binary signal as an example, the low level signal is 0, and the clock signal output 埠44 of the clock controller 4 of the ith line is electrically connected to the ith The clock signal of each current unit 2 is input to 埠221, and the clock controller 4 determines the signals received by the first signal input port 42 and the second signal input port 43, if the first signal input埠42 and the second signal input 埠43 have the same signal, and the variable clock signal output 埠44 is based on the received clock signal, and the output has only one clock cycle. If the signals of the first signal input port 42 and the second signal input port 43 are different, the variable clock signal output port 44 is based on the received clock signal, and the output has a continuous clock. The changing clock signal of the cycle.

Referring to FIG. 3 again, each of the clock controllers 4 includes a row of signal determining circuit 45, an inverter 46 and a variable clock switching circuit 47. The three input terminals of the signal determining circuit 45 are connected. For the clock signal input port 41, the first signal input port 42 and the second signal input port 43, the output end of the signal determining circuit 45 is electrically connected to one of the control terminals of the variable clock switch circuit 47. The input end of the inverter 46 is the clock signal input port 41. The output end of the inverter 46 is electrically connected to one input end of the variable clock switch circuit 47. One of the output terminals of the switch circuit 47 is the variable clock signal output 埠44. Among them, The logic operation of the clock controller 4 can be matched with other circuits. Therefore, before entering the variable clock switch circuit 47, the clock signal needs to pass through the inverter 46 to ensure the calculation of the digital circuit. accuracy.

In this embodiment, the line signal determining circuit 45 includes a peer judgment power. The circuit 451, the primary line determining circuit 452, the two-line determining switch 453 and a total determining circuit 454, wherein the two input terminals of the peer determining circuit 451 are the clock signal input port 41 and the first signal input port 42, respectively. The input terminals of the second line determining circuit 452 are respectively the clock signal input port 41 and the second signal input port 43, and the input end of the two-line judging switch 453 is the first signal input port 42, the double line The second control terminal of the determination switch 453 is the second signal input port 43, the peer determination circuit 451, the second line determination circuit 452 and the double line determination switch 453 respectively have an output end, and each of the output ends is electrically connected to the output terminal The output terminal of the total judgment circuit 454 is the output end of the signal judging circuit 45, and is electrically connected to the control end of the variable clock switch circuit 47.

More specifically, the peer determination circuit 451 includes a register 451a and a The mutually exclusive or (XOR) gate 451b, the register 451a can be any temporary storage circuit, or the D-type flip-flop as in the embodiment, the input terminals of the register 451a are respectively the clock signal The input port 41 and the first signal input port 42 are electrically connected to an input end of the mutex or gate 451b, and the other input end of the mutex or gate 451b is The first signal input terminal ,42, the output end of the mutual exclusion gate 451b is the output end of the peer judgment circuit 451, and is electrically connected to the input end of the total judgment circuit 454.

The row determining circuit 452 includes a register 452a and a mutually exclusive (XOR) gate 452b. The register 452a can be any temporary storage circuit, or a D-type flip-flop as in the embodiment. The input terminals of the register 452a are respectively the clock signal input port 41 and the second signal input port 43, and one of the output terminals of the register 452a is electrically connected to one of the mutual exclusion or gate 452b inputs. The other input end of the mutex or gate 452b is the second signal input port. The output end of the mutex or gate 452b is the output end of the sub-line judging circuit 452, and is electrically connected to the input end of the total judging circuit 454.

The two-line determination switch 453 is a CMOS switch, when the two lines are judged to be on When the low-level signal received by the control terminal 453 bis, the output of the two-line determination switch 453 outputs the signal received by the first signal input port 42; when the two-line determination switch 453 is controlled by two When the terminal receives a high-level signal, the output of the two-line determination switch 453 outputs a low-level signal. For example, when the signal of the output terminal is binary, the output low-level signal is 0.

The total judgment circuit 454 is an OR gate 454a, and the three inputs of the OR gate 454a. The end terminals are electrically connected to the output terminals of the peer determining circuit 451, the second line determining circuit 452 and the double line determining switch 453, and the output end of the OR gate is the output end of the signal determining circuit 45. The OR gate 454a may perform a logic determination after receiving the signals of the output terminals of the peer determination circuit 451, the second line determination circuit 452, and the double line determination switch 453, and output a determination signal to the output end of the signal determination circuit 45, and The output end of the OR gate 454a includes a forward output 埠 and a reverse output 埠. The forward output 直接 directly outputs the determination signal, and the reverse output 输出 outputs the complementary determination signal.

The variable clock switch circuit 47 is a CMOS switch, and the variable clock switch The control terminal of the circuit 47 includes a first control port and a second control port. The first control port is electrically connected to the forward output port of the total determining circuit 454. The second control device is electrically connected to the total determining circuit 454. The reverse output 埠. When the first control 该 of the time-varying switch circuit 47 receives the high-level signal from the positive output 埠, and the second control 埠 receives the low-level signal from the reverse output ,, the variable-time switch circuit is enabled. The output of 47 outputs the clock signal through the inverter 46.

In order to avoid receiving the low level when the first control 该 of the variable clock switch circuit 47 receives When the second control unit receives the high level signal, the variable clock circuit 47 is damaged. The clock controller 4 preferably has a protection circuit 48, and the protection circuit 48 is a battery. a crystal, and one of the protection circuits 48 is electrically connected to the output end of the variable clock switch circuit 47. One of the protection circuits 48 is electrically connected to the second control port of the variable clock switch circuit 47. One of the protection circuits 48 has a source connected to a ground.

In order to clearly explain the operation flow of the present case, the following describes the logic judgment and signal output of each circuit component in an embodiment.

If the row decoder 12 has 8 row bit lines 121, and the number of rows of the array formed by the current cell 2 is also 8, when the row decoder signal output by the row decoder 12 is sequentially 〝11000000〞 In the current unit 2 shown in FIG. 2, regardless of the column decoding signal output by the column decoder 11, the current unit 2 in the first row is in an on state, and each of the clock controllers 4 is The first signal input port 42 is electrically connected to the row bit line 121 of the same row number, and the second signal input port 43 of each clock controller 4 is electrically connected to the row bit line of the next row number. 121, the variable clock signal output 埠44 of each of the clock controllers 4 is electrically connected to the variable clock signal input 埠221 of the current unit 2 of the same number of rows, and therefore, the clock control with respect to the first row In the case of the device 4, when the row decoding signal is updated to 〞11000000〞, the first signal input 42 receives the first row 〝1〞, and the second signal input 埠43 receives the second row bit. 〝1〞, and at the first trigger edge (positive edge or negative edge) of the clock signal, if the peer judgment circuit 451 is temporarily stored 451a has stored a bit 〝0〞 in advance, or the register 452a of the row determining circuit 452 has pre-stored a bit 〝0〞, and the variable clock switch circuit 47 is turned on to make the clock signal The first clock cycle of the clock signal received by the input port 41 passes through the variable clock switch circuit 47, and after entering the second trigger edge of the clock signal, the peer judgment circuit 451 and the second line judge The value temporarily stored in the registers 451a, 452a in the circuit 452 has become the bit 〝1 输入 input in the previous clock cycle, which will cause the variable clock switch circuit 47 to be turned off, and the clock signal is input. The clock signal received by 埠41 cannot pass through the variable clock switch circuit 47, and outputs a variable clock signal as shown in FIG. 4a, since the variable time signal is transmitted to the plurality of currents in the first line. The variable clock signal of unit 2 is input to 埠221, and the first line is The plurality of current units 2 are turned on when the first clock is triggered, and no triggering action is generated any more to continue to be in a conducting state, so that the plurality of current units 2 of the first row are only subjected to one-time clock triggering. , thereby reducing unnecessary switching action due to excessive clock triggering.

Similarly, the line decoding signal outputted by the decoder 12 is 〝11000000〞 In the case of the plurality of current cells 2 of the second row, whether the plurality of current cells 2 are in an on state is determined by the column decoding signal output by the column decoder 11. Therefore, with respect to the clock controller 4 of the second row, the first signal input port 42 receives the second row bit 〝1〞, and the second signal input port 43 receives the third row bit 〝0〞, And the dual-line determination switch 453 continues to output the high-level signal 〝1〞, so that the variable clock switch circuit 47 continues to be in an on state, and the clock signal received by the clock signal input 埠41 continues to pass through. The variable clock switch circuit 47 outputs a variable clock signal as shown in FIG. 4b, so that the plurality of current units 2 of the second row can receive the variable clock signal having a continuous clock period, and Each of the triggering edges of the clock signal is changed such that the plurality of current units 2 of the second row are adjusted to be in an on or off state according to the column decoding signal.

Similarly, the line decoding signal outputted by the decoder 12 is 〝11000000〞 In the case of the plurality of current units 2 of the third row, regardless of the column decoding signals output by the column decoder 11, the plurality of current units 2 in the third row are in an off state, and therefore, relative to the third For the clock controller 4 of the row, when the row decoding signal is updated to 〞11000000〞, the first signal input 42 receives the third row 〝0〞, and the second signal input 埠43 receives The second row of bits 〝0〞, and at the first trigger edge of the clock signal, if the register 451a of the peer determination circuit 451 has previously stored a bit 〝1〞, or the line determination circuit The register 452a of 452 has pre-stored one bit 〝1〞, and the variable clock switch circuit 47 is in an on state, so that the clock signal is input to the first clock period of the clock signal received by 埠41. Through the variable clock switch circuit 47, after entering the second trigger edge of the clock signal, the value temporarily stored in the register 451a, 452a in the peer determination circuit 451 and the second line determination circuit 452 has become The bit 〝0〞 input by the previous clock cycle will cause the variable clock switch circuit 47 to cut State, and Similarly, the variable clock signal as shown in FIG. 4a is output, because the variable clock signal is transmitted to the variable clock signal input 埠221 of the plurality of current units 2 in the third row, and the number of the third row is made. The current unit 2 is in an off state when the first clock is triggered, and no trigger action is generated any more to continue the off state, so that the plurality of current units 2 of the third row are only subjected to the clock trigger of one time, and further Reduce unnecessary switching action due to excessive clock triggering.

In summary, the digital analog converter of the present invention can determine the clock controller The difference between the peer bit and the second row bit, and adjusting the variable clock signal input to the plurality of current cells according to the judgment result, when it is determined that the opening and closing of the current unit of the peer is independent of the column decoding signal, only output The variable clock signal with one clock cycle prevents the switching circuit of the current unit from continuously opening and closing due to the clock triggering, and has the effect of reducing the overall power consumption.

The digital analog converter of the present invention, the clock controller can judge the peer bit and the second The difference between the row bits, and according to the judgment result, the variable clock signal input to the plurality of current units is adjusted. When it is determined that the opening and closing of the current unit of the peer is independent of the column decoding signal, only the output has one clock period. The variable clock signal prevents the current unit from being continuously triggered by the clock signal, reducing the clock penetration effect and improving the signal output quality.

While the invention has been described in connection with the preferred embodiments described above, it is not intended to limit the scope of the invention. The technical scope of the invention is protected, and therefore the scope of the invention is defined by the scope of the appended claims.

1‧‧‧Decoding module

11‧‧‧ column decoder

111‧‧‧ column line

12‧‧‧ line decoder

121‧‧‧ row line

2‧‧‧current unit

3‧‧‧clock signal generator

4‧‧‧clock controller

41‧‧‧clock signal input埠

42‧‧‧First signal input埠

43‧‧‧Second signal input埠

44‧‧‧Variable clock signal output埠

Claims (21)

A digital analog converter comprises: a decoding module comprising a column of decoders and a row of decoders, the column decoder having a plurality of column bit lines arranged in M columns, the row decoders having N rows arranged a plurality of row bit lines, wherein M and N are positive integers greater than 0, and the decoding module decodes an input signal by a decoding program, and outputs a column of decoded signals from the plurality of column bit lines. And outputting a row of decoding signals from the plurality of row bit lines; a plurality of current cells, the plurality of current cells are arranged in M columns and N rows, wherein M and N are positive integers greater than 0, and each current unit comprises a judging circuit and a current switching circuit, each of the judging circuits being electrically connected to the corresponding bit line and the row bit line, each current switching circuit comprising a variable clock signal input and a current output The current switching circuit is electrically connected to each of the determining circuits, and the output current of one of the current output terminals of each current switching circuit is controlled by the signal output by each of the determining circuits; a clock signal generator, Used to generate one a clock signal, the clock signal generator is electrically connected to the decoding module to transmit the clock signal to the column decoder and the row decoder; and a plurality of clock controllers, the plurality of clock controllers The plurality of clock controllers of the i-th row are corresponding to the row of the bit line of the i-th row and the plurality of current units of the i-th row, wherein N and i are both greater than 0. An integer, and i=1, 2, . . . , N, each of the clock controllers has a clock signal input port, a first signal input port, a second signal input port, and a variable clock signal output port. The clock signal input of each clock controller is electrically connected to the clock signal generator to receive the clock signal, and the first signal input of the clock controller of the i-th row is electrically connected. To the row bit line of the i-th row, the second signal input of the clock controller of the i-th row is electrically connected Connected to the row bit line of the i+1th row, and the first signal input of the clock controller of the Nth row is electrically connected to the row bit line of the Nth row, the Nth row The second signal input of the clock controller receives a low level signal, and the variable clock signal output of the clock controller of the i-th row is electrically connected to the time of each current unit of the ith row. After the pulse signal is input, the clock controller determines the signal received by the first signal input port and the second signal input port, and if the signal of the first signal input port and the second signal input port are the same, The variable clock signal output system outputs a pulse signal having only one clock period according to the received clock signal. If the signal of the first signal input and the second signal input is different, The variable clock signal output system outputs the variable clock signal having a continuous clock period according to the received clock signal. According to the digital analog converter of claim 1, wherein each of the clock controllers comprises a line of signal determining circuit, an inverter and a variable clock switching circuit, wherein the three input terminals of the signal determining circuit are The clock signal input port, the first signal input port and the second signal input port, the output end of the signal determining circuit is electrically connected to one of the control terminals of the variable clock switch circuit, and one of the inverters is input The end is the clock signal input port, and one of the output terminals of the inverter is electrically connected to one of the input ends of the variable clock switch circuit, and one of the output terminals of the variable clock switch circuit is the variable clock Signal output 埠. According to the digital analog converter of claim 2, wherein the signal judging circuit comprises a peer judging circuit, a row judging circuit, a double row judging switch and a total judging circuit, and the second input end of the peer judging circuit The first signal input is the first pulse input signal, and the second input end of the second circuit is the second signal input, the time pulse signal input port, and the input end of the two-line determination switch is The first signal input 埠, the second control end of the two-line determination switch is the The second signal input port, the peer determining circuit, the second line determining circuit and the double line determining switch respectively have an output end, and each of the output ends is electrically connected to the three input ends of the total determining circuit, and the total determining circuit is An output is the output of the signal determination circuit. According to the digital analog converter of claim 3, wherein the peer judgment circuit includes a register and a mutual exclusion gate, and the input terminals of the register are the clock signal input and the The first signal input port is electrically connected to one of the mutex or gate inputs, and the other input end of the mutex or gate is the first signal input port, the mutual One of the outputs of the repulsion or gate is the output of the peer judgment circuit. According to the digital analog converter of claim 3, wherein the second determining circuit comprises a register and a mutually exclusive or gate, the input terminals of the register are respectively the clock signal input and The second signal input port is electrically connected to one of the mutex or gate inputs, and the other input end of the mutex or gate is the second signal input port. One of the mutually exclusive or gate outputs is the output of the line determination circuit. According to the digital analog converter of claim 3, wherein the two-line determination relationship is a CMOS switch, and when the two control terminals of the two-line determination switch receive a low level signal, the two-line determination switch is enabled. The output end outputs the signal received by the first signal input port; when the second control end of the two-line determination switch receives a high level signal, the output end of the two-line determination switch outputs a low level signal. According to the digital analog converter of claim 3, wherein the total judgment circuit is an OR gate, and the three input terminals of the gate are electrically connected to the peer judgment circuit, the second row judgment circuit and the double row judgment switch respectively. The output end of the OR gate is the output end of the signal judging circuit, and the OR gate receives the peer judging circuit and the second line judging circuit And after the signal of the output of the double-line judging switch, the logic judges and outputs a judgment signal to the output end of the signal judging circuit, and the output end of the OR gate includes a forward output port and a reverse output port. The forward output system directly outputs the determination signal, and the reverse output system outputs the complementary determination signal. The digital analog converter of claim 7, wherein the variable clock switching circuit is a CMOS switch, and the control end of the variable clock switching circuit includes a first control port and a second control port. The first control is electrically connected to the positive output of the total determining circuit, and the second control is electrically connected to the reverse output of the total determining circuit, when the first control of the time varying switching circuit is received from the positive direction When the high level signal of the output is received, and the second control unit receives the low level signal from the reverse output, the output of the variable clock switch circuit outputs the clock signal passing through the inverter. According to the digital analog converter of claim 8, wherein the clock controller has a protection circuit, and the protection circuit is a transistor, and one of the protection circuits is electrically connected to the variable clock switch circuit. At the output end, one of the protection circuits is electrically connected to the second control port of the variable clock switch circuit, and one source of the protection circuit is connected to a ground. According to the digital analog converter of claim 1, wherein the determining circuit of each current unit comprises a column of bit input ports, a row of bit input ports, a row bit bit input port, and a switching signal output port, and the Mth The row bit input lines of each of the judging circuits are electrically connected to the column bit lines of the Mth column, and the row bit input lines of the judging circuits of the i-th row are electrically connected to the i-th row. a row bit line, the sub-line input of each of the judging circuits of the i-th row is electrically connected to the row bit line of the i+1th row, and the row bit of each judging circuit of the Nth row The input system is electrically connected to the row bit line of the Nth row, and the second row bit input of each of the determining circuits of the Nth row receives a low level signal, where i is a positive integer greater than 0. And i=1, 2, ..., N, each of which The current switch circuit of the current unit further has a switch signal input port, and the switch signal input of the current switch circuit is electrically connected to the switch signal output port. According to the digital analog converter of claim 10, wherein the judging circuit of each current unit comprises a gate and a gate, and the input terminals of the gate are respectively the column bit input and the When the row bit is input, one of the output terminals of the gate is connected to one of the input terminals of the gate, and the other input of the gate is the row bit input port, and one of the outputs of the gate is The switching signal output 埠. A digital analog converter according to the first aspect of the patent application, wherein the decoding program is a thermometer decoder. A clock controller includes: a clock signal input port, a first signal input port, a second signal input port, and a variable clock signal output port, wherein the clock signal input port is configured to receive a clock signal, The clock controller determines the signal received by the first signal input port and the second signal input port. If the signal of the first signal input port and the second signal input port are the same, the variable clock signal output is According to the received clock signal, the output has only one clock pulse, and if the signal of the first signal input and the second signal input is different, the time signal output is changed. The system outputs the variable clock signal having a continuous clock cycle according to the received clock signal. According to the clock controller of claim 13, wherein each of the clock controllers comprises a line of signal judging circuit, an inverter and a variable clock switch circuit, wherein the three input terminals of the signal judging circuit are The first signal input port, the second signal input port, and the time pulse signal input port, the output end of the signal judging circuit is electrically connected to one of the control terminals of the variable clock switch circuit, and one of the input terminals of the inverter is For the clock signal input port, one of the output terminals of the inverter is electrically connected to one input end of the variable clock switch circuit, and one of the output terminals of the variable clock switch circuit is the variable clock signal output. port. According to the clock controller of claim 14, wherein the signal judging circuit comprises a peer judging circuit, a row judging circuit, a double row judging switch and a total judging circuit, and the second input end of the peer judging circuit The first signal input is the first pulse input signal, and the second input end of the second circuit is the second signal input, the time pulse signal input port, and the input end of the two-line determination switch is The first signal input port, the second control terminal of the two-line determination switch is the second signal input port, and the peer determination circuit, the second line determination circuit and the double line determination switch respectively have an output end, and each of the output ends They are electrically connected to the three input ends of the total judgment circuit, and an output end of the total judgment circuit is an output end of the signal judgment circuit. According to the clock controller of claim 15, wherein the peer judgment circuit includes a register and a mutual exclusion gate, and the input terminals of the register are the clock signal input and the The first signal input port is electrically connected to one of the mutex or gate inputs, and the other input end of the mutex or gate is the first signal input port, the mutual One of the outputs of the repulsion or gate is the output of the peer judgment circuit. According to the clock controller of claim 15, wherein the second determining circuit comprises a register and a mutually exclusive switch, and the input terminals of the register are respectively the clock signal input and The second signal input port is electrically connected to one of the mutex or gate inputs, and the other input end of the mutex or gate is the second signal input port. One of the mutually exclusive or gate outputs is the output of the line determination circuit. According to the clock controller of claim 15, wherein the two-line determination relationship is a CMOS switch, and when the two control terminals of the two-line determination switch receive a low level signal, the two-line determination switch is enabled. The output end outputs the signal received by the first signal input port; when the second control end of the two-line determination switch receives a high level signal, the output end of the two-line determination switch outputs a low level signal. According to the clock controller of claim 15th, wherein the total judgment circuit is a sluice gate, the three input terminals of the sluice gate are respectively electrically connected to the output terminals of the peer judging circuit, the second row judging circuit and the double row judging switch, and the output end of the sluice gate is the output end of the signal judging circuit. After receiving the signal of the peer judgment circuit, the second row judgment circuit and the output of the two-line judgment switch, the OR gate performs a logic judgment, and outputs a judgment signal to the output end of the signal judgment circuit, and the output end of the OR gate The system includes a forward output 埠 and a reverse output 埠. The forward output 直接 directly outputs the determination signal, and the reverse output 输出 outputs the complementary determination signal. The clock controller according to claim 19, wherein the variable clock switch circuit is a CMOS switch, and the control end of the variable clock switch circuit includes a first control port and a second control port. The first control is electrically connected to the positive output of the total determining circuit, and the second control is electrically connected to the reverse output of the total determining circuit, when the first control of the time varying switching circuit is received from the positive direction When the high level signal of the output is received, and the second control unit receives the low level signal from the reverse output, the output of the variable clock switch circuit outputs the clock signal passing through the inverter. The clock controller according to claim 20, further comprising a protection circuit, wherein the protection circuit is a transistor, and one of the protection circuits is electrically connected to the output end of the variable clock switch circuit. A gate of the protection circuit is electrically connected to the second control port of the variable clock switch circuit, and one source of the protection circuit is connected to a ground.