CN109346116A - The output self-regulation circuit of the anti-SSO of SRAM - Google Patents
The output self-regulation circuit of the anti-SSO of SRAM Download PDFInfo
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- CN109346116A CN109346116A CN201811060347.XA CN201811060347A CN109346116A CN 109346116 A CN109346116 A CN 109346116A CN 201811060347 A CN201811060347 A CN 201811060347A CN 109346116 A CN109346116 A CN 109346116A
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
- G11C11/4125—Cells incorporating circuit means for protecting against loss of information
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Abstract
Whether the present invention relates to a kind of output of the anti-SSO of SRAM self-regulation circuits, be related to IC design field, including n output data induction module, be flipped for detecting SRAM output data D [n-1,0] relative to a upper clock status；Overturn counting module, the n Data flipping for receiving the n output data induction module outputs determines signal D [i] _ sensor, and signal D [i] _ sensor, which carries out operation, to be determined to the n Data flipping, obtain corresponding and signal and carry signal；Logic coding module, to the overturning counting module provide described in and signal and the carry signal encode, provide the control signal S [i] (0≤i≤z-1) of different delayed time gear, wherein z is the integer more than or equal to 1；And delays time to control module, different delay gears is controlled by the control signal S [i] (0≤i≤z-1) that the logic coding module provides, so that the data time sequence output overturn simultaneously, can readjust automatically while overturn the output timing of output data.
Description
Technical field
The present invention relates to the output of IC design field more particularly to a kind of anti-SSO of SRAM self-regulation circuits.
Background technique
In IC design field, static random access memory (Static Random-Access Memory,
It SRAM is) common device.
However, current SRAM is there are multiple IO, overturning output causes high current simultaneously, and then causes biggish resistance pressure
The problem of dropping (IR Drop).Industry commonly prevents that overturning output (SSO) circuit simultaneously sees Fig. 1 at present, and Fig. 1 is existing skill
The anti-SSO circuit diagram of art.As shown in Figure 1, delay control signal S in the prior art is controlled by outside, pass through S control
Switch determines whether the output data of half is delayed output.Being controlled first is that controlling signal by outside for the defect of such way, it is difficult
It is accurately controlled with realizing, is unfavorable for avoiding SSO in time；Defect second is that delay output data section only one, if prolonging
When export the interval censored data can not solve SSO bring influence, then the circuit also fails therewith, is unfavorable for targetedly avoiding
SSO。
How effectively to prevent while overturn output (SSO) in SRAM, becomes industry urgent problem to be solved.
Summary of the invention
Purpose of the present invention is to provide a kind of output of the anti-SSO of SRAM self-regulation circuits, including n output data induction
Whether module is flipped for detecting SRAM output data D [n-1,0] relative to a upper clock status, wherein n be greater than etc.
In 4 integer, exports n Data flipping and determine signal D [i] _ sensor (0≤i≤n-1)；Counting module is overturn, receives n
The n Data flipping of the output data induction module output determines signal D [i] _ sensor, and to the n data
Overturning determines that signal D [i] _ sensor carries out operation, obtains corresponding and signal (J_S [x-1:0]) and carry signal (J_C
[y-1:0])；Logic coding module, to the overturning counting module provide described in and signal (J_S [x-1:0]) and it is described into
Position signal (J_C [y-1:0]) is encoded, and provides the control signal S [i] (0≤i≤z-1) of different delayed time gear, wherein z is
Integer more than or equal to 1；And delays time to control module, the control signal S [i] (0 provided by the logic coding module
≤ i≤z-1) the different delay gear of control, so that the data time sequence output overturn simultaneously.
Further, each output data induction module includes the trigger of two clock controls, one of them
Trigger data input be another trigger data export, the output of two triggers respectively represent data D [i] (0≤
I≤n-1) state in two adjacent clocks.
Further, each output data induction module further includes at least one combinational logic gate, to data D
[i] (0≤i≤n-1) output data in two adjacent clocks carries out logical operation to determine whether D [i] is flipped,
The output level when level that combinational logic gate exports when being flipped is different from not being flipped, obtains the n Data flipping
Determine signal D [i] _ sensor (0≤i≤n-1).
Further, the combinational logic gate is XOR gate, to data D [i] (0≤i≤n-1) in two adjacent clocks
Interior output data does xor operation, for the input data being flipped, the Data flipping of the output of the XOR gate
Determine that signal (D [i] _ sensor, 0≤i≤n-1) is high level, otherwise is low level.
Further, multiple output data induction modules are multiple identical output data induction modules.
Further, the overturning counting module includes at least one adder, and the n Data flipping determines signal
D [i] _ sensor is added by the adder, to obtain described and signal (J_S [x-1:0]) and the carry signal (J_
C[y-1:0])。
Further, the overturning counting module receives the n number of the n output data induction module output
Signal D [i] _ sensor is determined according to overturning, and signal D [i] _ sensor, which carries out operation, to be determined to the n Data flipping, it must
The number for the data being flipped into the n data.
Further, the logic coding module includes at least one combinational logic gate, for described and signal (J_
S [x-1:0]) and the carry signal (J_C [y-1:0]) encoded, thus generate z data interval of control be delayed it is described
It controls signal S [i] (0≤i≤z-1).
Further, the delays time to control module includes delay circuit and transmission gate circuit, and the delay circuit includes
The time delay module of multiple constant time lags；The transmission gate circuit includes multiple switch unit, and each delay data section is all connected with
To two branches: the first branch is switch unit and the concatenated cascaded structure of time delay module, and second branch is a switch unit, should
Whether the data in data interval are delayed controls institute by control signal S [i] (0≤i≤z-1) and S [i] ' (0≤i≤z-1) respectively
The switch unit stated in the first branch and the second branch determines, when control signal S [i] (0≤i≤z-1) controls institute
When stating the switching means conductive of the first branch, delay data section delay；When control signal S [i] ' (0≤i≤z-1)
When controlling the switching means conductive of the second branch, which is not delayed.
Further, each control signal S [i] (0≤i≤z-1) and S [i] ' (0≤i≤z-1) control one
Corresponding data interval, each delay data section include at least one data.
Further, the time delay module is made of at least one phase inverter.
Further, the delays time to control scheme of the delays time to control module is directly by the data of overturning simultaneously by ideal
Data interval divide equally, each control signal S [i] (0≤i≤z-1) individually delay of one data interval of control or is led
It is logical, to provide different delay gears for each data interval.
Further, the delays time to control scheme of the delays time to control module is to divide the data of overturning simultaneously directly step by step
To ideal final stage data interval, the time delay module that every grade of data interval is chosen is identical, each control signal S [i] (0
≤ i≤z-1) individually control one data interval delay or conducting, by the combination between delay and conducting step by step, to be
Each final stage data interval provides different delay gears.
Further, the summation of the big delay of every grade of time delay module later of the delay of first order time delay module.
In an embodiment of the present invention, by including n output data induction module, overturning counting module, logic coding
The output self-regulation circuit of the anti-SSO of module and delays time to control module, can readjust automatically while overturn the defeated of output data
Timing out, reduce because multiple IO simultaneously overturn output caused by high current, to avoid IR Drop.
Detailed description of the invention
Fig. 1 is the anti-SSO circuit diagram of the prior art.
The output self-regulation circuit diagram that Fig. 2 is the anti-SSO of one embodiment of the invention.
Fig. 3 is the schematic diagram of output data induction module in one embodiment of the invention.
Fig. 4 is the structural schematic diagram of the overturning counting module of one embodiment of the invention.
Fig. 5 is the structural schematic diagram of the logic coding module of one embodiment of the invention.
Fig. 6 is the delay encryption algorithm schematic diagram of one embodiment of the invention.
Fig. 7 is the delays time to control scheme schematic diagram of the delays time to control module of one embodiment of the invention.
Fig. 8 is the delays time to control scheme schematic diagram of the delays time to control module of another embodiment of the present invention.
Fig. 9 is the working waveform figure using the output self-regulation circuit of the anti-SSO of SRAM provided by the invention.
Figure 10 is the working waveform figure using the output self-regulation circuit of the anti-SSO of SRAM provided by the invention.
The reference numerals are as follows for main element in figure:
100, output data induction module；200, counting module is overturn；300, logic coding module；400, delays time to control mould
Block.
Specific embodiment
Below in conjunction with attached drawing, clear, complete description is carried out to the technical solution in the present invention, it is clear that described
Embodiment is a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is general
Logical technical staff's all other embodiment obtained under the premise of not making creative work belongs to what the present invention protected
Range.
In one embodiment of the invention, it is to provide the output self-regulation circuit of anti-SSO of SRAM a kind of, to reduce because of multiple IO
High current caused by output is overturn simultaneously, to avoid IR Drop.Specifically, referring to Fig. 2, Fig. 2 is one embodiment of the invention
Anti- SSO output be self-regulated circuit diagram.As shown in Fig. 2, the output of the anti-SSO of the SRAM provided in one embodiment of the invention
The circuit that is self-regulated includes: n output data induction module 100 (n sensor), for detecting SRAM output data D [n-1,0]
Whether it is flipped relative to a upper clock status, wherein n is the integer more than or equal to 4, exports n Data flipping and determines signal
D[i]_sensor(0≦i≦n-1)；It overturns counting module 200 (REVERSAL COUNTING), receives n output data induction
The n Data flipping that module 100 exports determines signal D [i] _ sensor, and to n Data flipping judgement signal D [i] _
Sensor carries out operation, obtains corresponding and (S) signal (J_S [x-1:0]) and carry (CO) signal (J_C [y-1:0]),
Middle x, y are the integer more than or equal to 1；Logic coding module 300 (LOGIC CODING) provides overturning counting module 200
And (S) signal (J_S [x-1:0]) and carry (CO) signal (J_C [y-1:0]) encoded, different delayed time gear is provided
It controls signal S [i] (0≤i≤z-1), wherein z is the integer more than or equal to 1；400 (DELAY of delays time to control module
CONTROL), different delay gears is controlled by the control signal S [i] (0≤i≤z-1) that logic coding module 300 provides,
So that the data time sequence output overturn simultaneously.
Specifically, referring to Fig. 3, Fig. 3 is the schematic diagram of output data induction module in one embodiment of the invention.Such as Fig. 3
Shown, each output data induction module 100 includes the trigger 110 of two clock controls, the number of one of trigger 110
(Q0) is exported according to the data that input is another trigger 110, the output (Q0, Q1) of two triggers 110 respectively represents data D
The state of [i] (0≤i≤n-1) in two adjacent clocks.Further, each output data induction module 100 further includes
At least one combinational logic gate carries out output data (Q0, Q1) of the data D [i] (0≤i≤n-1) in two adjacent clocks
Logical operation determines whether D [i] is flipped, and the level that combinational logic gate exports when being flipped is different from not turning over
Output level when turning obtains n Data flipping and determines signal D [i] _ sensor (0≤i≤n-1), and n Data flipping determines letter
Number D [i] _ sensor (0≤i≤n-1) is sent to overturning counting module 200.
Specifically, referring to Fig. 3, the combinational logic gate is XOR gate 120, to data D [i] (0≤i≤n-1) two
Output data (Q0, Q1) in a adjacent clock does xor operation, for the input data being flipped, XOR gate 120 it is defeated
Data flipping out determines that signal (D [i] _ sensor, 0≤i≤n-1) is high level, otherwise is low level, so detects
Whether the output data of SRAM is flipped.Certainly, in an embodiment of the present invention, each output induction module is not limited
Specific structure, as long as the signal that the output signal of output induction module is exported when the output data of SRAM is flipped is different
In the output data signal that there is no exporting when overturning of SRAM, whether the output data that can be detected SRAM is flipped.
More specifically, in an embodiment of the present invention, multiple output data induction modules 100 are multiple identical output numbers
According to induction module 100.Each output data induction module 100 receives output data D [i], the 0≤i≤n-1 of a SRAM, output
The Data flipping whether corresponding output data D [i] of one characterization is flipped determines signal (D [i] _ sensor, 0≤i≤n-
1)。
Referring to Fig. 2, overturning counting module 200 (REVERSAL COUNTING), receives n output data induction module
N Data flippings of 100 outputs determine signal D [i] _ sensor, and to n Data flipping judgement signal D [i] _ sensor into
Row operation obtains corresponding and (S) signal (J_S [x-1:0]) and carry (CO) signal (J_C [y-1:0]).Specifically, can
Refering to the structural schematic diagram for the overturning counting module that Fig. 4, Fig. 4 are one embodiment of the invention, as shown in figure 4, overturning counting module
200 include at least one adder, n Data flipping determine signal D [i] _ sensor by adder addition, thus obtain with
(S) signal (J_S [x-1:0]) and carry (CO) signal (J_C [y-1:0]).
As in an embodiment, when circuit work, output induction module detects 16 output signals relative to upper simultaneously
Whether one clock status is flipped, and exports as D [15:0] _ sensor；Overturn counting module 200 by adder by D [15:
0] _ sensor be added, provide and (S), carry (CO) signal implementation are as follows: by 81 adders to 16 data into
Row first round addition obtains 8 groups of 2 outputs S0, CO；The second wheel addition is carried out to 8 groups of 2 data by 42 adders to obtain
To 4 groups of 3 outputs S0, S1, CO；Third round addition is carried out to 4 groups of 3 data by 23 adders and obtains 2 groups of 4 outputs
S0,S1,S2,CO；Fourth round addition, which is carried out, by 14 adder obtains 1 group of 5 outputs S0, S1, S2, S3, CO.It uses simultaneously
8 S0 that similar mode obtains the first round are added, and finally obtain 1 group of 4 outputs S0, S1, S2, CO.
Further, in an embodiment of the present invention, overturning counting module 200 (REVERSAL COUNTING) receives n
The n Data flipping that a output data induction module 100 exports determines signal D [i] _ sensor, and determines n Data flipping
Signal D [i] _ sensor carries out operation, also obtains the number for the data being flipped in n data.Wherein, counting module is overturn
The output of middle afterbody adder is just the number of the data of overturning.
Referring to Fig. 2, logic coding module 300 (LOGIC CODING), providing overturning counting module 200 and (S)
Signal (J_S [x-1:0]) and carry (CO) signal (J_C [y-1:0]) are encoded, and the control signal of different delayed time gear is provided
S [i] (0≤i≤z-1), wherein z is the integer more than or equal to 1.Specifically, seeing Fig. 5, Fig. 5 is one embodiment of the invention
The structural schematic diagram of logic coding module, as shown in figure 5, logic coding module 300 (LOGIC CODING) includes at least one
Combinational logic gate, for being encoded to J_S [x-1:0], J_C [y-1:0], to generate z data interval delay of control
It controls signal S [i] (0≤i≤z-1).The J_S [x-1:0] specifically used is right depending on J_C [y-1:0] is by delay encryption algorithm
Signal J_S [x-1:0], J_C [y-1:0] are encoded to obtain the delay control signal S [z-1,0] of data interval.In the present invention
In one embodiment, referring to Fig. 6, Fig. 6 is the delay encryption algorithm schematic diagram of one embodiment of the invention, delay as shown in FIG. 6
Encryption algorithm encodes corresponding and (S), carry (CO) signal, obtains 3 delay control signal S [2:0].
Referring to Fig. 2, delays time to control module 400 (DELAY CONTROL), the control provided by logic coding module 300
Signal S [i] (0≤i≤z-1) processed controls different delay gears, so that the data time sequence output overturn simultaneously.So make simultaneously
The output data of overturning is finally delayed with the timing of different stalls and is exported, to avoid the generation of SSO.
Specifically, in an embodiment of the present invention, seeing Fig. 7, Fig. 7 is the delays time to control module of one embodiment of the invention
Delays time to control scheme schematic diagram.As shown in fig. 7, it is that will directly turn over simultaneously that the delays time to control scheme of delays time to control module 400, which is,
The data turned are divided equally by ideal data interval, and each control signal S [i] (0≤i≤z-1) individually controls a data interval
Delay or conducting, to provide different delay gears for each data interval.Wherein, the ideal data interval is
Designer thinks data interval to be achieved.
Specifically, in an alternative embodiment of the invention, seeing Fig. 8, Fig. 8 is the delays time to control of another embodiment of the present invention
The delays time to control scheme schematic diagram of module.As shown in figure 8, can also be will be same for the delays time to control scheme of delays time to control module 400
When the data that overturn divide step by step (such as: being divided into two, two points are four ...) until ideal final stage data interval, every grade of data
The time delay module that section is chosen is identical, and each control signal S [i] (0≤i≤z-1) individually controls the delay of a data interval
Or conducting, by the combination between delay and conducting step by step, to provide different delay gears for each final stage data interval.
In an embodiment of the present invention, the summation of the big delay of every grade of time delay module later of the delay of first order time delay module.Wherein,
The ideal final stage data interval is that designer thinks final stage data interval to be achieved.
Specifically, seeing Fig. 7 and Fig. 8, delays time to control module 400 includes delay circuit and transmission gate circuit, delay electricity
Road includes the time delay module 410 of multiple constant time lags；Transmission gate circuit includes multiple switch unit, and each delay data section is equal
Be connected to two branches: the first branch is switch unit and time delay module 410 (Delay Block) concatenated cascaded structure, the
Two branches are a switch unit, and whether the data in the data interval are delayed by S [i] (0≤i≤z-1) and S [i] ' (0≤i≤
Z-1) switch unit respectively in the control first branch and second branch determines, wherein S [i] ' (0≤i≤z-1) is to signal S
The signal that [i] (0≤i≤z-1) is negated.Specifically, when the switch unit of S [i] (0≤i≤z-1) control first branch is led
When logical, delay data section delay；As S [i] ' (0≤i≤z-1) control second branch switching means conductive when, the delay
Data interval is not delayed.In an embodiment of the present invention, each control signal S [i] (0≤i≤z-1) and S [i] ' (0≤i≤z-
1) a corresponding data interval is controlled, each delay data section includes at least one data.In an embodiment of the present invention,
Time delay module 410 is made of at least one phase inverter.
By taking 16 outputs ([16Data]) as an example, using delays time to control scheme as shown in Figure 8, first 16 outputs are divided
Contain the data interval ([8Data]) of 8 data respectively for two groups, the corresponding delay of time delay module 410 is 20n；Then respectively by 8
Data are again divided into two groups of data intervals ([4Data]) for containing 4 data respectively, and the delay of corresponding time delay module 410 is
10n.4 delay gears of 4 groups [4Data]: 0n, 10n, 20n, 30n are realized by 3 delay control signals.
Fig. 9 and Figure 10 are please referred to, Fig. 9 and Figure 10 are respectively to be self-regulated using the output of the anti-SSO of SRAM provided by the invention
The working waveform figure of circuit.As shown in figure 9, four adjacent datas form a data interval, successively increases four while overturning
Data, then the corresponding delay control signal S of the data interval is opened, so that the data delay in the section be made to export, is effectively kept away
SSO is exempted from.As shown in Figure 10, it is not overturn and D [2i] (0≤i≤7) is overturn one by one when D [2i+1] (0≤i≤7) are kept, whenever
When overturning simultaneously there are four data, corresponding delay control signal S is triggered unlatching to guarantee the data overturn simultaneously less than 4
It is a, to avoid SSO.
In this way, in an embodiment of the present invention, by including n output data induction module, overturning counting module, logic
The output self-regulation circuit of coding module and the anti-SSO of delays time to control module, can readjust automatically while overturn output data
Output timing, reduce because multiple IO simultaneously overturn output caused by high current, to avoid IR Drop.
Further, the delay timing of output data is to detect, automatically adjust automatically under current output, for
Overturning output data while different number, circuit can targetedly make corresponding data section rationally be delayed output, without
Outside carries out any additional operations, considerably increases the intelligence of circuit.
Particularly, with the increase of SRAM output data digit, since there are a large amount of outputs data bits, the prior art passes through
The method for increasing external signal control delay will become to be difficult to operate and realize further, and cause to be difficult to avoid that SSO, and the present invention can
With self-test, self-regulation while the output timing for overturning output data.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (14)
- The circuit 1. output of anti-SSO of SRAM a kind of is self-regulated characterized by comprisingWhether n output data induction module is sent out for detecting SRAM output data D [n-1,0] relative to a upper clock status Raw overturning, wherein n is the integer more than or equal to 4, exports n Data flipping and determines signal D [i] _ sensor (0≤i≤n-1)；Counting module is overturn, the n Data flipping for receiving the n output data induction module outputs determines signal D [i] _ sensor, and signal D [i] _ sensor, which carries out operation, to be determined to the n Data flipping, obtain corresponding and signal (J_S [x-1:0]) and carry signal (J_C [y-1:0]), wherein x, y are the integer more than or equal to 1；Logic coding module, to the overturning counting module provide described in and signal (J_S [x-1:0]) and the carry signal (J_C [y-1:0]) is encoded, and the control signal S [i] (0≤i≤z-1) of different delayed time gear is provided, wherein z be greater than etc. In 1 integer；AndDelays time to control module is controlled not by the control signal S [i] (0≤i≤z-1) that the logic coding module provides Same delay gear, so that the data time sequence output overturn simultaneously.
- The circuit 2. output of the anti-SSO of SRAM according to claim 1 is self-regulated, which is characterized in that each output number It include the trigger of two clock controls according to induction module, the data input of one of trigger is the number of another trigger According to output, the output of two triggers respectively represents state of the data D [i] (0≤i≤n-1) in two adjacent clocks.
- The circuit 3. output of the anti-SSO of SRAM according to claim 1 is self-regulated, which is characterized in that each output number It further include at least one combinational logic gate according to induction module, it is defeated in two adjacent clocks to data D [i] (0≤i≤n-1) Data carry out logical operation to determine whether D [i] is flipped out, and the level that combinational logic gate exports when being flipped is different Output level when not being flipped obtains the n Data flipping and determines signal D [i] _ sensor (0≤i≤n-1).
- The circuit 4. output of the anti-SSO of SRAM according to claim 3 is self-regulated, which is characterized in that the combinational logic gate For XOR gate, xor operation is done to output data of the data D [i] (0≤i≤n-1) in two adjacent clocks, for turning over The input data turned, the Data flipping of the output of the XOR gate determine that signal (D [i] _ sensor, 0≤i≤n-1) is equal For high level, on the contrary is low level.
- The circuit 5. output of the anti-SSO of SRAM according to claim 1 is self-regulated, which is characterized in that multiple output numbers It is multiple identical output data induction modules according to induction module.
- The circuit 6. output of the anti-SSO of SRAM according to claim 1 is self-regulated, which is characterized in that the overturning count module Block includes at least one adder, and the n Data flipping determines that signal D [i] _ sensor is added by the adder, from And obtain described and signal (J_S [x-1:0]) and the carry signal (J_C [y-1:0]).
- The circuit 7. output of the anti-SSO of SRAM according to claim 1 is self-regulated, which is characterized in that the overturning count module The n Data flipping that block receives the n output data induction module output determines signal D [i] _ sensor, and to institute It states n Data flipping and determines that signal D [i] _ sensor carries out operation, also obtain the data being flipped in the n data Number.
- The circuit 8. output of the anti-SSO of SRAM according to claim 1 is self-regulated, which is characterized in that the logic coding mould Block includes at least one combinational logic gate, for described and signal (J_S [x-1:0]) and the carry signal (J_C [y-1: 0] it) is encoded, to generate the control signal S [i] (0≤i≤z-1) of control z data interval delay.
- The circuit 9. output of the anti-SSO of SRAM according to claim 1 is self-regulated, which is characterized in that the delays time to control mould Block includes delay circuit and transmission gate circuit, and the delay circuit includes the time delay module of multiple constant time lags；The transmission gate Circuit includes multiple switch unit, and each delay data section is connected to two branches: the first branch is switch unit and prolong When block coupled in series cascaded structure, second branch is a switch unit, and whether the data in the data interval are delayed is believed by control Number S [i] (0≤i≤z-1) and S [i] ' (0≤i≤z-1) control respectively the first branch with it is described in the second branch Switch unit determines, when controlling the switching means conductive of signal S [i] (0≤i≤z-1) control first branch, is somebody's turn to do The delay of delay data section；When control signal S [i] ' (0≤i≤z-1) controls the switching means conductive of the second branch When, which is not delayed.
- The circuit 10. output of the anti-SSO of SRAM according to claim 9 is self-regulated, which is characterized in that each control letter Number S [i] (0≤i≤z-1) controls a corresponding data interval, each delay data section packet with S [i] ' (0≤i≤z-1) Containing at least one data.
- The circuit 11. output of the anti-SSO of SRAM according to claim 9 is self-regulated, which is characterized in that the time delay module by At least one phase inverter composition.
- The circuit 12. output of the anti-SSO of SRAM according to claim 9 is self-regulated, which is characterized in that the delays time to control mould The delays time to control scheme of block is that the data directly by overturning simultaneously are divided equally by ideal data interval, each control signal S [i] (0≤i≤z-1) individually controls the delay or conducting of a data interval, to provide different prolong for each data interval When gear.
- The circuit 13. output of the anti-SSO of SRAM according to claim 9 is self-regulated, which is characterized in that the delays time to control mould The delays time to control scheme of block is to divide the data of overturning simultaneously step by step until ideal final stage data interval, every grade of data field Between the time delay module chosen it is identical, individually one data interval of control prolongs for each control signal S [i] (0≤i≤z-1) When or conducting, by the combination between delay and conducting step by step, to provide different delay shelves for each final stage data interval Position.
- The circuit 14. output of the anti-SSO of SRAM according to claim 13 is self-regulated, which is characterized in that first order delay mould The summation of the big delay of every grade of time delay module later of the delay of block.
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