CN109326531B - Rewiring structure and method of manufacturing the same, and semiconductor device and method of manufacturing the same - Google Patents

Rewiring structure and method of manufacturing the same, and semiconductor device and method of manufacturing the same Download PDF

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CN109326531B
CN109326531B CN201811116166.4A CN201811116166A CN109326531B CN 109326531 B CN109326531 B CN 109326531B CN 201811116166 A CN201811116166 A CN 201811116166A CN 109326531 B CN109326531 B CN 109326531B
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pad
dielectric layer
metal layer
semiconductor device
rewiring
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CN109326531A (en
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吕凌剑
邵永军
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0392—Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions

Abstract

The invention provides a rewiring structure and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the rewiring structure comprises the following steps: firstly, forming a first dielectric layer on a substrate with a first bonding pad; then, forming a rewiring metal layer on a top surface of the first pad; and finally, forming a second dielectric layer on the rewiring metal layer and the first dielectric layer, wherein the second dielectric layer is provided with a plurality of openings respectively exposing the top surfaces of different positions of the rewiring metal layer, and the rewiring metal layer exposed at the bottom of each opening is used as a second bonding pad. The number of the bonding pads on the semiconductor device is increased, the positions of the bonding pads on the semiconductor device are diversified, each bonding pad on the semiconductor device has the same clock response, and the problem that a metal layer at the bottom of each bonding pad is cracked due to point measurement and welding on the same bonding pad is solved.

Description

Rewiring structure and method of manufacturing the same, and semiconductor device and method of manufacturing the same
Technical Field
The present invention relates to the field of integrated circuit manufacturing, and more particularly, to a rewiring structure and a method of manufacturing the rewiring structure, and a semiconductor device and a method of manufacturing the semiconductor device.
Background
In a production process of a semiconductor integrated circuit, it is generally necessary to form a bonding pad (pad) as an electrode using a conductive material such as aluminum (Al) or gold (Au) for connecting a semiconductor device (chip) to an external circuit or for test inspection. The general design requirement is that the bonding pads are regularly distributed around the semiconductor device (chip) to ensure the same distance from the center of the semiconductor device (chip), i.e. the same clock response. In actual manufacturing, the position of the bonding Pad (Pad) is limited by the position of the copper metal layer (including the copper interconnect line Cu line and the copper Pad Cu Pad) therebelow, for example, when the lower part of the copper Pad Cu Pad is located near the center of the semiconductor device (chip), the position of the part of the bonding Pad (Pad) is also located near the center of the semiconductor device (chip). Taking an aluminum Pad (Al Pad) as an example, specifically referring to fig. 1a and fig. 1b, fig. 1a is a schematic diagram of a location of a Pad on a conventional semiconductor device (chip), fig. 1b is a schematic diagram of a longitudinal cross section of the Pad on the conventional semiconductor device (chip) shown in fig. 1a, and as can be seen from fig. 1a and fig. 1b, a Cu Pad (M1 in fig. 1 b) is connected with the Al Pad (M2 in fig. 1 b) and located below the Al Pad, the Al Pad is not connected with the Al Pad, and the Cu Pad is connected with the Cu Pad through a Cu line (for example, the interconnect L1 in fig. 1a connects the Cu Pad P1 and the P2). A part of the Cu Pad (e.g., P1 in fig. 1 a) is regularly arranged on the periphery of the upper surface of the chip, which results in a corresponding part of the Al Pad (e.g., P3, P4 in fig. 1 a) being regularly arranged on the periphery of the upper surface of the chip; another portion of the Cu Pad (e.g., P2 in fig. 1 a) is arranged on the upper surface of the chip near the center of the chip, which results in another corresponding portion of the Al Pad (e.g., P5 in fig. 1 a) being arranged on the upper surface of the chip near the center of the chip, and it can be seen that the position of the Cu Pad on the chip defines the position of the Al Pad, thereby resulting in the limitation of the position of the Al Pad on the chip; meanwhile, as can be seen from fig. 1b, Cu Pad and Al Pad are in one-to-one correspondence. Thus, the design of existing bond pads (e.g., Al pads) leads to the following problems:
1. the same clock reaction cannot be achieved: achieving the same clock response requires ensuring that each bond Pad (e.g., Al Pad) above the copper metal layer on the chip reaches the same distance to the primary circuit on the chip (with the primary circuit in the middle of the chip), i.e., that all bond pads (e.g., Al pads) are regularly arranged on the periphery of the chip. However, the position of the Cu Pad in the copper metal layer limits the position of the bonding Pad (e.g., Al Pad) to achieve the above requirements, and thus the same clock reaction cannot be achieved.
2. Cu Pad cracking (crack): in addition, in the conventional chip package structure, only one bonding Pad (e.g., Al Pad) connected to one Cu Pad is disposed on the Cu Pad, and a probe (probe) and a bonding (bonding) process need to be performed on the bonding Pad (e.g., Al Pad) at the same time, so that a large compressive stress is generated, and the compressive stress easily causes cracking (crack) of the Cu Pad on the lower layer, thereby causing yield loss of the chip.
In order to solve the above problems, it is necessary to break the limitation of the position of the existing Cu Pad on the position of the bonding Pad (e.g., Al Pad), so that the number of bonding pads (e.g., Al pads) connected to the same Cu Pad is increased and the position of the bonding Pad (e.g., Al Pad) is more diversified. Therefore, how to increase the number of bonding pads (e.g., Al pads) connected to the same Cu Pad and to diversify the positions of the bonding pads (e.g., Al pads) is a problem to be solved.
Disclosure of Invention
The invention aims to provide a rewiring structure and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof, so as to increase the number of bonding pads on the semiconductor device and diversify the positions of the bonding pads, further enable each bonding pad on the semiconductor device to have the same clock reaction, and avoid the problem of cracking of a metal layer at the bottom of each bonding pad caused by point measurement and welding on the same bonding pad.
To achieve the above object, the present invention provides a method of manufacturing a rewiring structure, comprising:
providing a substrate with a first bonding pad;
forming a first dielectric layer on the substrate, wherein the first dielectric layer exposes a part of or the whole top surface of the first bonding pad;
forming a redistribution metal layer on a top surface of the first pad, the redistribution metal layer further extending onto a portion of the top surface of the first dielectric layer; and the number of the first and second groups,
and forming a second dielectric layer on the rewiring metal layer and the first dielectric layer, wherein the second dielectric layer is provided with a plurality of openings respectively exposing the top surfaces of different positions of the rewiring metal layer, the rewiring metal layer exposed at the bottom of each opening is used as a second bonding pad, and the rewiring metal layer is electrically contacted with the first bonding pad so that the second bonding pad is electrically connected with the first bonding pad.
Optionally, the redistribution metal layer includes interconnection lines connected to the second pads, and the number of the second pads connected to each interconnection line is greater than or equal to 2.
Optionally, the step of forming the first dielectric layer includes: firstly, depositing the first dielectric layer on the substrate, wherein the first bonding pad is completely buried in the deposited first dielectric layer; then, planarizing the top surface of the first dielectric layer by chemical mechanical polishing; and finally, etching the part of the first dielectric layer on the first bonding pad to expose the partial or whole top surface of the first bonding pad.
Optionally, the step of forming the redistribution metal layer includes: firstly, forming a metal layer on the first bonding pad and the first dielectric layer, wherein the metal layer completely buries the first dielectric layer and the first bonding pad; then, the metal layer is patterned by photolithography and etching to form the rewiring metal layer.
Optionally, the step of forming the second dielectric layer includes: firstly, depositing a second dielectric layer on the rewiring metal layer and the first dielectric layer; then, the second dielectric layer is etched on different positions of the rewiring metal layer to form a plurality of openings respectively exposing the top surfaces of the rewiring metal layer at different positions.
The present invention also provides a rewiring structure including:
the first dielectric layer is positioned on a substrate with a first bonding pad, and the first dielectric layer exposes part or all of the top surface of the first bonding pad;
a rewiring metal layer on a top surface of the first pad, the rewiring metal layer further extending onto a portion of the top surface of the first dielectric layer; and the number of the first and second groups,
and a second dielectric layer on the redistribution metal layer and the first dielectric layer, the second dielectric layer having a plurality of openings respectively exposing top surfaces of different positions of the redistribution metal layer, the redistribution metal layer exposed at the bottom of each opening serving as a second pad, the redistribution metal layer being in electrical contact with the first pad so that the second pad is electrically connected with the first pad.
Optionally, the redistribution metal layer includes interconnection lines connected to the second pads, and the number of the second pads connected to each interconnection line is greater than or equal to 2.
Optionally, the redistribution metal layer is made of any one or more of aluminum, gold, silver, nickel, and titanium; the first dielectric layer and the second dielectric layer are made of any one or more of silicon dioxide, silicon nitride, tetraethoxysilane, borosilicate glass, phosphosilicate glass and borophosphosilicate glass.
The present invention also provides a pad structure, comprising: the rewiring structure provided by the invention is positioned on the first bonding pad.
The present invention also provides a semiconductor device comprising: the substrate is provided with a first bonding pad, a metal interconnection structure, a third dielectric layer and the rewiring structure provided by the invention; the third dielectric layer is positioned on the bottom surface of the rewiring structure, the metal interconnection structure is formed in the third dielectric layer, and the top surface of the metal interconnection structure is electrically contacted with the bottom surface of the first bonding pad of the rewiring structure; the first pad also extends onto a portion of a top surface of the third dielectric layer.
The present invention also provides a method for manufacturing a semiconductor device, comprising: and welding is carried out on one second bonding pad of the rewiring structure provided by the invention, and meanwhile, point measurement is carried out on the other second bonding pad of the rewiring structure.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. according to the manufacturing method of the rewiring structure, the first dielectric layer, the rewiring metal layer and the second dielectric layer are sequentially formed on the substrate with the first bonding pad, and the second bonding pads connected with the first bonding pad are further formed, so that the number of the bonding pads is increased, the positions of the bonding pads are diversified, the same clock reaction of each bonding pad is realized, and the cracking of the metal layer at the bottom of the bonding pad caused by point measurement and welding on the same bonding pad is avoided.
2. The rewiring structure can form the second bonding pads through the first dielectric layer, the rewiring metal layer and the second dielectric layer in the rewiring structure, the number of the second bonding pads is increased compared with that of the original first bonding pads, the positions of the second bonding pads are more diversified, the same clock reaction of each bonding pad is realized, and the cracking of the metal layer at the bottom of each bonding pad caused by point measurement and welding on the same bonding pad is avoided.
3. According to the pad structure, due to the addition of the rewiring structure, a plurality of second pads can be formed on the original first pad, so that the number of the pads is increased, meanwhile, the positions of the pads are more diversified, each pad has the same clock response, the spot measurement and welding processes can be respectively operated on two pads which are connected with each other, and the problem of cracking of a metal layer at the bottom of the pad caused by operation on the same pad is avoided.
4. According to the semiconductor device, the rewiring structure is added, so that a plurality of new second bonding pads are formed on each original first bonding pad in the semiconductor device, the point measurement and welding processes can respectively operate on different bonding pads which are connected with each other, and the problem that a metal layer at the bottom of each bonding pad is cracked due to operation on the same bonding pad is solved; but the diversity of the location of the new pads also allows each pad on the semiconductor device to have the same clock reaction.
5. According to the manufacturing method of the semiconductor device, the problem of cracking of the bottom metal layer caused by point measurement and welding on the same second bonding pad is solved by welding on one second bonding pad of the rewiring structure and simultaneously performing point measurement on the other second bonding pad of the rewiring structure.
Drawings
FIG. 1a is a schematic diagram of the location of a bond pad on a prior art semiconductor device (chip);
FIG. 1b is a schematic longitudinal cross-sectional view of a bonding pad on the prior art semiconductor device (chip) shown in FIG. 1 a;
FIG. 2 is a flow chart of a method of manufacturing a rewiring structure in accordance with an embodiment of the present invention;
FIGS. 3a to 3g are schematic views of devices in the method of manufacturing the re-wiring structure shown in FIG. 2;
fig. 4 is a schematic diagram of the location of a pad on a semiconductor device (chip) according to an embodiment of the present invention.
Wherein the reference numerals of figures 1a to 4 are as follows:
p1, P2, M1-Cu Pad; P3-P5 and M2-Al Pad; P6-P10-second pad; l1, L2, L3-interconnect; 10-a substrate; 11-a first pad; 20-a first dielectric layer; 30-rerouting the metal layer; 40-a second dielectric layer; 50-a second pad; T1-T4-groove.
Detailed Description
To make the objects, advantages and features of the present invention more apparent, the rewiring structure and the method of manufacturing the rewiring structure, and the semiconductor device and the method of manufacturing the semiconductor device according to the present invention will be described in further detail with reference to fig. 2 to 4. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides a method for manufacturing a rewiring structure, and referring to fig. 2, fig. 2 is a flowchart of a method for manufacturing a rewiring structure according to an embodiment of the present invention, where the method for manufacturing a rewiring structure includes:
step S2-A, providing a substrate with a first bonding pad, and forming a first dielectric layer on the substrate, wherein the first dielectric layer exposes a part or all of the top surface of the first bonding pad;
step S2-B, forming a redistribution metal layer on the top surface of the first pad, wherein the redistribution metal layer also extends to part of the top surface of the first dielectric layer;
and step S2-C, forming a second dielectric layer on the redistribution metal layer and the first dielectric layer, where the second dielectric layer has a plurality of openings respectively exposing top surfaces of different positions of the redistribution metal layer, the redistribution metal layer exposed at the bottom of each opening serves as a second pad, and the redistribution metal layer is in electrical contact with the first pad, so that the second pad is electrically connected with the first pad.
The method for manufacturing the redistribution structure according to the present embodiment will be described in more detail with reference to fig. 3a to 3g, and fig. 3a to 3g are schematic device diagrams in the method for manufacturing the redistribution structure shown in fig. 2.
First, referring to fig. 3a to 3c, according to step S2-a, a substrate 10 having a first pad 11 is provided, and a first dielectric layer 20 is formed on the substrate 10, wherein the first dielectric layer 20 exposes a portion or all of a top surface of the first pad 11. As can be seen from fig. 3a, the first pad 11 may be partially located in the substrate 10, and another portion is located on the top surface of the substrate 10, and a groove T1 may be present in the first pad 11 located on the top surface of the substrate 10. In addition, the top surface of the first pad 11 may be a flat surface or a convex circular arc surface. As can be seen from fig. 3b and 3c, when the groove T1 exists in the first pad 11, the step of forming the first dielectric layer 20 includes: firstly, depositing the first dielectric layer 20 on the substrate 10, and the first dielectric layer 20 completely burying the first pad 11 (as shown in fig. 3 b); then, planarizing the top surface of the first dielectric layer 20 by chemical mechanical polishing; finally, the part of the first dielectric layer 20 on the first pad 11 is etched to expose part or all of the top surface of the first pad 11 (see fig. 3 c). In addition, other metal layers and dielectric layers, such as copper (Cu) metal layers and Tetraethylorthosilicate (TEOS) dielectric layers, may also be included in the substrate 10.
Then, referring to fig. 3d and 3e, according to step S2-B, a redistribution metal layer 30 is formed on the top surface of the first pad 11, wherein the redistribution metal layer 30 further extends to a portion of the top surface of the first dielectric layer 20. As can be seen from fig. 3d and 3e, the step of forming the redistribution metal layer 30 includes: firstly, forming a metal layer on the first pad 11 and the first dielectric layer 20, wherein the metal layer completely buries the first dielectric layer 20 and the first pad 11 therein, and the metal layer can be formed by sputtering deposition; then, the metal layer is patterned by photolithography and etching to form the rewiring metal layer 30. Since the first dielectric layer 20 formed in step S2-a exposes a part or all of the top surface of the first pad 11, a groove T2 is formed on the top surface of the first pad 11 within the first dielectric layer 20, and then, when the metal layer is formed on the top surface of the first pad 11 and the top surface of the first dielectric layer 20, the thickness of the metal layer on the first pad 11 may be the same as that of the metal layer on the top surface of the first dielectric layer 20, thereby forming a groove T3 in the metal layer above the first pad 11; when patterning the metal layer by photolithography and etching, the recess T3 may be left while another recess or recesses, such as recess T4 in fig. 3e, are etched in the metal layer on a portion of the top surface of the first dielectric layer 20. Alternatively, the deposition time on the first pad 11 may be prolonged so that the metal layer on the top surface of the first pad 11 and the top surface of the first dielectric layer 20 are flush, i.e. a plane is formed, and then 2 or more than 2 grooves are formed in the metal layer simultaneously by photolithography and etching. In addition, in order to ensure that the grooves can be connected and conducted, the redistribution metal layer 30 further includes interconnection lines, such as the interconnection lines L2 and L3 in fig. 4.
Finally, referring to fig. 3f and 3g, according to step S2-C, a second dielectric layer 40 is formed on the redistribution metal layer 30 and the first dielectric layer 20, the second dielectric layer 40 has a plurality of openings respectively exposing top surfaces of different positions of the redistribution metal layer 30, the redistribution metal layer 30 exposed at the bottom of each opening serves as a second pad 50, and the redistribution metal layer 30 is electrically contacted with the first pad 11, so that the second pad 50 is electrically connected with the first pad 11. As can be seen in fig. 3f and 3g, the step of forming the second dielectric layer 40 includes: firstly, depositing a second dielectric layer 40 on the redistribution metal layer 30 and the first dielectric layer 20; then, portions of the second dielectric layer 40 located at different positions of the redistribution metal layer 30 are etched to form a plurality of openings respectively exposing top surfaces of the redistribution metal layer 30 at different positions. The redistribution metal layer 30 includes interconnection lines connected to the second pads 50, and the number of the second pads 50 connected to each interconnection line is 2 or more. The second pad 50 is in direct electrical contact with the first pad 11, or the interconnection line is in direct electrical contact with the first pad 11, so that the second pad 50 is electrically connected with the first pad 11, and the second pad 50 is electrically connected with the first pad 11. Since the second dielectric layer 40 is mainly used for protecting the redistribution metal layer 30, a certain thickness of the second dielectric layer 40 still remains on the sidewall of the groove of the redistribution metal layer 30 where the second pad 50 is located.
Referring to fig. 4, fig. 4 is a schematic diagram of the position of a Pad on a semiconductor device (chip) according to an embodiment of the present invention, and as can be seen from fig. 4, the second Pad 50 connected to the Al Pad (i.e., the first Pad 11 made of Al) P3 shown in fig. 1a is P6, and P6 is connected to P7 and P8 through an interconnection line L2; in addition, the second Pad 50 connected to the Al Pad (i.e., the first Pad 11 made of Al) P5 shown in fig. 1a is P9, and P9 is connected to P10 through an interconnection line L3. When the pads on the semiconductor device (chip) need to be subjected to spot measurement and welding, if the Pad design of the semiconductor device (chip) shown in fig. 1a is adopted, both the spot measurement and the welding are carried out on the P3, and the large compressive stress can cause the cracking of the Cu Pad M1 shown in fig. 1 b; however, if the design of the pad on the semiconductor device (chip) shown in fig. 4 is adopted, the dotting can be made on P6, and the soldering can be made on P7 or P8; solder connections can be made at P9 and point measurements made at P10 so that each Pad experiences less compressive stress and thus avoids cracking of the Cu Pad M1. In addition, due to the connection between P9 and P10, the P9 located near the center of the semiconductor device (chip) can also obtain the same clock reaction with other pads located at the periphery of the semiconductor device (chip) through the P10 located at the periphery of the semiconductor device (chip).
In summary, the manufacturing method of the redistribution structure provided by the invention includes: forming a first dielectric layer on a substrate with a first bonding pad, wherein the first dielectric layer exposes part or all of the top surface of the first bonding pad; forming a redistribution metal layer on a top surface of the first pad, the redistribution metal layer further extending onto a portion of the top surface of the first dielectric layer; and forming a second dielectric layer on the rewiring metal layer and the first dielectric layer, wherein the second dielectric layer is provided with a plurality of openings respectively exposing the top surfaces of different positions of the rewiring metal layer, the rewiring metal layer exposed at the bottom of each opening is used as a second bonding pad, and the rewiring metal layer is electrically contacted with the first bonding pad so that the second bonding pad is electrically connected with the first bonding pad. The manufacturing method of the rewiring structure provided by the invention has the advantages that the number of the bonding pads is increased, the positions of the bonding pads are diversified, the bonding pads on a semiconductor device (chip) can have the same clock reaction, and the cracking of a metal layer at the bottom of the bonding pad caused by point measurement and welding on the same bonding pad is avoided.
An embodiment of the present invention provides a rewiring structure, referring to fig. 3g, and as can be seen from fig. 3g, the rewiring structure includes: a first dielectric layer 20, a redistribution metal layer 30, and a second dielectric layer 40. The first dielectric layer 20 is located on a substrate 10 having a first bonding pad 11, and the first dielectric layer 20 exposes a part or all of the top surface of the first bonding pad 11; the redistribution layer 30 is located on the top surface of the first pad 11, and the redistribution layer 30 also extends to a part of the top surface of the first dielectric layer 20; and the second dielectric layer 40 is located on the redistribution layer 30 and the first dielectric layer 20, the second dielectric layer 40 has a plurality of openings respectively exposing top surfaces of different positions of the redistribution layer 30, the redistribution layer 30 exposed at the bottom of each opening serves as a second pad 50, and the redistribution layer 30 is in electrical contact with the first pad 11 so that the second pad 50 is electrically connected with the first pad 11.
The rewiring structure provided by this embodiment is described in more detail below with reference to fig. 3 g:
the first dielectric layer 20 is located on a substrate 10 having a first bonding pad 11, and the first dielectric layer 20 exposes a part or all of the first bonding pad 11The top surface of the portion. The first pad 11 may be partially located in the substrate 10 and another portion is located on the top surface of the substrate 10, and a groove T1 may be present in the first pad 11 located on the top surface of the substrate 10. In addition, the top surface of the first pad 11 may be a flat surface or a convex circular arc surface. The material of the first dielectric layer 20 may include silicon dioxide (SiO)2) Silicon nitride (Si)3N4) One or more of Tetraethylorthosilicate (TEOS), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and the thickness of the first dielectric layer 20 on the top surface of the first pad 11 may be set to be equal to
Figure BDA0001810627890000101
(for example, is
Figure BDA0001810627890000102
Etc.) the thickness of the first dielectric layer 20 on the substrate 10 may be
Figure BDA0001810627890000103
(for example, is
Figure BDA0001810627890000104
Figure BDA0001810627890000105
Etc.).
The redistribution metal layer 30 is located on the top surface of the first pad 11, and the redistribution metal layer 30 further extends to a part of the top surface of the first dielectric layer 20. The redistribution metal layer 30 further includes interconnection lines connected to the second pads 50, and the number of the second pads 50 connected to each interconnection line is 2 or more. The material of the redistribution metal layer 30 may include any one or more of aluminum (Al), gold (Au), silver (Ag), nickel (Ni), and titanium (Ti), and the thickness of the redistribution metal layer 30 may be
Figure BDA0001810627890000106
(for example, is
Figure BDA0001810627890000107
Etc.);
the second dielectric layer 40 is located on the redistribution metal layer 30 and the first dielectric layer 20, the second dielectric layer 40 has a plurality of openings respectively exposing top surfaces of different positions of the redistribution metal layer 30, the redistribution metal layer 30 exposed at the bottom of each opening serves as a second pad 50, and the redistribution metal layer 30 is in electrical contact with the first pad 11 so that the second pad 50 is electrically connected with the first pad 11. The redistribution metal layer 30 further includes interconnection lines connected to the second pads 50, and the number of the second pads 50 connected to each interconnection line is greater than or equal to 2, that is, the number of the second pads 50 connected to each first pad 11 is greater than or equal to 2. The material of the second dielectric layer 40 may include silicon dioxide (SiO)2) Silicon nitride (Si)3N4) One or more of Tetraethylorthosilicate (TEOS), borosilicate glass (BSG), phosphosilicate glass (PSG), and borophosphosilicate glass (BPSG), and the second dielectric layer 40 on the first dielectric layer 20 may have a thickness of
Figure BDA0001810627890000108
(for example, is
Figure BDA0001810627890000109
Figure BDA00018106278900001010
Etc.).
In summary, the redistribution structure provided by the present invention includes a first dielectric layer on a substrate having a first pad, wherein the first dielectric layer exposes a part or all of a top surface of the first pad; a rewiring metal layer on a top surface of the first pad, the rewiring metal layer also extending onto a portion of the top surface of the first dielectric layer; and a second dielectric layer on the redistribution metal layer and the first dielectric layer, the second dielectric layer having a plurality of openings respectively exposing top surfaces of different positions of the redistribution metal layer, the redistribution metal layer exposed at the bottom of each opening serving as a second pad, the redistribution metal layer being in electrical contact with the first pad so that the second pad is electrically connected with the first pad. The rewiring structure provided by the invention can form more than or equal to 2 new bonding pads on each original bonding pad, so that the number of the bonding pads is increased, the positions of the bonding pads are more diversified, the bonding pads on a semiconductor device (chip) can have the same clock reaction, and the cracking of a metal layer at the bottom of the bonding pad caused by point measurement and welding on the same bonding pad is avoided.
An embodiment of the present invention provides a pad structure, including: the rewiring structure provided by the invention is positioned on the first bonding pad. By adopting the rewiring structure, second bonding pads are formed on the first bonding pads, the number of the second bonding pads which are connected with each other and formed on each first bonding pad is more than or equal to 2, the connected second bonding pads can be simultaneously positioned on the periphery of a semiconductor device (chip) or partially positioned on the periphery of the semiconductor device (chip), and the other part of the second bonding pads is positioned on the position, close to the center, of the semiconductor device (chip) so as to realize that each bonding pad has the same clock reaction, and the connected second bonding pads can be partially used for point measurement and the other part of the second bonding pads is used for welding, so that the problem that a metal layer below the first bonding pad or the first bonding pad is cracked due to the point measurement and the welding on the same bonding pad is avoided.
An embodiment of the present invention provides a semiconductor device including: the substrate is provided with a first bonding pad, a metal interconnection structure, a third dielectric layer and the rewiring structure provided by the invention. The third dielectric layer is positioned on the bottom surface of the rewiring structure, the metal interconnection structure is formed in the third dielectric layer, and the top surface of the metal interconnection structure is electrically contacted with the bottom surface of the first bonding pad of the rewiring structure; the first pad further extends to the third dielectric layerOn the top surface. The material of the metal interconnection structure may include any one or more of copper (Cu), aluminum (Al), and cobalt (Co), and the material of the third dielectric layer may include silicon dioxide (SiO)2) Any one or more of Tetraethylorthosilicate (TEOS), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG). By adopting the rewiring structure, second pads are formed on the first pads and are connected with each other through the interconnecting wires, the number of the second pads connected with each interconnecting wire is more than or equal to 2, so that welding can be carried out on one second pad of the rewiring structure, and meanwhile point measurement is carried out on the other second pad of the rewiring structure, and the problem that the first pad or the metal interconnecting structure is cracked due to the fact that the point measurement and the welding are carried out on the same second pad is avoided; and the position of the second bonding pad is more diversified, so that the bonding pads on the semiconductor device have the same clock reaction.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, including: the second bonding pad of the rewiring structure provided by the invention is welded, and meanwhile, the point measurement is carried out on the other second bonding pad of the rewiring structure, so that the problem of cracking of the bottom metal layer caused by point measurement and welding on the same second bonding pad is solved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (11)

1. A method of manufacturing a rewiring structure, comprising:
providing a substrate with a first bonding pad;
forming a first dielectric layer on the substrate, wherein the first dielectric layer exposes a part of or the whole top surface of the first bonding pad;
forming a redistribution metal layer on a top surface of the first pad, the redistribution metal layer further extending onto a portion of the top surface of the first dielectric layer; and the number of the first and second groups,
forming a second dielectric layer on the redistribution metal layer and the first dielectric layer, wherein the second dielectric layer has a plurality of openings respectively exposing the top surfaces of different positions of the redistribution metal layer, the redistribution metal layer exposed at the bottom of each opening serves as a second pad, and the redistribution metal layer is electrically contacted with the first pad so that the second pad is electrically connected with the first pad; and, in the plurality of second pads electrically connected to each of the first pads, at least one of the second pads is located at the periphery of the semiconductor device, and all of the second pads located at the periphery of the semiconductor device are equally spaced from the center of the semiconductor device, and each of the second pads located near the center of the semiconductor device is connected to the corresponding second pad located at the periphery of the semiconductor device through an interconnection line in the rewired metal layer so that all of the second pads have the same clock reaction, and the center of the semiconductor device is formed with a main circuit of the semiconductor device.
2. The method of manufacturing a rewiring structure of claim 1, wherein the number of the second pads to which each interconnect line in the rewiring metal layer is connected is 2 or more.
3. The method of manufacturing a rewiring structure of claim 1, wherein the step of forming the first dielectric layer comprises: firstly, depositing the first dielectric layer on the substrate, wherein the first bonding pad is completely buried in the deposited first dielectric layer; then, planarizing the top surface of the first dielectric layer by chemical mechanical polishing; and finally, etching the part of the first dielectric layer on the first bonding pad to expose the partial or whole top surface of the first bonding pad.
4. The method of manufacturing a rewiring structure of claim 1 or 2, wherein the step of forming the rewiring metal layer includes: firstly, forming a metal layer on the first bonding pad and the first dielectric layer, wherein the metal layer completely buries the first dielectric layer and the first bonding pad; then, the metal layer is patterned by photolithography and etching to form the rewiring metal layer.
5. The method of manufacturing a rewiring structure of claim 1, wherein the step of forming the second dielectric layer comprises: firstly, depositing a second dielectric layer on the rewiring metal layer and the first dielectric layer; then, the second dielectric layer is etched on different positions of the rewiring metal layer to form a plurality of openings respectively exposing the top surfaces of the rewiring metal layer at different positions.
6. A rewiring structure comprising:
the first dielectric layer is positioned on a substrate with a first bonding pad, and the first dielectric layer exposes part or all of the top surface of the first bonding pad;
a rewiring metal layer on a top surface of the first pad, the rewiring metal layer further extending onto a portion of the top surface of the first dielectric layer; and the number of the first and second groups,
a second dielectric layer on the redistribution metal layer and the first dielectric layer, the second dielectric layer having a plurality of openings respectively exposing top surfaces of different positions of the redistribution metal layer, the redistribution metal layer exposed at the bottom of each opening serving as a second pad, the redistribution metal layer being in electrical contact with the first pad so that the second pad is electrically connected with the first pad; and, in the plurality of second pads electrically connected to each of the first pads, at least one of the second pads is located at the periphery of the semiconductor device, and all of the second pads located at the periphery of the semiconductor device are equally spaced from the center of the semiconductor device, and each of the second pads located near the center of the semiconductor device is connected to the corresponding second pad located at the periphery of the semiconductor device through an interconnection line in the rewired metal layer so that all of the second pads have the same clock reaction, and the center of the semiconductor device is formed with a main circuit of the semiconductor device.
7. The rerouting structure of claim 6 wherein the number of second pads to which each interconnect line in the rerouting metal layer is connected is 2 or greater.
8. The rewiring structure of claim 6 or 7, wherein said rewiring metal layer is made of a material including any one or more of aluminum, gold, silver, nickel, and titanium; the first dielectric layer and the second dielectric layer are made of any one or more of silicon dioxide, silicon nitride, tetraethoxysilane, borosilicate glass, phosphosilicate glass and borophosphosilicate glass.
9. A pad structure, comprising: a first pad and a re-routing structure as claimed in any one of claims 6 to 8, the re-routing structure being located on the first pad.
10. A semiconductor device, comprising: a substrate having a first pad, a metal interconnect structure, a third dielectric layer, and the rewiring structure of any one of claims 6-8; the third dielectric layer is positioned on the bottom surface of the rewiring structure, the metal interconnection structure is formed in the third dielectric layer, and the top surface of the metal interconnection structure is electrically contacted with the bottom surface of the first bonding pad of the rewiring structure; the first pad also extends onto a portion of a top surface of the third dielectric layer.
11. A method for manufacturing a semiconductor device according to claim 10, comprising: a bond is made to a second bond pad of the rewiring structure while a point test is made to another second bond pad of the rewiring structure.
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