CN109326531A - Rewiring structure and its manufacturing method and semiconductor devices and its manufacturing method - Google Patents
Rewiring structure and its manufacturing method and semiconductor devices and its manufacturing method Download PDFInfo
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- CN109326531A CN109326531A CN201811116166.4A CN201811116166A CN109326531A CN 109326531 A CN109326531 A CN 109326531A CN 201811116166 A CN201811116166 A CN 201811116166A CN 109326531 A CN109326531 A CN 109326531A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
- H01L2224/0392—Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0651—Function
- H01L2224/06515—Bonding areas having different functions
Abstract
The present invention provides a kind of rewiring structure and its manufacturing method and semiconductor devices and its manufacturing method, the manufacturing method of the rewiring structure includes: firstly, forming the first dielectric substance layer on a substrate with the first pad;Then, it is formed on the top surface of first pad and reroutes metal layer;Finally, the second dielectric substance layer is formed on the rewiring metal layer and first dielectric substance layer, second dielectric substance layer has the multiple openings for exposing the top surface for rerouting metal layer different location respectively, and the rewiring metal layer that each open bottom exposes is as second pad.Increased with the number of pads realized on semiconductor devices more diversified with position, so that each pad Clock reaction having the same on semiconductor devices, and avoid the problem that the metal layer cracking of the bottom of pad caused by doing a survey and welding on the same pad.
Description
Technical field
The present invention relates to IC manufacturing field, in particular to a kind of rewiring structure and its manufacturing method and partly lead
Body device and its manufacturing method.
Background technique
In the production technology of semiconductor integrated circuit, it usually needs using the material of the electric conductivity such as aluminium (Al) or golden (Au)
It forms landing pad (pad) and is used as electrode, be attached with external circuit or for semiconductor devices (chip) for testing
It checks.Being typically designed requirement is the surrounding that landing pad is regularly distributed on semiconductor devices (chip), is guaranteed apart from semiconductor device
The distance at part (chip) center is identical, i.e., Clock reaction is identical.And in actually manufacturing, the position of landing pad (Pad) will receive
The limitation of the position of copper metal layer (including copper interconnecting line Cu line and copper pad Cu Pad) below, such as when lower section
When part copper pad Cu Pad is positioned at the position at close semiconductor devices (chip) center, part landing pad will lead to
(Pad) it is also located close to the position at semiconductor devices (chip) center.By taking aluminum pad (Al Pad) as an example, referring specifically to Fig. 1 a
It is the schematic diagram of the position of pad on existing semiconductor devices (chip) with Fig. 1 b, Fig. 1 a, Fig. 1 b is existing half shown in Fig. 1 a
The longitudinal cross-section schematic diagram of pad on conductor device (chip), can be seen that from Fig. 1 a and Fig. 1 b, Cu Pad (M1 in Fig. 1 b)
It is connected with Al Pad (M2 in Fig. 1 b), and is located at the lower section of Al Pad, does not have interconnection line company between Al Pad and Al Pad
It connects, passes through Cu line connection (such as interconnection line L1 connection Cu Pad P1 and P2 in Fig. 1 a) between Cu Pad and Cu Pad.One
Part Cu Pad (such as P1 in Fig. 1 a) regular array in the periphery of chip upper surface, then will lead to corresponding a part of Al
Pad (such as P3, P4 in Fig. 1 a) regular array is in the periphery of chip upper surface;Another part Cu Pad (such as in Fig. 1 a
P2 it) is arranged in the position of the close chip center of chip upper surface, then will lead to corresponding another part Al Pad (such as Fig. 1 a
In P5) be arranged in chip upper surface close chip center position, it is seen then that the position restriction of the Cu pad on chip Al
The position of Pad, so as to cause the limitation of the position Al Pad on chip;Meanwhile as can be seen that Cu Pad and Al from 1b
Pad is one-to-one.Therefore, the design of existing landing pad (such as Al Pad) results in following problem:
1, it cannot achieve identical Clock reaction: realizing that identical Clock reaction needs to guarantee on the copper metal layer on chip
Each landing pad (such as Al Pad) of side reaches the distance of the main circuit (main circuit is in the centre of chip) on chip
It is identical, that is, need all landing pads (such as Al Pad) all regular arrays in the periphery of chip.But the Cu in copper metal layer
The position that the position of pad limits landing pad (such as Al Pad) cannot achieve requirements above, and then lead to not realize phase
Same Clock reaction.
2, Cu Pad cracks (crack): in addition, due in existing chip-packaging structure, being only arranged one on a Cu Pad
A landing pad (such as Al Pad) being attached thereto needs above while to do and to survey in the landing pad (such as Al Pad)
(probe) and (bonding) is welded, therefore biggish compression can be generated, which is easy to cause the Cu Pad of lower layer to open
(crack) is split, and then leads to the yield loss of chip.
In order to solve problem above, need to break position of the position to landing pad (such as Al Pad) of existing Cu Pad
Limitation caused by setting, so that the quantity for the landing pad (such as Al Pad) being connected with the same Cu Pad increases and makes
The position for obtaining landing pad (such as Al Pad) is more diversified.Therefore, how to connect with what the same Cu Pad was connected
The quantity for closing pad (such as Al Pad) increases and makes the position of landing pad (such as Al Pad) is more diversified to become
The problem of urgent need to resolve.
Summary of the invention
The purpose of the present invention is to provide a kind of rewiring structure and its manufacturing method and semiconductor devices and its manufactures
Method, increased with the number of pads realized on semiconductor devices it is more diversified with position so that on semiconductor devices
Each pad Clock reaction having the same, and avoid the bottom of pad caused by doing a survey and welding on the same pad
The problem of metal layer cracking in portion.
To achieve the above object, the present invention provides a kind of manufacturing methods of rewiring structure, comprising:
One substrate with the first pad is provided;
The first dielectric substance layer is formed on the substrate, first dielectric substance layer exposes the part of first pad
Or whole top surface;
It is formed and reroutes metal layer on the top surface of first pad, the rewiring metal layer also extends to described
On the portion top surface of first dielectric substance layer;And
The second dielectric substance layer is formed on the rewiring metal layer and first dielectric substance layer, second dielectric medium
Layer has the multiple openings for exposing the top surface for rerouting metal layer different location respectively, and each open bottom exposes
The rewiring metal layer as second pad, the rewiring metal layer and first pad are in electrical contact so that
Second pad is obtained to be electrically connected with first pad.
Optionally, the metal layer that reroutes includes the interconnection line for connecting second pad, each interconnection line connection
The quantity of second pad is more than or equal to 2.
Optionally, the step of forming first dielectric substance layer includes: firstly, deposition first dielectric substance layer is in described
On substrate, and in first pad is completely buried in by first dielectric substance layer deposited;Then, it is ground by chemical machinery
Mill planarizes the top surface of first dielectric substance layer;Finally, etching first dielectric substance layer is located at first pad
On part, the top surface of some or all of first pad is exposed.
Optionally, the step of forming the rewiring metal layer includes: firstly, forming a metal layer in first pad
On first dielectric substance layer, first dielectric substance layer and first pad are completely buried in interior by the metal layer;
Then, by lithography and etching by the metallic layer graphic, to form the rewiring metal layer.
Optionally, the step of forming second dielectric substance layer includes: firstly, the second dielectric substance layer of deposition is in the heavy cloth
On line metal layer and first dielectric substance layer;Then, it etches second dielectric substance layer and is located at the rewiring metal layer
Part on different location, to form the multiple openings for exposing the top surface for rerouting metal layer different location respectively.
The present invention also provides a kind of rewiring structures, comprising:
First dielectric substance layer, on a substrate with the first pad, first dielectric substance layer exposes described the
The top surface of some or all of one pad;
Metal layer is rerouted, on the top surface of first pad, the rewiring metal layer also extends to described
On the portion top surface of first dielectric substance layer;And
Second dielectric substance layer is located on the rewiring metal layer and first dielectric substance layer, second dielectric medium
Layer has the multiple openings for exposing the top surface for rerouting metal layer different location respectively, and each open bottom exposes
The rewiring metal layer as second pad, the rewiring metal layer and first pad are in electrical contact so that
Second pad is obtained to be electrically connected with first pad.
Optionally, the metal layer that reroutes includes the interconnection line for connecting second pad, each interconnection line connection
The quantity of second pad is more than or equal to 2.
Optionally, the material for rerouting metal layer includes that aluminium, gold, silver, nickel, titanium are any one or more of;It is described
The material of first dielectric substance layer and second dielectric substance layer include silica, silicon nitride, ethyl orthosilicate, Pyrex,
Phosphorosilicate glass, boron-phosphorosilicate glass are any one or more of.
The present invention also provides a kind of pad structures, comprising: the first pad and the rewiring knot provided by the invention
Structure, the rewiring structure are located on first pad.
The present invention also provides a kind of semiconductor devices, comprising: has the first pad, metal interconnection structure, third dielectric
The substrate of matter layer and the rewiring structure provided by the invention;The third dielectric substance layer is located at the rewiring structure
Bottom surface on, and the metal interconnection structure is formed in the third dielectric substance layer, and the top table of the metal interconnection structure
The bottom surface of first pad of face and the rewiring structure is in electrical contact;First pad also extends to the third dielectric
On the portion top surface of matter layer.
The present invention also provides a kind of manufacturing methods of semiconductor devices, comprising: in the cloth again provided by the invention
It is welded on one second pad of cable architecture, while making point on another second pad of the rewiring structure and surveying.
Compared with prior art, technical solution of the present invention has the advantages that
1, the manufacturing method of rewiring structure of the invention, can be by having on the substrate of the first pad successively one
Form the first dielectric substance layer, reroute metal layer and the second dielectric substance layer, so form connect with first pad it is more
A second pad, so that the quantity of pad increases and position is more diversified, to realize that each pad clock having the same is anti-
It answers, and avoids the cracking of pad bottom metal layers caused by doing a survey and welding on the same pad.
2, rewiring structure of the invention can pass through the first dielectric substance layer in the rewiring structure, rewiring
Metal layer and the second dielectric substance layer and form the second pad, second pad increases than the quantity of former first pad, and position
It is more diversified, each pad Clock reaction having the same is realized, and avoid and do a survey and weldering on the same pad
The cracking of pad bottom metal layers caused by connecing.
3, pad structure of the invention can be original due to joined rewiring structure of the invention
Multiple second pads are formed on one pad, and then the quantity of pad are increased, while the position of pad is more diversified, so that often
A pad Clock reaction having the same, and point is surveyed and welding procedure can distinguish operation on two pads interconnected,
The problem of avoiding the cracking of the pad bottom metal layers caused by operation on the same pad.
4, semiconductor devices of the invention is made in the semiconductor devices by the rewiring structure for being added of the invention
Each of multiple the second new pads are formd on original first pad so that point is surveyed and welding procedure can be mutual
Operation is distinguished on the different pads of connection, avoid that on same pad pad bottom metal layers caused by operation crack asks
Topic;And the diversification of the position of new pad is but also each pad clock having the same on the semiconductor devices is anti-
It answers.
5, the manufacturing method of semiconductor devices of the invention passes through one second pad in rewiring structure of the invention
It is upper to weld, while making point on another second pad of the rewiring structure and surveying, it avoids same described second
The problem of bottom metal layers crack caused by doing a survey on pad and welding.
Detailed description of the invention
Fig. 1 a is the schematic diagram of the position of pad on existing semiconductor devices (chip);
Fig. 1 b is the longitudinal cross-section schematic diagram of pad on existing semiconductor devices (chip) shown in Fig. 1 a;
Fig. 2 is the flow chart of the manufacturing method of the rewiring structure of one embodiment of the invention;
Fig. 3 a~3g is the device schematic diagram in the manufacturing method of rewiring structure shown in Fig. 2;
Fig. 4 is the schematic diagram of the position of pad on the semiconductor devices (chip) of one embodiment of the invention.
Wherein, the reference numerals are as follows for attached drawing 1a~4:
P1,P2,M1-Cu Pad;P3~P5, M2-Al Pad;The second pad of P6~P10-;L1, L2, L3- interconnection line;10-
Substrate;The first pad of 11-;The first dielectric substance layer of 20-;30- reroutes metal layer;The second dielectric substance layer of 40-;The second pad of 50-;
T1~T4- groove.
Specific embodiment
It is proposed by the present invention heavy below in conjunction with 2~4 pairs of attached drawing to keep the purpose of the present invention, advantages and features clearer
New route structure and its manufacturing method and semiconductor devices and its manufacturing method are described in further detail.It should be noted that attached
Figure is all made of very simplified form and using non-accurate ratio, only to convenient, lucidly the aid illustration present invention is real
Apply the purpose of example.
One embodiment of the invention provides a kind of manufacturing method of rewiring structure, referring to Fig.2, Fig. 2 is that the present invention one is real
The flow chart of the manufacturing method of the rewiring structure of example is applied, the manufacturing method of the rewiring structure includes:
Step S2-A, a substrate with the first pad is provided, forms the first dielectric substance layer on the substrate, described the
One dielectric substance layer exposes the top surface of some or all of described first pad;
Step S2-B, it is formed and reroutes metal layer on the top surface of first pad, the rewiring metal layer is also
It extends on the portion top surface of first dielectric substance layer;
Step S2-C, the second dielectric substance layer is formed on the rewiring metal layer and first dielectric substance layer, it is described
Second dielectric substance layer has the multiple openings for exposing the top surface for rerouting metal layer different location respectively, each opening
The rewiring metal layer that bottom-exposed goes out is as second pad, the rewiring metal layer and first pad electricity
Contact, so that second pad is electrically connected with first pad.
Introduce the manufacturing method of rewiring structure provided in this embodiment in more detail referring next to Fig. 3 a~Fig. 3 g,
Fig. 3 a~3g is the device schematic diagram in the manufacturing method of rewiring structure shown in Fig. 2.
Firstly, refering to Fig. 3 a~Fig. 3 c, according to step S2-A, a substrate 10 with the first pad 11 is provided, forms the
For one dielectric substance layer 20 on the substrate 10, first dielectric substance layer 20 exposes some or all of described first pad 11
Top surface.It can be seen that from Fig. 3 a, first pad 11 can partially be located in the substrate 10, and another part is located at institute
On the top surface for stating substrate 10, may exist a groove in first pad 11 on the top surface of the substrate 10
T1.In addition, the top surface of first pad 11 is also possible to the arc-shaped face of a plane or protrusion.From Fig. 3 b and Fig. 3 c
It can be seen that, when there are include: head the step of when the groove T1, forming the first dielectric substance layer 20 in first pad 11
First, first dielectric substance layer 20 is deposited on the substrate 10, and first dielectric substance layer 20 deposited is by described first
Pad 11 is completely buried in interior (such as Fig. 3 b);Then, by chemical mechanical grinding by the top surface of first dielectric substance layer 20
Planarization;Finally, etching first dielectric substance layer 20 is located at the part on first pad 11, by first pad
(such as Fig. 3 c) is exposed in some or all of 11 top surface.In addition, also may include in the substrate 10 other metal layers and
Dielectric substance layer, such as copper (Cu) metal layer and ethyl orthosilicate (TEOS) dielectric substance layer.
Then, it refering to Fig. 3 d and Fig. 3 e, according to step S2-B, is formed and reroutes metal layer 30 in first pad 11
On top surface, the rewiring metal layer 30 is also extended on the portion top surface of first dielectric substance layer 20.From Fig. 3 d and
The step of can be seen that in Fig. 3 e, forming rewiring metal layer 30 includes: firstly, forming a metal layer in first pad
11 and first dielectric substance layer 20 on, the metal layer covers first dielectric substance layer 20 and first pad 11 completely
In being embedded in, the method for forming the metal layer can be sputtering sedimentation;Then, by lithography and etching by the metal layer image
Change, to form the rewiring metal layer 30.Since first dielectric substance layer 20 formed in step S2-A exposes institute
The top surface of some or all of first pad 11 is stated, so, first pad 11 in first dielectric substance layer 20
It will form a groove T2 on top surface, then, in the top surface and first dielectric substance layer 20 to first pad 11
When forming the metal layer on top surface, the thickness of the metal layer on first pad 11 can be with first dielectric
The thickness of the metal layer on the top surface of matter layer 20 is identical, thus in the metal layer above first pad 11
Form a groove T3;When by lithography and etching by the metallic layer graphic, the groove T3 can be retained, simultaneously
Another or multiple grooves, example are etched on the metal layer on the portion top surface for being located at first dielectric substance layer 20
Such as the groove T4 in Fig. 3 e.Alternatively, can also be by way of extending in the sedimentation time on first pad 11, so that institute
It states the metal layer on the top surface of the first pad 11 and on the top surface of first dielectric substance layer 20 to flush, that is, forms one
Then plane, then is formed simultaneously by way of lithography and etching 2 or 2 or more grooves in the metal layer.Separately
It outside, include also interconnection line in the rewiring metal layer 30, such as scheme in order to guarantee to can connect conducting between the groove to be formed
Interconnection line L2 and L3 in 4.
Finally, according to step S2-C, forming the second dielectric substance layer 40 in the rewiring metal layer refering to Fig. 3 f and Fig. 3 g
30 and first dielectric substance layer 20 on, second dielectric substance layer 40 have exposes the rewiring metal layer 30 respectively not
With multiple openings of the top surface of position, the rewiring metal layer 30 that each open bottom exposes is as one second weldering
Disk 50, the rewiring metal layer 30 is in electrical contact with first pad 11, so that second pad 50 and described first
Pad 11 is electrically connected.The step of can be seen that from Fig. 3 f and Fig. 3 g, forming the second dielectric substance layer 40 includes: firstly, deposition
Second dielectric substance layer 40 is on the rewiring metal layer 30 and first dielectric substance layer 20;Then, described second is etched to be situated between
Electric matter layer 40 is located at the part on the different location for rerouting metal layer 30, exposes the rewiring gold respectively to be formed
Belong to multiple openings of the top surface of 30 different location of layer.The metal layer 30 that reroutes includes the mutual of connection second pad 50
The quantity of line, second pad 50 of each interconnection line connection is more than or equal to 2.Second pad 50 and first weldering
Disk 11 is directly in electrical contact, alternatively, the interconnection line and first pad 11 are directly in electrical contact, so that second pad 50
It is electrically connected with first pad 11, so that connecting conducting between second pad 50 and first pad 11.By
It is mainly used for shielding to the rewiring metal layer 30 in second dielectric substance layer 40, so, in second weldering
Certain thickness second dielectric substance layer can still be retained on the side wall of the groove of the rewiring metal layer 30 where disk 50
40。
It is the schematic diagram of the position of pad on the semiconductor devices (chip) of one embodiment of the invention refering to Fig. 4, Fig. 4, from
It can be seen that in Fig. 4, described the to be connected with Al Pad shown in Fig. 1 a (i.e. material be Al first pad 11) P3
Two pads 50 are P6, and P6 passes through interconnection line L2 connection P7 and P8;In addition, with Al Pad shown in Fig. 1 a, (i.e. material is Al
First pad 11) second pad 50 that is connected of P5 is P9, and P9 passes through interconnection line L3 connection P10.Work as needs
When carrying out a survey and welding to the pad on semiconductor devices (chip), if using semiconductor devices (core shown in Fig. 1 a
Piece) pad design, P3 is upper should to carry out surveying, and welded again, biggish compression may result in institute in Fig. 1 b
The Cu Pad M1 cracking shown;But if using the pad on semiconductor devices shown in Fig. 4 (chip) design, can be with
A survey is done on P6, is welded on P7 or P8;Can be welded on P9, do and to survey on P10, on pad each in this way by
The compression arrived is smaller, to avoid result in Cu Pad M1 cracking.In addition, due to being connected between P9 and P10, so that being located at
The P9 close to semiconductor devices (chip) center can also pass through the P10 positioned at semiconductor devices (chip) peripheral position
Obtain Clock reaction identical with other pads of semiconductor devices (chip) periphery are located at.
In conclusion the manufacturing method of rewiring structure provided by the invention, comprising: form the first dielectric substance layer in one
On substrate with the first pad, first dielectric substance layer exposes the top surface of some or all of described first pad;
It is formed and reroutes metal layer on the top surface of first pad, the rewiring metal layer also extends to first dielectric
On the portion top surface of matter layer;And the second dielectric substance layer is formed in the rewiring metal layer and first dielectric substance layer
On, second dielectric substance layer has the multiple openings for exposing the top surface for rerouting metal layer different location respectively,
The rewiring metal layer that each open bottom exposes is as second pad, the rewiring metal layer and described the
One pad electrical contact, so that second pad is electrically connected with first pad.The rewiring provided through the invention
The manufacturing method of structure, so that the quantity of pad increases and position is more diversified, so that semiconductor devices (chip)
On pad Clock reaction having the same and can avoid surveying and pad caused by welding doing on the same pad
The cracking of bottom metal layers.
One embodiment of the invention provides a kind of rewiring structure, refering to Fig. 3 g, can be seen that from Fig. 3 g, the cloth again
Cable architecture includes: the first dielectric substance layer 20, reroutes metal layer 30 and the second dielectric substance layer 40.First dielectric substance layer 20
In one with the first pad 11 substrate 10 on, and first dielectric substance layer 20 expose first pad 11 part or
Whole top surfaces;The rewiring metal layer 30 is located on the top surface of first pad 11, the rewiring metal layer
30 also extend on the portion top surface of first dielectric substance layer 20;And second dielectric substance layer 40 is positioned at described heavy
On interconnection metal layer 30 and first dielectric substance layer 20, second dielectric substance layer 40 has exposes the rewiring respectively
Multiple openings of the top surface of 30 different location of metal layer, 30 conduct of rewiring metal layer that each open bottom exposes
One the second pad 50, the rewiring metal layer 30 is in electrical contact with first pad 11, so that second pad 50
It is electrically connected with first pad 11.
Rewiring structure provided in this embodiment is introduced in more detail referring next to Fig. 3 g:
First dielectric substance layer 20 is located on a substrate 10 with the first pad 11, and first dielectric substance layer 20
Expose the top surface of some or all of described first pad 11.First pad 11 can partially be located at the substrate 10
In, another part is located on the top surface of the substrate 10, first pad 11 on the top surface of the substrate 10
In may exist a groove T1.In addition, the top surface of first pad 11 be also possible to a plane or protrusion it is arc-shaped
Face.The material of first dielectric substance layer 20 may include silica (SiO2), silicon nitride (Si3N4), ethyl orthosilicate
(TEOS), Pyrex (BSG), phosphorosilicate glass (PSG), boron-phosphorosilicate glass (BPSG) are any one or more of, are located at described
The thickness of first dielectric substance layer 20 on the top surface of first pad 11 can be(for example,Deng), the thickness of first dielectric substance layer 20 on the substrate 10 can be(for example, Deng).
The rewiring metal layer 30 is located on the top surface of first pad 11, and the rewiring metal layer 30 also prolongs
On the portion top surface for extending to first dielectric substance layer 20.The rewiring metal layer 30 is also comprising connecting second pad
The quantity of 50 interconnection line, second pad 50 of each interconnection line connection is more than or equal to 2.The rewiring metal layer 30
Material may include that aluminium (Al), golden (Au), silver-colored (Ag), nickel (Ni), titanium (Ti) are any one or more of, the rewiring metal
Layer 30 thickness can be(for example,Deng);
Second dielectric substance layer 40 is located on the rewiring metal layer 30 and first dielectric substance layer 20, and described
Two dielectric substance layers 40 have the multiple openings for exposing the top surface for rerouting 30 different location of metal layer respectively, Mei Gekai
The rewiring metal layer 30 that mouthful bottom-exposed goes out is used as second pad 50, the rewirings metal layer 30 and described the
One pad 11 electrical contact, so that second pad 50 is electrically connected with first pad 11.The rewiring metal layer 30
Also comprising the interconnection line for connecting second pad 50, the quantity of second pad 50 of each interconnection line connection is more than or equal to
2, i.e., the quantity that second pad 50 of conducting is connect with each first pad 11 is more than or equal to 2.Second dielectric substance layer
40 material may include silica (SiO2), silicon nitride (Si3N4), ethyl orthosilicate (TEOS), Pyrex (BSG), phosphorus
Silica glass (PSG), boron-phosphorosilicate glass (BPSG) are any one or more of, and described on first dielectric substance layer 20
The thickness of two dielectric substance layers 40 can be(for example, Deng).
In conclusion rewiring structure provided by the invention, including be located on a substrate with the first pad the
One dielectric substance layer, first dielectric substance layer expose the top surface of some or all of described first pad;Positioned at described
Rewiring metal layer on the top surface of one pad, the part for rerouting metal layer and also extending to first dielectric substance layer
On top surface;And the second dielectric substance layer on the rewiring metal layer and first dielectric substance layer, described second
Dielectric substance layer has the multiple openings for exposing the top surface for rerouting metal layer different location respectively, each open bottom
The rewiring metal layer exposed connects as second pad, the rewiring metal layer with the first pad electricity
Touching, so that second pad is electrically connected with first pad.Rewiring structure provided by the invention can be each
The new pad for being more than or equal to 2 quantity is formed on former pad, so that the quantity of pad increases, and the position of pad is also more more
Sample so that pad on semiconductor devices (chip) can Clock reaction having the same, and avoid same
The cracking of pad bottom metal layers caused by doing a survey on pad and welding.
One embodiment of the invention provides a kind of pad structure, and the pad structure includes: that the first pad and the present invention provide
The rewiring structure, the rewiring structure is located on first pad.By using the rewiring knot
Structure forms the second pad, and described the of the interconnection formed on each first pad on first pad
The quantity of two pads is more than or equal to 2, and second pad being connected can be located at the periphery of semiconductor devices (chip) simultaneously,
Or part be located at semiconductor devices (chip) periphery, another part be located at semiconductor devices (chip) lean on paracentral position
It sets, to realize each pad Clock reaction having the same, and second pad being connected can partially be used for a survey, separately
A part avoids first pad or described first caused by doing a survey and welding on the same pad for welding
The problem of metal layer below pad cracks.
One embodiment of the invention provides a kind of semiconductor devices, and the semiconductor devices includes: with the first pad, metal
Interconnection structure, the substrate of third dielectric substance layer and the rewiring structure provided by the invention.Third dielectric substance layer position
In on the bottom surface of the rewiring structure, and the metal interconnection structure is formed in the third dielectric substance layer, and described
The bottom surface of the top surface of metal interconnection structure and the first pad of the rewiring structure is in electrical contact;First pad is also
It extends on the portion top surface of the third dielectric substance layer.The material of the metal interconnection structure may include copper (Cu), aluminium
(Al), cobalt (Co) is any one or more of, and the material of the third dielectric substance layer may include silica (SiO2), positive silicic acid
Ethyl ester (TEOS), Pyrex (BSG), phosphorosilicate glass (PSG), boron-phosphorosilicate glass (BPSG) are any one or more of.Pass through
Using the rewiring structure, the second pad is formd on first pad, second pad passes through interconnection line phase
It connects, the quantity of second pad of each interconnection line connection is more than or equal to 2, in this way can be in the rewiring structure
One second pad on weld, while on another second pad of the rewiring structure make point survey, avoid same
What first pad or the metal interconnection structure cracked caused by doing a survey on one second pad and welding asks
Topic;And the position of second pad is more diversified, so that the pad clock having the same on the semiconductor devices
Reaction.
One embodiment of the invention provides a kind of manufacturing method of semiconductor devices, comprising: provided by the invention described heavy
It is welded on one second pad of new route structure, while making point on another second pad of the rewiring structure and surveying,
Avoid the problem of bottom metal layers crack caused by doing a survey and welding on same second pad.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (11)
1. a kind of manufacturing method of rewiring structure characterized by comprising
One substrate with the first pad is provided;
The first dielectric substance layer is formed on the substrate, first dielectric substance layer exposes the part or complete of first pad
The top surface in portion;
It is formed and reroutes metal layer on the top surface of first pad, the rewiring metal layer also extends to described first
On the portion top surface of dielectric substance layer;And
The second dielectric substance layer is formed on the rewiring metal layer and first dielectric substance layer, second dielectric substance layer has
There are the multiple openings for exposing the top surface for rerouting metal layer different location respectively, the institute that each open bottom exposes
It states and reroutes metal layer as second pad, the rewiring metal layer and first pad electrical contact, so that institute
The second pad is stated to be electrically connected with first pad.
2. the manufacturing method of rewiring structure as described in claim 1, which is characterized in that the rewiring metal layer includes
The interconnection line of second pad is connected, the quantity of second pad of each interconnection line connection is more than or equal to 2.
3. the manufacturing method of rewiring structure as described in claim 1, which is characterized in that form first dielectric substance layer
The step of include: firstly, deposition first dielectric substance layer is on the substrate, and first dielectric substance layer deposited is by institute
It states in the first pad is completely buried in;Then, the top surface of first dielectric substance layer is planarized by chemical mechanical grinding;
Finally, etching first dielectric substance layer is located at the part on first pad, by the part of first pad or entirely
The top surface in portion is exposed.
4. the manufacturing method of rewiring structure as claimed in claim 1 or 2, which is characterized in that form the rewiring gold
The step of belonging to layer includes: the metal layer firstly, form a metal layer on first pad and first dielectric substance layer
First dielectric substance layer and first pad are completely buried in interior;Then, by lithography and etching by the metal layer
Graphically, to form the rewiring metal layer.
5. the manufacturing method of rewiring structure as described in claim 1, which is characterized in that form second dielectric substance layer
The step of include: firstly, deposition the second dielectric substance layer on the rewiring metal layer and first dielectric substance layer;Then,
The part that second dielectric substance layer is located on the different location for rerouting metal layer is etched, exposes institute respectively to be formed
State the multiple openings for rerouting the top surface of metal layer different location.
6. a kind of rewiring structure characterized by comprising
First dielectric substance layer, on a substrate with the first pad, first dielectric substance layer exposes first weldering
The top surface of some or all of disk;
Metal layer is rerouted, on the top surface of first pad, the rewiring metal layer also extends to described first
On the portion top surface of dielectric substance layer;And
Second dielectric substance layer is located on the rewiring metal layer and first dielectric substance layer, the second dielectric substance layer tool
There are the multiple openings for exposing the top surface for rerouting metal layer different location respectively, the institute that each open bottom exposes
It states and reroutes metal layer as second pad, the rewiring metal layer and first pad electrical contact, so that institute
The second pad is stated to be electrically connected with first pad.
7. rewiring structure as claimed in claim 6, which is characterized in that the rewiring metal layer includes to connect described the
The quantity of the interconnection line of two pads, second pad of each interconnection line connection is more than or equal to 2.
8. the rewiring structure as described in claim 6 or 7, which is characterized in that the material packet for rerouting metal layer
It is any one or more of to include aluminium, gold, silver, nickel, titanium;The material of first dielectric substance layer and second dielectric substance layer includes
Silica, silicon nitride, ethyl orthosilicate, Pyrex, phosphorosilicate glass, boron-phosphorosilicate glass are any one or more of.
9. a kind of pad structure characterized by comprising cloth again described in any one of the first pad and claim 6 to 8
Cable architecture, the rewiring structure are located on first pad.
10. a kind of semiconductor devices characterized by comprising have the first pad, metal interconnection structure, third dielectric substance layer
Substrate and any one of claim 6 to 8 described in rewiring structure;The third dielectric substance layer is located at the cloth again
On the bottom surface of cable architecture, and the metal interconnection structure is formed in the third dielectric substance layer, and the metal interconnection structure
Top surface and the rewiring structure the first pad bottom surface be in electrical contact;First pad also extends to described
On the portion top surface of three dielectric substance layers.
11. a kind of manufacturing method of semiconductor devices described in any one of claim 10 characterized by comprising in the cloth again
It is welded on one second pad of cable architecture, while making point on another second pad of the rewiring structure and surveying.
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Cited By (1)
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US11837551B2 (en) | 2020-09-09 | 2023-12-05 | Samsung Electronics Co., Ltd. | Semiconductor package |
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US20030218246A1 (en) * | 2002-05-22 | 2003-11-27 | Hirofumi Abe | Semiconductor device passing large electric current |
US20110049515A1 (en) * | 2003-12-08 | 2011-03-03 | Megica Corporation | Chip structure with bumps and testing pads |
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CN1387681A (en) * | 1999-11-05 | 2002-12-25 | 爱特梅尔股份有限公司 | Metal redistribution layer having solderable pads and wire bondable pads |
US20020180026A1 (en) * | 2001-06-05 | 2002-12-05 | Chipmos Technologies Inc. | Semiconductor wafer designed to avoid probed marks while testing |
US20030218246A1 (en) * | 2002-05-22 | 2003-11-27 | Hirofumi Abe | Semiconductor device passing large electric current |
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