CN109309084A - Electric static discharge protector - Google Patents
Electric static discharge protector Download PDFInfo
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- CN109309084A CN109309084A CN201710617014.1A CN201710617014A CN109309084A CN 109309084 A CN109309084 A CN 109309084A CN 201710617014 A CN201710617014 A CN 201710617014A CN 109309084 A CN109309084 A CN 109309084A
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- Prior art keywords
- doped region
- static discharge
- substrate
- discharge protector
- interior
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Abstract
The present invention discloses a kind of electric static discharge protector comprising: substrate, epitaxial layer, the first interior doped region, the second interior doped region, the first top doped region, the second top doped region and conductive layer.There is a first element area and a second element area in substrate, epitaxial layer is set in substrate, first interior doped region and the second interior doped region are respectively arranged in first element area and second element area and close to the junctions of substrate and epitaxial layer, first top doped region is respectively arranged on first element area in second element area and respectively from the surface exposed of epitaxial layer with the second top doped region, and conductive layer is electrically connected the first top doped region and the second top doped region.Accordingly, clamp voltage can be effectively reduced in the present invention.
Description
Technical field
The present invention relates to a kind of semiconductor elements, more particularly to a kind of electric static discharge protector.
Background technique
Electrostatic is always masty problem to the injury of electronic product, and the electronic product of normal operating is once by quiet
When discharge of electricity (Electrostatic Discharge, ESD) acts on, it often will appear some unstable phenomenons, as function is unexpected
Not normal situation etc., less serious case's palpus boots could exclude, and serious person will directly contribute damage of product.To ensure that electronic product is normally transported
Row can often increase protection element to make it have the anti-ability processed of electrostatic, when electrostatic is more than the peace of a certain setting in electronic product
When total head, protection element is soon done with by overvoltage and overcurrent safe release to ground connection.
Existing protection element is broadly divided into platform-type (Mesa), plane formula (Planar) and plough groove type (Trench) and ties
Structure, wherein Mesa structure belongs to stereochemical structure, therefore is unfavorable for the contraposition in yellow light technique and exposes to influence the stability of technique,
It is unable to satisfy requirement of the small-sized component for line width and photoresist (PR) cladding ability.Although Planar structure can solve
The problem that steric hindrance, and the line width after yellow light development also may conform to the design requirement of element high accurancy and precision, but due to
Planar structure is only used for the design of transverse type, so the ground connection region (Gnd) must be designed the element surface more,
The area of Planar structure is also therefore bigger than what Mesa structure was come；In addition, preventing for Planar structure is quiet compared with Mesa structure
Electric energy power is weaker.
Trench structure maintains chip surface mainly by way of digging out groove from surface and inserting insulating layer
Flatness can so promote the ability of yellow light technique, and since Trench structure and Mesa structure are similarly vertical conducting element,
So anti-static ability is significantly better than Planar structure, not needing to design a region Gnd element surface so as to have more yet
The size of effect reduction integral member.However, Trench structure has the significant drawback for being also easy to produce high clamp voltage (Vc), this may
It will affect the operation of IC element.
Summary of the invention
Technical problem to be solved by the present invention lies in provide a kind of electrostatic discharge (ESD) protection member in view of the deficiencies of the prior art
Part can protect IC element not destroyed by esd pulse, and ensure that it can be worked normally in high frequency, to meet the need of high-frequency transmission
It wants.
In order to solve the above technical problems, a wherein technical solution of the present invention is: a kind of static discharge guarantor
Protection element a comprising substrate, an epitaxial layer, one first interior doped region, one second interior doped region, one first top doping
Area, one second top doped region and a conductive layer.The substrate has a first conductive type, and has one first yuan in the substrate
Part area, a second element area and one are set to the isolated area between the first element area and the second element area；The epitaxial layer is set
In in the substrate, and the second conductive type for being different from the first conductive type with one；First interior doped region and this in second
Portion's doped region is respectively arranged in the first element area and the second element area, and close to the junction of the substrate and the epitaxial layer,
In first interior doped region have the second conductive type, and second interior doped region have the first conductive type；This first
Top doped region and second top doped region are respectively arranged in the first element area and the second element area, and of heap of stone from this respectively
Crystal layer it is surface exposed, wherein first top doped region have the first conductive type, and second top doped region have should
The second conductive type；The conductive layer is electrically connected first top doped region and second top doped region.
Further, which further includes a buffer layer being set between the substrate and the epitaxial layer,
The buffer layer has a second conductive type, and first interior doped region and second interior doped region extend further downward to
In the buffer layer.
Further, first interior doped region and second interior doped region further extend horizontally to the isolated area
It is interior.
Further, which further includes multiple insulated trench, and at least one insulated trench is set to should
In isolated area, and first interior doped region and second interior doped region are extended downwardly through from the surface of the epitaxial layer and is prolonged
It extends in the substrate, another insulated trench is set in the first element area, and is extended downwardly through from the surface of the epitaxial layer
First interior doped region simultaneously extends in the substrate, and another insulated trench is set in the second element area, and from the epitaxy
The surface of layer extends downwardly through second interior doped region and extends in the substrate.
Further, which includes at least two partial sectors being separated from each other and at least one position
Channel section between the partial sector and relative to first top doped region.
Further, which further includes a separation layer, which is set on the epitaxial layer, this is led
Electric layer is set on the separation layer, and contacts first top doped region and second top doped region by the separation layer.
Further, which has the resistivity between 0.001 ohm-cm and 0.13 ohm-cm, should
Epitaxial layer has the resistivity between 14 ohm-cms and 100 ohm-cms, and micro- with 6 between 2 microns with one
Thickness between rice.
Further, the width of first interior doped region and second interior doped region is between 0.5 micron to 10 microns
Between, and doping concentration between 1E12 atoms/cm between 1E17 atoms/cm.
Further by taking positive-negative-positive structure as an example, which is p-type, and the second conductive type is N-type.
Further by taking NPN structure as an example, which is N-type, and the second conductive type is p-type.
The beneficial effects of the present invention are, electric static discharge protector provided by technical solution of the present invention, by " will
First interior doped region and the second interior doped region are respectively arranged in first element area and second element area, and close to substrate with
The junction of epitaxial layer, wherein substrate and the second interior doped region conductibility having the same, and epitaxial layer and the first inside doping
The design of area's conductibility having the same " can effectively reduce clamp voltage, and can improve and adulterate (auto- in technique automatically
Doping influence) is to promote whole yield.
Be further understood that feature and technology contents of the invention to be enabled, please refer to below in connection with it is of the invention specifically
Bright and attached drawing, however provided attached drawing is merely provided for reference and description, is not intended to limit the present invention.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of a part of the electric static discharge protector of first embodiment of the invention.
Fig. 2 is the schematic equivalent circuit of a part of the electric static discharge protector of first embodiment of the invention.
Fig. 3 is the structural schematic diagram of a part of the electric static discharge protector of second embodiment of the invention.
Fig. 4 is the schematic equivalent circuit of a part of the electric static discharge protector of second embodiment of the invention.
Specific embodiment
The invention mainly relates to a kind of electric static discharge protectors for power semiconductor, not merely with groove
Formula structure come reduce component size and improve technology stability, clamp voltage (Vc) is also reduced using NPN structure.It is logical below
Particular specific embodiment is crossed to illustrate the presently disclosed embodiment in relation to " electric static discharge protector ", this field skill
Art personnel can understand advantages of the present invention and effect by content disclosed in this specification.The present invention can pass through other different tools
Body embodiment is implemented or is applied, and the various details in this specification may be based on different viewpoints and application, is not departing from this
Various modifications and change are carried out under the design of invention.In addition, attached drawing of the invention is only simple schematically illustrate, not according to practical ruler
Very little description is stated in advance.The relevant technologies content of the invention will be explained in further detail in the following embodiments and the accompanying drawings, but disclosed
The protection scope that is not intended to limit the invention of content.
First embodiment
Referring to Fig. 1, the structural schematic diagram of a part for the electric static discharge protector of first embodiment of the invention.Such as
Shown in figure, electric static discharge protector Z1 inside a substrate 1, an epitaxial layer 2, one first interior doped region 3, one second including mixing
Miscellaneous area 3 ', one first top doped region 4, one second top doped region 4 ', a separation layer 5, one first conductive layer 6 and one second
Conductive layer 6 '.
In the present embodiment, substrate 1 can be silicon chip, and have a first conductive type, wherein have one first yuan in substrate 1
Part area 11, a second element area 12 and an isolated area 13 between first element area 11 and second element area 12；Epitaxy
Layer 2 can be formed on the first surface 14 (such as top surface) of substrate 1 by epitaxial growth regime, and has a second conductive type,
Wherein the second conductive type is different from the first conductive type, for example, it is N that the second conductive type is i.e. opposite when the first conductive type is p-type
Type, the two are also interchangeable.Preferably, substrate 1 can have one between 0.001 ohm-cm (Ohm-cm) and 0.13 ohm-cm
Between resistivity, epitaxial layer 2 can have the resistivity between 14 ohm-cms and 100 ohm-cms, and epitaxy
Layer 2 can have the thickness between 2 microns (μm) and 6 microns, so that element meets (such as 5 volts to 24 of specific condition
The breakdown voltage of volt).
First interior doped region 3 and the second interior doped region 3 ' can pass through ion implant (Ion Implant) and thermal diffusion
(Thermal Diffusion) mode is respectively positioned on substrate 1 to be respectively formed in first element area 11 and second element area 12
Near the junction of epitaxial layer 2, the first interior doped region 3 has the second conductive type, and the second interior doped region 3 ' has first
Conductivity type；Preferably, the width of the first and second interior doped regions 3,3 ' is between 0.5 micron to 10 microns, and adulterates dense
Degree is between 1E12cm-3To 1E17cm-3Between.
Being worth being described is, substrate 1, first or second interior doped region 3,3 ' and epitaxial layer 2 may make up a NPN
Structure, and enlarge-effect provided by this NPN structure can reduce the resistance value of element entirety to which Vc value be effectively reduced；In addition,
Vc value can be reduced by adjusting the structure and doping concentration of first and second interior doped regions 3,3 '；Furthermore due to the first He
The doping concentration variation of second interior doped region 3,3 ' will affect the size of exhaustion region, therefore can be by adjusting in first and second
The doping concentration of portion's doped region 3,3 ' reaches the capacitance of setting, and wherein the configuration of first or second interior doped region 3,3 ' is again
The stability of capacitance can be improved.
First top doped region 4 and the second top doped region 4 ' can be respectively formed in first yuan by ion implant mode
In part area 11 and second element area 12, and respectively from the surface exposed of epitaxial layer 2；First and second top doped regions 4,4 ' can be divided
Not as the source area of element and collector region, wherein the first top doped region 4 has the first conductive type, the first top doped region 4
Doping concentration be greater than the doping concentration of epitaxial layer 2, a part of the first top doped region 4 and the first interior doped region 3 is vertical
Histogram is overlapped on (thickness direction of epitaxial layer 2) and one suitable distance of mutual holding, to be formed in epitaxial layer 2
Drift region；Similarly, the second top doped region 4 ' has the second conductive type, and the doping concentration of the second top doped region 4 ' is greater than of heap of stone
The doping concentration of crystal layer 2, the second top doped region 4 ' are same as a part of the second interior doped region 3 ' in vertical direction (epitaxy
Layer 2 thickness direction) on overlapped and one suitable distance of mutual holding, to form drift region in epitaxial layer 2.
Separation layer 5 can be formed on epitaxial layer 2 by various methods well known to those skilled in the art, and avoid the first He
The coverage area of second top doped region 4,4 ', that is, separation layer 5 has opening (not labeled) to the first and second top of exposure
Doped region 4,4 '.First conductive layer 6 can be formed with the second conductive layer 6 ' by various methods well known to those skilled in the art,
Using the electrode as element, wherein the first conductive layer 6 is configured on separation layer 5, and the first and second top doped regions 4 of contact,
4 ', to be electrically connected the high-pressure side (such as 5 volts of power supplys) of regulated power supply, the second conductive layer 6 ' is configured at the second table of substrate 1
On face 15 (such as bottom surface), to be electrically connected another protected element (such as IC element).
The buffer layer 7 of a second conductive type can be further formed between substrate 1 and epitaxial layer 2, at this time in first and second
Portion's doped region 3,3 ' extends downward into buffer layer 7；Epitaxial layer 2 can be formed in by epitaxial growth regime simultaneously with buffer layer 7
In substrate 1, wherein the thickness of buffer layer 7 is thin compared with epitaxial layer 2, and doping concentration is less than the doping concentration of epitaxial layer 2.
It is the first conductive type and the using p-type and N-type in electric static discharge protector Z1 also referring to Fig. 1 and Fig. 2
Two conductivity types, substrate 1, epitaxial layer 2, the first interior doped region 3 and the first top doped region 4 can be constituted in first element area 11
Zener diode D2 (the Zener of one first steering PN diode D1 and one and the first steering PN diode D1 series coupled
Diode), and substrate 1, epitaxial layer 2, the second interior doped region 3 ' and the second top doped region 4 ' can in second element area 12 structure
At one second steering PN diode D3, wherein the second steering PN diode D3 and the first steering PN diode D1 and Zener diode
The combination parallel coupled of D2.
Furthermore, electric static discharge protector Z1 (is filled exhausted using multiple insulated trench T1, T2, T3 in groove
Edge material) will be formed the first steering PN diode D1 epitaxial layer 2 a part and form the of heap of stone of the second steering PN diode D3
Another part of crystal layer 2 is isolated, these insulated trench T1, T2, T3 simultaneously contributes to form Zener diode D2；Specifically, until
A few insulated trench T1 is configured in isolated area 13, and is extended downward into substrate 1 from the surface of epitaxial layer 2, if the first He
Second interior doped region 3,3 ' further extends horizontally in isolated area 13, then the surface of insulated trench T1 from epitaxial layer 2 is downward
It extends through the first and second interior doped regions 3,3 ' and extends in substrate 1, another insulated trench T2 is configured at first yuan
In part area 11, and the first interior doped region 3 being extended downwardly through from the surface of epitaxial layer 2 and is extended in substrate 1, another is absolutely
Edge groove T3 is configured in second element area 12, and extends downwardly through the second interior doped region 3 ' simultaneously from the surface of epitaxial layer 2
It extends in substrate 1.
Must be described is, although showing in Fig. 1, the quantity for the insulated trench T1 being configured in isolated area 13 has two
A, so actually the quantity of insulated trench T1 can be changed with position according to actual demand, therefore insulated trench T1 as shown in Figure 1
Quantity only supply for example, limit the present invention.
When positive static discharge (ESD) occurs, generated positive current IPBy from connection the first conductive layer 6 terminals P 1
The terminals P 2 for connecting the second conductive layer 6 ' is flowed to Zener diode D2 by the first steering PN diode D1；Due to 1 phase of terminals P
It is imposed to bigger positive voltage for terminals P 2, and is forward biased the first steering PN diode D1 and Zener diode D2
It is reverse biased, therefore the maximum voltage between terminals P 1, P2 can be fixed to and be approximately equal to Zener by the first steering PN diode D1
The Zener voltage (such as 5 volts) of diode D2, to protect the element of rear end not destroyed by ESD.When reversed ESD occurs, institute
The negative current I of generationNTerminals P 1 will be flowed to from terminals P 2 by the second steering PN diode D3, and in the second control of forward bias
Reversed esd pulse can be safely handled to PN diode D3.
Second embodiment
Referring to Fig. 3, the cross-sectional view of a part for the electric static discharge protector of second embodiment of the invention.As schemed
Show, the present embodiment different from the first embodiment essentially consists in, the first interior doped region 3 packet in electric static discharge protector Z1
It includes partial sector 31 that at least two are separated from each other and at least one is located between these partial sectors 31 and relative to first
The channel section 32 of top doped region 4, remaining technical detail are identical with the first embodiment, and in this, it is no longer repeated.
Also referring to Fig. 3 and Fig. 4, using p-type and N-type as the first conductive type and the second conductive type, substrate 1, epitaxial layer
2, the first interior doped region 3 and the first top doped region 4 can be constituted in first element area 11 one first steering PN diode D1,
Zener diode D2 and one second steering PN diode D3, wherein Zener diode D2 and the second steering PN diode D3 be simultaneously
Connection coupling, and the combination series coupled of the first steering PN diode D1 and Zener diode D2 and the second steering PN diode D3；
In addition, substrate 1, epitaxial layer 2, the second interior doped region 3 ' can be constituted in second element area 12 with the second top doped region 4 ' it is another
A second steering PN diode D3, and this second steering PN diode D3 and the first steering PN diode D1, Zener diode D2
With the combination parallel coupled of the second steering PN diode D3.
Being worth being described is, when positive static discharge (ESD) occurs, generated positive current IPIt can be from terminal
P1 flows to terminals P 2 by the first steering PN diode D1 and Zener diode D2, can also pass through the first steering PN bis- from terminals P 1
Pole pipe D1 and the second steering PN diode D3 flow to terminals P 2；Accordingly, electric static discharge protector Z1 is not only using Zener two
The stabilizing voltage characteristic of pole pipe D2 protects the element of rear end, and Vc value can be also reduced using negative resistance effect.
[beneficial effect of embodiment]
Electric static discharge protector provided by the embodiment of the present invention, passing through " will be in the first interior doped region and second
Portion's doped region is respectively arranged in first element area and second element area, and close to the junction of substrate and epitaxial layer, wherein substrate
With the second interior doped region conductibility having the same, and epitaxial layer and the first interior doped region conductibility having the same "
Design, can effectively reduce clamp voltage, and can improve in technique that adulterate the influence of (auto-doping) automatically whole good to be promoted
Rate.
Hold above-mentioned, the present invention can also reduce Vc by adjusting the structure and doping concentration of first and second interior doped regions
Value.
Furthermore since the variation of the doping concentration of the first and second interior doped regions will affect the size of exhaustion region, this
Invention can reach the capacitance of setting by adjusting the doping concentration of the first and second interior doped regions, wherein the first or second
The stability of capacitance can be improved in the configuration of interior doped region again.
In addition, the present invention utilizes groove type structures, component size can be reduced compared to platform and planar configuration and is improved
Technology stability.
Content disclosed above is only preferred possible embodiments of the invention, not thereby limits to right of the invention and wants
The protection scope of book is sought, therefore all equivalence techniques variations done with description of the invention and accompanying drawing content, it is both contained in this hair
In the protection scope of bright claims.
Claims (10)
1. a kind of electric static discharge protector, which is characterized in that the electric static discharge protector includes:
One substrate has a first conductive type, wherein sets in the substrate with a first element area, a second element area and one
Isolated area between the first element area and the second element area；
The second conductive type that one epitaxial layer is set in the substrate, and is different from the first conductive type with one；
One first interior doped region and one second interior doped region are respectively arranged in the first element area and the second element area,
And close to the junction of the substrate and the epitaxial layer, wherein first interior doped region has a second conductive type, and this is in second
Portion's doped region has the first conductive type；
One first top doped region and one second top doped region are respectively arranged in the first element area and the second element area,
And respectively from the surface exposed of the epitaxial layer, wherein first top doped region has the first conductive type, and second top
Doped region has the second conductive type；And
One conductive layer is electrically connected first top doped region and second top doped region.
2. electric static discharge protector according to claim 1, which is characterized in that the electric static discharge protector further includes
One is set to the buffer layer between the substrate and the epitaxial layer, which has the second conductive type, and the first inside doping
Area and second interior doped region are extended further downward into the buffer layer.
3. electric static discharge protector according to claim 1, which is characterized in that first interior doped region and this second
Interior doped region further extends horizontally in the isolated area.
4. electric static discharge protector according to claim 3, which is characterized in that the electric static discharge protector further includes
Multiple insulated trench, at least one insulated trench is set in the isolated area, and extends downwardly through this from the surface of the epitaxial layer
First interior doped region and second interior doped region simultaneously extend in the substrate, and another insulated trench is set to the first element
In area, and first interior doped region being extended downwardly through from the surface of the epitaxial layer and is extended in the substrate, further this is exhausted
Edge groove is set in the second element area, and is extended downwardly through second interior doped region from the surface of the epitaxial layer and extended
Into the substrate.
5. electric static discharge protector according to claim 4, which is characterized in that first interior doped region includes at least
Two partial sectors being separated from each other and at least one between the partial sector and relative to this first top doping
The channel section in area.
6. electric static discharge protector according to claim 1, which is characterized in that the electric static discharge protector further includes
One separation layer, the separation layer are set on the epitaxial layer, which is set on the separation layer, and by the separation layer contact this
One top doped region and second top doped region.
7. electric static discharge protector according to claim 1, which is characterized in that the substrate is with one between 0.001 Europe
Resistivity between nurse-centimetre and 0.13 ohm-cm, the epitaxial layer is with one between 14 ohm-cms and 100 ohm-public affairs
/ resistivity, and have the thickness between 2 microns and 6 microns.
8. electric static discharge protector according to claim 1, which is characterized in that first interior doped region and this second
The width of interior doped region is between 0.5 micron to 10 microns, and doping concentration is between 1E12 atoms/cm to 1E17
Between atoms/cm.
9. electric static discharge protector according to claim 1, which is characterized in that the first conductive type is p-type, and this
Two conductivity types are N-type.
10. electric static discharge protector according to claim 1, which is characterized in that the first conductive type is N-type, and should
The second conductive type is p-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710617014.1A CN109309084A (en) | 2017-07-26 | 2017-07-26 | Electric static discharge protector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710617014.1A CN109309084A (en) | 2017-07-26 | 2017-07-26 | Electric static discharge protector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109309084A true CN109309084A (en) | 2019-02-05 |
Family
ID=65202355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710617014.1A Pending CN109309084A (en) | 2017-07-26 | 2017-07-26 | Electric static discharge protector |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109309084A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101728384A (en) * | 2008-11-03 | 2010-06-09 | 世界先进积体电路股份有限公司 | Protecting component for electrostatic discharge of grid insulating double-junction transistor |
| CN105280631A (en) * | 2014-06-13 | 2016-01-27 | 立锜科技股份有限公司 | Transient voltage suppression device and manufacturing method thereof |
-
2017
- 2017-07-26 CN CN201710617014.1A patent/CN109309084A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101728384A (en) * | 2008-11-03 | 2010-06-09 | 世界先进积体电路股份有限公司 | Protecting component for electrostatic discharge of grid insulating double-junction transistor |
| CN105280631A (en) * | 2014-06-13 | 2016-01-27 | 立锜科技股份有限公司 | Transient voltage suppression device and manufacturing method thereof |
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Application publication date: 20190205 |