TWI615939B - Electrostatic discharge protection component - Google Patents

Abstract

The present invention discloses an electrostatic discharge protection element comprising: a substrate, an epitaxial layer, a first internal doped region, a second internal doped region, a first top doped region, a second top doped region, and a conductive layer. The substrate has a first component region and a second component region. The epitaxial layer is disposed on the substrate, and the first inner doped region and the second inner doped region are respectively disposed in the first device region and the second device region. Adjacent to the junction of the substrate and the epitaxial layer, the first top doped region and the second top doped region are respectively disposed in the first device region and the second device region and are respectively exposed from the surface of the epitaxial layer, and the conductive layer is electrically A first top doped region and a second top doped region are connected. Accordingly, the present invention can effectively reduce the clamping voltage.

Description

Electrostatic discharge protection component

The present invention relates to a semiconductor component, and more particularly to an electrostatic discharge protection component.

The damage of static electricity to electronic products has always been a difficult problem to solve. When an electronic product that is normally operated is subjected to Electrostatic Discharge (ESD), there are often some unstable phenomena, such as a sudden malfunction of the function, etc. It can be removed by booting, and the serious one directly causes damage to the product. In order to ensure the normal operation of electronic products, protective components are often added to electronic products to make them have electrostatic protection capability. When the static electricity exceeds a certain set safety value, the protection components are immediately activated to safely release overvoltage and overcurrent. To ground.

The existing protection components are mainly divided into a platform type (Mesa), a planar type (Planar) and a trench type (Trench) structure, wherein the Mesa structure belongs to a three-dimensional structure, which is disadvantageous to the alignment exposure in the yellow light process and affects the stability of the process. Sex, can not meet the requirements of small size components for line width and photoresist (PR) coating capability. Although the Planar structure can solve the problems caused by steric obstacles, and the line width after yellow light development can also meet the high-precision design requirements of the components, since the Planar structure can only be used for the horizontal design, it must be on the surface of the components. Designing a grounded (Gnd) area, the area of the Planar structure is therefore larger than that of the Mesa structure; in addition, the Planar structure has a weaker antistatic capability than the Mesa structure.

The Trench structure mainly maintains the flatness of the surface of the wafer by digging the trench from the surface and filling the insulating layer, thus improving the capability of the yellow light process, and The Trench structure is also a vertical conduction element as the Mesa structure, so the antistatic capability is much better than the Planar structure, and there is no need to design a Gnd area on the surface of the component to effectively reduce the size of the overall component. However, the Trench structure has a major disadvantage of easily generating a high clamp voltage (Vc), which may affect the operation of the IC component.

The technical problem to be solved by the present invention is to provide an electrostatic discharge protection component that protects the IC component from ESD pulses and ensures that it can operate normally at high frequencies to meet the needs of high frequency transmission.

In order to solve the above technical problem, the technical solution adopted by the present invention is to provide an electrostatic discharge protection component including a substrate, an epitaxial layer, a first internal doping region, a second internal doping region, and a a first top doped region, a second top doped region, and a conductive layer. The substrate has a first conductivity type, and the substrate has a first component region, a second component region, and an isolation region disposed between the first device region and the second device region; the epitaxial layer Is disposed on the substrate and has a second conductivity type different from the first conductivity type; the first internal doping region and the second internal doping region are respectively disposed on the first component region and the second component And adjacent to the junction of the substrate and the epitaxial layer, wherein the first inner doped region has the second conductivity type, and the second inner doped region has the first conductivity type; the first top portion The doped region and the second top doped region are respectively disposed in the first device region and the second device region, and are respectively exposed from a surface of the epitaxial layer, wherein the first top doped region has the first Conductive type, and the second top doped region has the second conductivity type; the conductive layer is electrically connected to the first top doped region and the second top doped region.

Further, the ESD protection device further includes a buffer layer disposed between the substrate and the epitaxial layer, the buffer layer having the second conductivity type, and the first internal doping region and the second internal doping The miscellaneous region extends further down into the buffer layer.

Further, the first inner doped region and the second inner doped region further extend horizontally to the isolation region.

Further, the ESD protection component further includes a plurality of insulating trenches, at least An insulating trench is disposed in the isolation region, and extends downward from a surface of the epitaxial layer through the first inner doped region and the second inner doped region and extends into the substrate, and the other An insulating trench is disposed in the first component region, and extends downward from the surface of the epitaxial layer through the first inner doping region and into the substrate, and the insulating trench is disposed in the second Within the component region, and extending from the surface of the epitaxial layer through the second inner doped region and into the substrate.

Further, the first inner doped region includes at least two partial segments separated from each other and at least one channel segment located between the partial segments and opposite to the first top doped region.

Further, the ESD protection device further includes an isolation layer disposed on the epitaxial layer, the conductive layer is disposed on the isolation layer, and contacts the first top doped region through the isolation layer Second top doped region.

Further, the substrate has a resistivity of between 0.001 Ohm-cm and 0.13 Ohm-cm, the epitaxial layer having a resistivity between 14 Ohm-cm and 100 Ohm-cm, and having a ratio between 2 μm and 6 μm The thickness between.

Further, the width of the first inner doped region and the second inner doped region is between 0.5 μm and 10 μm, and the doping concentration is between 1E12 cm ⁻³ and 1E17 cm ⁻³ .

Taking the PNP structure as an example, the first conductivity type is a P type, and the second conductivity type is an N type.

Taking the NPN structure as an example, the first conductivity type is an N type, and the second conductivity type is a P type.

The utility model has the beneficial effects of the winding type solid electrolytic capacitor package structure and the manufacturing method thereof provided by the technical solution of the present invention, which can be configured by “disposing the first inner doping region and the second inner doping region respectively The element region and the second device region are adjacent to the junction of the substrate and the epitaxial layer, wherein the substrate and the second inner doped region have the same conductivity, and the epitaxial layer has the same conduction as the first inner doped region "Design" to effectively reduce the clamping voltage and improve auto-doping in the process The impact of improving the overall yield.

For a better understanding of the features and technical aspects of the present invention, reference should be made to the accompanying drawings.

Z1, Z2‧‧‧ Electrostatic discharge protection components

1‧‧‧Base

11‧‧‧First component area

12‧‧‧Second component area

13‧‧‧Isolated area

14‧‧‧ first surface

15‧‧‧ second surface

2‧‧‧ epitaxial layer

3‧‧‧First internal doping zone

4'‧‧‧Second top doped area

5‧‧‧Isolation

6‧‧‧First conductive layer

6'‧‧‧Second conductive layer

7‧‧‧ Buffer layer

T1, T2, T3‧‧‧ insulated trench

D1‧‧‧First Controlled PN Dipole

D2‧‧‧Zina diode

31‧‧‧ Sections

32‧‧‧Channel section

3'‧‧‧Second internal doping zone

4‧‧‧First top doped area

D3‧‧‧Second control PN diode

P1, P2‧‧‧ terminals

I _P ‧‧‧Positive current

I _N ‧‧‧negative current

1 is a schematic view showing the structure of a part of an electrostatic discharge protection element according to a first embodiment of the present invention.

2 is a schematic diagram showing an equivalent circuit of a part of an electrostatic discharge protection element according to a first embodiment of the present invention.

Fig. 3 is a schematic structural view showing a part of an electrostatic discharge protection element according to a first embodiment of the present invention.

4 is a schematic diagram showing an equivalent circuit of a portion of an electrostatic discharge protection element according to a second embodiment of the present invention.

The present invention is primarily directed to an electrostatic discharge protection device for a power semiconductor device that utilizes not only a trench structure to reduce component size and process stability, but also an NPN structure to reduce the clamping voltage (Vc). The embodiments of the present invention relating to "electrostatic discharge protection elements" are described below by way of specific embodiments, and those skilled in the art can understand the advantages and effects of the present invention from the disclosure of the present specification. The present invention may be carried out or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention. In addition, the drawings of the present invention are merely illustrative and are not intended to be stated in the actual size. The following embodiments will further explain the related technical content of the present invention, but the disclosure is not intended to limit the scope of the present invention.

[First Embodiment]

Please refer to FIG. 1 , which is a part of an electrostatic discharge protection component according to a first embodiment of the present invention. Schematic diagram of the structure. As shown, the electrostatic discharge protection element Z1 includes a substrate 1, an epitaxial layer 2, a first internal doped region 3, a second internal doped region 3', a first top doped region 4, and a a second top doped region 4', an isolation layer 5, a first conductive layer 6, and a second conductive layer 6'.

In this embodiment, the substrate 1 can be a germanium wafer and has a first conductivity type, wherein the substrate 1 has a first component region 11, a second component region 12, and a first component region 11 and a second component. The isolation region 13 between the regions 12; the epitaxial layer 2 may be formed on the first surface 14 (such as the top surface) of the substrate 1 by epitaxial growth, and has a second conductivity type, wherein the second conductivity type is different from the first conductivity type A conductivity type, for example, when the first conductivity type is P type, the second conductivity type is relatively N type, and the two are also interchangeable. Preferably, the substrate 1 may have a resistivity between 0.001 Ohm-cm and 0.13 Ohm-cm, and the epitaxial layer 2 may have a resistivity between 14 Ohm-cm and 100 Ohm-cm, and the epitaxial layer 2 may have a thickness between 2 μm and 6 μm to allow the component to meet certain conditions (eg, a breakdown voltage of 5V to 24V).

The first inner doped region 3 and the second inner doped region 3 ′ may be formed in the first element region 11 and the second element region 12 by ion implantation (Ion Implant) and thermal diffusion (Thermal Diffusion), respectively. And both are located near the junction of the substrate 1 and the epitaxial layer 2, the first inner doped region 3 has a second conductivity type, and the second inner doped region 3' has a first conductivity type; preferably, the first The width of the second inner doping regions 3, 3' is between 0.5 μm and 10 μm, and the doping concentration is between 1E12 cm ^-3 and 1E17 cm ^-3 .

It should be noted that the substrate 1, the first or second internal doping regions 3, 3' and the epitaxial layer 2 may constitute an NPN structure, and the amplification effect provided by the NPN structure can reduce the overall resistance value of the device and is effective. Lowering the Vc value; alternatively, reducing the Vc value by adjusting the structure and doping concentration of the first and second internal doping regions 3, 3'; further, due to the first and second internal doping regions 3, 3 The change in doping concentration affects the size of the depletion region, so the doping concentration of the first and second internal doping regions 3, 3' can be adjusted to achieve a set capacitance value, wherein the first or second internal doping Zone 3, 3' configuration can be Improve the stability of the capacitance value.

The first top doping region 4 and the second top doping region 4 ′ may be formed by ion implantation in the first device region 11 and the second device region 12 , respectively, and exposed from the surface of the epitaxial layer 2 respectively; The first and second top doped regions 4, 4' may respectively serve as a source region and a collector region of the device, wherein the first top doping region 4 has a first conductivity type, and the doping of the first top doping region 4 The concentration is greater than the doping concentration of the epitaxial layer 2, and the first top doped region 4 and a portion of the first inner doped region 3 overlap each other in the vertical direction (the thickness direction of the epitaxial layer 2) and are maintained at an appropriate position a distance to form a drift region in the epitaxial layer 2; similarly, the second top doped region 4' has a second conductivity type, and the doping concentration of the second top doped region 4' is greater than that of the epitaxial layer 2 The concentration, the second top doped region 4' and a portion of the second inner doped region 3' are also overlapped in the vertical direction (thickness direction of the epitaxial layer 2) and maintained at an appropriate distance from each other to be epitaxial A drift region is formed in layer 2.

The isolation layer 5 can be formed on the epitaxial layer 2 by various methods well known to those skilled in the art, and avoids the covered areas of the first and second top doped regions 4, 4', that is, the isolation layer 5 has an opening (not The label) is used to expose the first and second top doped regions 4, 4'. The first conductive layer 6 and the second conductive layer 6' may be formed by various methods well known to those skilled in the art as electrodes of the element, wherein the first conductive layer 6 is disposed on the isolation layer 5 and contacts the first and the first The top doped regions 4, 4' are electrically connected to the high voltage side of the regulated power supply (such as a 5V power supply), and the second conductive layer 6' is disposed on the second surface 15 (such as the bottom surface) of the substrate 1 to Electrically connect another component that is protected (such as an IC component).

A second conductivity type buffer layer 7 may be further formed between the substrate 1 and the epitaxial layer 2, and the first and second internal doping regions 3, 3' extend downward into the buffer layer 7; the epitaxial layer 2 The buffer layer 7 can be simultaneously formed on the substrate 1 by epitaxial growth, wherein the buffer layer 7 is thinner than the epitaxial layer 2, and the doping concentration is smaller than the doping concentration of the epitaxial layer 2.

Referring to FIG. 1 and FIG. 2 together, in the electrostatic discharge protection device Z1, the P-type and the N-type are the first conductivity type and the second conductivity type, and the substrate 1, the epitaxial layer 2, and the first interior The doped region 3 and the first top doped region 4 may form a first steering PN diode D1 and a Zener diode coupled in series with the first steering PN diode D1 in the first component region 11. a body D2 (Zener diode), and the substrate 1, the epitaxial layer 2, the second inner doped region 3' and the second top doped region 4' may constitute a second control PN dipole in the second element region 12. The body D3, wherein the second steering PN diode D3 is coupled in parallel with the combination of the first steering PN diode D1 and the Zener diode D2.

Further, the electrostatic discharge protection element Z1 uses a plurality of insulating trenches T1, T2, T3 (filled with insulating material in the trench) to form a portion of the epitaxial layer 2 of the first steering PN diode D1 and form the first The second control is isolated from another portion of the epitaxial layer 2 of the PN diode D3, and the insulating trenches T1, T2, T3 contribute to form the Zener diode D2; specifically, at least one insulating trench T1 Disposed in the isolation region 13 and extending downward from the surface of the epitaxial layer 2 into the substrate 1. If the first and second internal doping regions 3, 3' extend further horizontally into the isolation region 13, the insulating trench T1 extends downward from the surface of the epitaxial layer 2 through the first and second inner doped regions 3, 3' and into the substrate 1, and the other insulating trench T2 is disposed in the first element region 11, and The surface of the epitaxial layer 2 extends downward through the first inner doped region 3 and into the substrate 1, and another insulating trench T3 is disposed in the second element region 12 and downward from the surface of the epitaxial layer 2. It extends through the second inner doped region 3' and extends into the substrate 1.

It should be noted that although the number of the insulating trenches T1 disposed in the isolation region 13 is two, the number and position of the insulating trenches T1 may be changed according to actual needs. The number of insulating trenches T1 shown in Figure 1 is for illustrative purposes only and is not intended to limit the invention.

When positive electrostatic discharge (ESD) occurs, the generated positive current I _P will flow from the terminal P1 connecting the first conductive layer 6 through the first steering PN diode D1 and the Zener diode D2 to the connection. Terminal P2 of the second conductive layer 6'; since the terminal P1 is forced to a larger positive voltage with respect to the terminal P2, and the first steering PN diode D1 is forward biased and the Zener diode D2 is reversed Offset, so the first steering PN diode D1 can fix the maximum voltage between the terminals P1, P2 to a Zener voltage (such as 5V) approximately equal to the Zener diode D2 to protect the components at the back end. Destroyed by ESD. When the reverse ESD occurs, the generated negative current I _N will flow from the terminal P2 through the second steering PN diode D3 to the terminal P1, and the second biased PN diode D3 which is forward biased can be safe. The reverse ESD pulse is processed.

[Second embodiment]

3 is a cross-sectional view showing a portion of an electrostatic discharge protection element according to a second embodiment of the present invention. As shown, the difference between this embodiment and the first embodiment is mainly that the first inner doped region 3 in the electrostatic discharge protection element Z1 includes at least two partial segments 31 separated from each other and at least one portion located therein. The remaining technical details are the same as those of the first embodiment with respect to the channel section 32 between the sections 31 and with respect to the first top doped area 4, and the detailed description thereof will not be repeated here.

Referring to FIG. 3 and FIG. 4 together, the P-type and the N-type are the first conductivity type and the second conductivity type, and the substrate 1, the epitaxial layer 2, the first internal doping region 3 and the first top doping region 4 are used. A first steering PN diode D1, a Zener diode D2 and a second steering PN diode D3 can be formed in the first component region 11, wherein the Zener diode D2 and the second steering direction The PN diode D3 is coupled in parallel, and the first control PN diode D1 is coupled in series with the combination of the Zener diode D2 and the second steering PN diode D3; in addition, the substrate 1, the epitaxial layer 2 The second inner doped region 3' and the second top doped region 4' may constitute another second controlled PN diode D3 in the second element region 12, and the second controlled PN diode D3 is The combination of the first control PN diode D1, the Zener diode D2 and the second steering PN diode D3 is coupled in parallel.

It is worth noting that when positive electrostatic discharge (ESD) occurs, the generated positive current I _P can flow from the terminal P1 through the first steering PN diode D1 and the Zener diode D2 to the terminal P2. The terminal P1 can pass through the first steering PN diode D1 and the second steering PN diode D3 to the terminal P2; accordingly, the electrostatic discharge protection component Z1 can utilize not only the voltage stabilizing characteristic of the Zener diode D2 To protect the components of the back end, the negative resistance effect can also be used to reduce the Vc value.

[Advantageous Effects of Embodiments]

The electrostatic discharge protection device provided by the embodiment of the invention can be configured to “dispose the first inner doped region and the second inner doped region in the first device region and the second device region, respectively, and close to the substrate and the epitaxial layer The junction of the layers, wherein the substrate and the second inner doped region have the same conductivity, and the epitaxial layer has the same conductivity as the first inner doped region, can effectively reduce the clamping voltage and improve the process The effect of auto-doping improves the overall yield.

In view of the above, the present invention can also reduce the Vc value by adjusting the structure and doping concentration of the first and second internal doping regions.

Furthermore, since the doping concentration variation of the first and second internal doping regions affects the size of the depletion region, the present invention can achieve the set capacitance value by adjusting the doping concentrations of the first and second internal doping regions. Wherein the configuration of the first or second internal doped regions in turn increases the stability of the capacitance value.

In addition, the present invention utilizes a trench structure that reduces component size and improves process stability compared to platform and planar structures.

The above disclosure is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Therefore, any equivalent technical changes made by using the present specification and the contents of the drawings are included in the application of the present invention. Within the scope of the patent.

Z1‧‧‧Electrostatic Discharge Protection Element

1‧‧‧Base

11‧‧‧First component area

12‧‧‧Second component area

13‧‧‧Isolated area

14‧‧‧ first surface

15‧‧‧ second surface

2‧‧‧ epitaxial layer

3‧‧‧First internal doping zone

3'‧‧‧Second internal doping zone

4‧‧‧First top doped area

4'‧‧‧Second top doped area

5‧‧‧Isolation

6‧‧‧First conductive layer

6'‧‧‧Second conductive layer

7‧‧‧ Buffer layer

T1, T2, T3‧‧‧ insulated trench

P1, P2‧‧‧ terminals

I _P ‧‧‧Positive current

I _N ‧‧‧negative current

Claims (9)

An electrostatic discharge protection device comprising: a substrate having a first conductivity type, wherein the substrate has a first component region, a second component region, and a first component region and the second component region An isolation region; an epitaxial layer disposed on the substrate and having a second conductivity type different from the first conductivity type; a first internal doped region and a second internally doped region, respectively Provided in the first component region and the second component region, and close to the junction of the substrate and the epitaxial layer, wherein the first internal doping region has the second conductivity type, and the second internal doping The region has the first conductivity type; a first top doped region and a second top doped region are respectively disposed in the first device region and the second device region, and are respectively exposed from the surface of the epitaxial layer The first top doped region has the first conductivity type, and the second top doped region has the second conductivity type; a conductive layer electrically connected to the first top doped region and the second top portion a doped region; and a buffer layer disposed between the substrate and the epitaxial layer, wherein the buffer Having the second conductivity type layer, and the first inner and the second doped region extends further down to the inner region of the doped buffer layer. The electrostatic discharge protection device of claim 1, wherein the first inner doped region and the second inner doped region extend further horizontally into the isolation region. The electrostatic discharge protection device of claim 1, further comprising a plurality of insulating trenches, at least one of the insulating trenches being disposed in the isolation region and extending downward from the surface of the epitaxial layer through the first interior a doped region and the second inner doped region extend into the substrate, and the other insulating trench is disposed in the first element region and extends downward from the surface of the epitaxial layer through the first inner portion Doping regions and extending into the substrate, and then An insulating trench is disposed in the second component region and extends downwardly from the surface of the epitaxial layer through the second inner doped region and into the substrate. The electrostatic discharge protection element of claim 3, wherein the first inner doped region comprises at least two partial segments separated from each other and at least one is located between the partial segments and is doped with respect to the first top The channel section of the miscellaneous zone. The electrostatic discharge protection device of claim 1, further comprising an isolation layer disposed on the epitaxial layer, the conductive layer being disposed on the isolation layer and contacting the first top doping through the isolation layer a miscellaneous region and the second top doped region. The electrostatic discharge protection device according to claim 1, wherein the substrate has a resistivity of between 0.001 Ohm-cm and 0.13 Ohm-cm, and the epitaxial layer has a relationship between 14 Ohm-cm and 0100 Ohm-cm. The resistivity and has a thickness of between 2 μm and 6 μm. The electrostatic discharge protection device of claim 1, wherein the first inner doped region and the second inner doped region have a width of between 0.5 μm and 10 μm and a doping concentration of 1E12 cm ^-3 Between 1E17 cm ^-3 . The electrostatic discharge protection device of claim 1, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The electrostatic discharge protection device of claim 1, wherein the first conductivity type is an N type, and the second conductivity type is a P type.