CN109309071A - 集成扇出型封装 - Google Patents

集成扇出型封装 Download PDF

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Publication number
CN109309071A
CN109309071A CN201710778117.6A CN201710778117A CN109309071A CN 109309071 A CN109309071 A CN 109309071A CN 201710778117 A CN201710778117 A CN 201710778117A CN 109309071 A CN109309071 A CN 109309071A
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Prior art keywords
layer
integrated circuit
scaling powder
conductive
line structure
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CN201710778117.6A
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Inventor
陈威宇
谢静华
刘重希
林修任
张家纶
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN109309071A publication Critical patent/CN109309071A/zh
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Abstract

提供一种集成扇出型封装，所述集成扇出型封装包括集成电路组件、绝缘包封体、重布线路结构及多个导电端子。所述绝缘包封体在侧向上包封所述集成电路组件的侧壁。所述重布线路结构设置在所述绝缘包封体及所述集成电路组件上。所述重布线路结构电连接到所述集成电路组件且所述重布线路结构包括多个球接垫。所述导电端子中的每一者包括导电球及环形助焊剂结构，其中所述导电球中的每一者设置在所述球接垫中的一个上且电连接到所述球接垫中的所述一个。所述环形助焊剂结构中的每一者设置在所述重布线路结构上。所述环形助焊剂结构中的每一者围绕所述导电球的底部部分设置且接触所述导电球的所述底部部分。还提供一种制作集成扇出型封装的方法。

Description

集成扇出型封装
技术领域
本发明的实施例涉及一种集成扇出型封装。
背景技术
由于各种电子组件(即，晶体管、二极管、电阻器、电容器等)的集成密度的持续提高，半导体行业已经历快速发展。在很大程度上，集成密度的此种提高来自于最小特征大小(minimum feature size)的持续减小，此使得更多较小的组件能够集成到给定区域中。这些较小的电子组件也需要与先前的封装相比利用较小区域的较小的封装。半导体组件的一些较小类型的封装包括方形扁平封装(quad flat package，QFP)、引脚栅阵列(pin gridarray，PGA)封装、球栅阵列(ball grid array，BGA)封装等等。
当前，集成扇出型封装因其紧凑性而正变得日渐流行。在包括被模制化合物(molding compound)包封的至少一个芯片的集成扇出型封装中，制作在模制化合物上的重布线路结构与形成在所述重布线路结构上的导电端子之间的电连接的可靠性可能因在所述重布线路结构中的导电层与介电层之间的界面处发生的层离(delamination)而劣化。如何提高集成扇出型封装的制作良率(yield rate)受到高度关注。
发明内容
根据本发明的一些实施例，提供一种集成扇出型封装，所述集成扇出型封装包括集成电路组件、绝缘包封体、重布线路结构及多个导电端子。所述绝缘包封体在侧向上包封所述集成电路组件的侧壁。所述重布线路结构设置在所述绝缘包封体及所述集成电路组件上。所述重布线路结构电连接到所述集成电路组件且所述重布线路结构包括多个球接垫。所述导电端子中的每一者包括导电球及环形助焊剂结构，其中所述导电球中的每一者设置在所述球接垫中的一个上且电连接到所述球接垫中的所述一个。所述环形助焊剂结构中的每一者设置在所述重布线路结构上。所述环形助焊剂结构中的每一者围绕所述导电球的底部部分设置且接触所述导电球的所述底部部分。
根据本发明的替代性实施例，提供一种集成扇出型封装，所述集成扇出型封装包括集成电路组件、绝缘包封体、重布线路结构及多个导电端子。所述绝缘包封体在侧向上包封所述集成电路组件的侧壁。所述重布线路结构设置在所述绝缘包封体及所述集成电路组件上。所述重布线路结构电连接到所述集成电路组件。所述重布线路结构包括交替堆叠的多个重布线导电层与多个层间界电层，所述重布线导电层中的最顶部的一个重布线导电层被所述层间界电层中的最顶部的一个层间界电层覆盖，所述重布线导电层中的所述最顶部的一个重布线导电层包括多个球接垫，且所述层间界电层中的所述最顶部的一个层间界电层包括与所述球接垫对应的多个接触开口。所述导电端子中的每一者包括导电球环形助焊剂结构。所述导电球中的每一者设置在所述球接垫中的一个上且电连接到所述球接垫中的所述一个。所述环形助焊剂结构中的每一者围绕所述导电球的底部部分设置。所述环形助焊剂结构中的每一者填充所述导电球的所述底部部分与所述重布线路结构之间的空间。所述环形助焊剂结构中的每一者包括第一接合表面及第二接合表面，所述第一接合表面接触所述导电球的所述底部部分，所述第二接合表面接触所述重布线路结构。
根据本发明的又一些替代性实施例，提供一种制作集成扇出型封装的方法。所述方法包括以下步骤。在载体上提供集成电路组件。在所述载体上形成绝缘包封体，以包封所述集成电路组件的侧壁。在所述集成电路组件及所述绝缘包封体上形成重布线路结构，其中所述重布线路结构电连接到所述集成电路组件，且所述重布线路结构包括多个球接垫。在所述重布线路结构上形成助焊剂材料，其中所述助焊剂材料是围绕所述球接垫形成。将多个导电球放置在所述球接垫上。通过执行回焊工艺将所述导电球与所述球接垫进行接合，以从所述助焊剂材料形成多个环形助焊剂结构，其中所述环形助焊剂结构设置在所述重布线路结构上，所述环形助焊剂结构中的每一者分别围绕所述导电球中的一个的底部部分设置且接触所述导电球中的所述一个的所述底部部分。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1至图13说明制作根据一些实施例的集成扇出型封装的工艺流程。
图14是说明根据一些实施例的叠层封装(package-on-package，POP)结构的剖视图。
[符号的说明]
100：晶片
100’：薄化晶片
110：半导体衬底
110a：半导体衬底
110’：薄化半导体衬底
120：导电接垫
130、130a：钝化层
132：接触开口
140、140a：后钝化层
142：接触开口
150：导电柱
160、160a、160a’：保护层
200：集成电路
210：绝缘材料
210’：绝缘包封体
220：前侧重布线路结构
222：层间介电层
222a、222b：接触开口
224：重布线导电层
240、260：导电球
250：表面安装装置
300：半导体装置
BS1：第一接合表面
BS2：第二接合表面
C：载体
DB：剥离层
DI：介电层
E：电极
F1、F3：助焊剂材料
F2：环形助焊剂结构
F4：环形助焊剂结构
O：接触开口
P1：球接垫
P2：连接接垫
S：焊料
TV：导电穿孔
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开内容。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对性描述语可同样相应地进行解释。
也可包括其他特征及工艺。举例来说，可包括测试结构，以帮助对三维(3D)封装或三维集成电路(3DIC)装置进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试接垫(test pad)，所述测试接垫使得能够对三维封装或三维集成电路进行测试、对探针及/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外，本文中所公开的结构及方法可结合包括对已知良好管芯进行中间验证的测试方法而使用，以提高良率并降低成本。
图1至图13说明制作根据一些实施例的集成扇出型封装的工艺流程，且图14是说明根据一些实施例的叠层封装(POP)结构的剖视图。
参照图1，提供包括排列成阵列的多个管芯(die)或集成电路200的晶片100。在对晶片100执行晶片切割工艺(wafer dicing process)之前，晶片100的集成电路200是彼此实体连接的。在一些实施例中，晶片100包括半导体衬底110、形成在半导体衬底110上的多个导电接垫120及钝化层(passivation layer)130。钝化层130形成在半导体衬底110之上且具有多个接触开口132，进而使得导电接垫120被钝化层130的接触开口132局部地暴露出。举例来说，半导体衬底110可为硅衬底，所述硅衬底包括形成在所述硅衬底中的有源组件(例如，晶体管等)及无源组件(例如，电阻器、电容器、电感器等)；导电接垫120可为铝接垫、铜接垫或其他适合的金属接垫；且钝化层130可为氧化硅层、氮化硅层、氮氧化硅层或由其他适合的介电材料形成的介电层。
如图1中所示，在一些实施例中，晶片100可视情况包括形成在钝化层130之上的后钝化层(post-passivation layer)140。后钝化层140覆盖钝化层130且具有多个接触开口142。被钝化层130的接触开口132所局部地暴露出的导电接垫120会被后钝化层140的接触开口142局部地暴露出。举例来说，后钝化层140可为聚酰亚胺(polyimide，PI)层、聚苯并恶唑(polybenzoxazole，PBO)层或由其他适合的介电聚合物形成的介电层。
参照图2，在晶片100的导电接垫120上形成多个导电柱150。在一些实施例中，通过导电材料的镀覆工艺(plating process)在导电接垫120上形成导电柱150。以下详细阐述导电柱150的镀覆工艺。首先，将晶种层沉积(例如，通过溅镀(sputtering))到后钝化层140及被接触开口142所暴露出的导电接垫120上。接着通过旋转涂布(spin coating)光刻胶材料层、烘烤(baking)所述光刻胶材料层及光刻(photolithography)(即，曝光工艺(exposure process)与显影工艺(development process))在晶种层之上形成具有预定图案的图案化光刻胶层(图中未示出)。晶种层的与导电接垫120对应的部分被图案化光刻胶层暴露出。接着，将包括形成在晶片100上的图案化光刻胶层的晶片100浸入至镀覆槽(plating bath)中，进而使得导电柱150镀覆在晶种层的与导电接垫120对应的所述部分上且被图案化光刻胶层显露出。在形成导电柱150之后，通过例如蚀刻(etching)、灰化(ash)或其他适合的移除工艺剥除图案化光刻胶层。此后，利用导电柱150作为硬掩模，例如通过刻蚀移除晶种层未被导电柱150所覆盖的另一部分直至暴露出后钝化层140为止。
在一些实施例中，导电柱150为经镀覆铜柱或其他适合的金属柱。在一些替代性实施例中，导电柱150为被焊料顶盖(solder cap)(例如，不含铅的焊料顶盖)覆盖的铜柱或其他适合的金属柱。
参照图3，在形成导电柱150之后，在晶片100的后钝化层140上形成保护层160，进而使得导电柱150被保护层160覆盖。在一些实施例中，保护层160可为具有足以包封及保护导电柱150的厚度的聚合物层。在一些实施例中，保护层160可为聚苯并恶唑(PBO)层、聚酰亚胺(PI)层或其他适合的聚合物层。在一些替代实施例中，保护层160可由无机材料制成。如图3中所示，保护层160具有实质上平坦的顶表面且保护层160的最大厚度大于导电柱150的高度。
参照图4，在形成保护层160之后，可视需要对晶片100的背表面执行背侧研磨工艺(back side grinding process)。在所述背侧研磨工艺期间，局部地研磨半导体衬底110，进而使得形成包括薄化半导体衬底110’的薄化晶片100’。在一些实施例中，可通过机械研磨或其他适合的研磨工艺或抛光工艺(polishing process)研磨晶片100的背表面。
参照图5，在执行背侧研磨工艺之后，对薄化晶片100’执行晶片切割工艺，进而使得薄化晶片100’中的集成电路200彼此单体化。经单体化的集成电路200中的每一者可包括半导体衬底110a、形成在半导体衬底110a上的导电接垫120、钝化层130a、后钝化层140a、导电柱150及保护层160a。如图4及图5中所示，半导体衬底110a、钝化层130a、后钝化层140a及保护层160a的材料及特性与半导体衬底110、钝化层130、后钝化层140及保护层160的材料及特性相同。因此，为简洁起见，本文中不再对半导体衬底110a、钝化层130a、后钝化层140a及保护层160a予以赘述。
如图4及图5中所示，在背侧研磨工艺及晶片切割工艺期间，保护层160及160a可妥善地保护集成电路200的导电柱150。另外，保护层160及160a可保护集成电路200的导电柱150不被例如集成电路200的拾取及放置工艺(pick-up and placing process)、模制工艺(molding process)等依序执行的工艺损坏。
参照图6，在集成电路200从薄化晶片100’(在图4中示出)被单体化之后，提供上面形成有剥离层(de-bonding layer)DB及介电层DI的载体C，其中剥离层DB位于载体C与介电层DI之间。在一些实施例中，载板C可为玻璃衬底，剥离层DB可为形成在所述玻璃衬底上的光-热转换(light-to-heat conversion，LTHC)释放层，且介电层DI可为形成在剥离层DB上的聚苯并恶唑(PBO)层。
在提供上面形成有剥离层DB及介电层DI的载体C之后，在介电层DI上形成多个导电穿孔TV。在一些实施例中，通过旋转涂布光刻胶材料层、烘烤所述光刻胶材料层、光刻(即，曝光工艺与显影工艺)、镀覆(例如，电镀(electro-plating)或无电镀覆(electro-less plating))及光刻胶剥除工艺形成所述多个导电穿孔TV。举例来说，导电穿孔TV包括铜柱(copper post)或其他适合的金属柱。
在一些实施例中，在形成导电穿孔TV之前，可在由载体C所承载的介电层DI上形成背侧重布线路结构(图中未示出)，且导电穿孔TV可形成在所述背侧重布线路结构上且电连接到所述背侧重布线路结构。
如图6中所示，在一些实施例中，拾取集成电路200中包括形成于其上的导电接垫120、导电柱150及保护层160a的一个集成电路200并且放置在由载体C所承载的介电层DI上。通过管芯贴合膜(die attach film，DAF)(图中未示出)、粘合膏(adhesion paste)等将集成电路200贴合或粘合在介电层DI上。在一些替代实施例中，拾取集成电路200中的两个或更多个集成电路200并且放置在由载体C所承载的介电层DI上，其中放置在介电层DI上的集成电路200可排列成阵列。在一些实施例中，当放置在介电层DI上的集成电路200排列成阵列时，可将导电穿孔TV分类成多个群组。集成电路200的数目对应于导电穿孔TV的群组的数目。
如图6中所示，保护层160a的顶表面低于导电穿孔TV的顶表面。然而，本发明并不仅限于此。在一些替代性实施例中，保护层160a的顶表面可与导电穿孔TV的顶表面实质上对齐。在又一些替代性实施例中，保护层160a的顶表面可高于导电穿孔TV的顶表面，且导电柱150的顶表面可低于、高于导电穿孔TV的顶表面或与导电穿孔TV的所述顶表面实质上对齐。
如图6中所示，在形成导电穿孔TV之后将集成电路200拾取及放置在介电层DI上。然而，本发明并不仅限于此。在一些替代性实施例中，在形成导电穿孔TV之前将集成电路200拾取及放置在介电层DI上。
参照图7，在介电层DI上形成绝缘材料210以覆盖集成电路200及导电穿孔TV。在一些实施例中，绝缘材料210是通过模制工艺而形成的模制化合物。集成电路200的导电柱150及保护层160a被绝缘材料210覆盖。换句话说，集成电路200的导电柱150及保护层160a不被绝缘材料210显露出且被绝缘材料210妥善地保护。在一些实施例中，绝缘材料210包括环氧树脂或其他适合的介电材料。
参照图8，接着研磨绝缘材料210直至暴露出导电柱150的顶表面、导电穿孔TV的顶表面及保护层160a的顶表面为止。在一些实施例中，通过机械研磨工艺及/或化学机械抛光(chemical mechanical polishing，CMP)工艺研磨绝缘材料210。在研磨绝缘材料210之后，在介电层DI之上形成绝缘包封体210’。在绝缘材料210的研磨工艺期间，研磨保护层160a的部分以形成保护层160a’。在一些实施例中，在绝缘材料210及保护层160a的研磨工艺期间，也会略微研磨导电穿孔TV的部分及导电柱150的部分。
如图8中所示，绝缘包封体210’在侧向上包封集成电路200的侧壁，且绝缘包封体210’被导电穿孔TV穿透。换句话说，集成电路200及导电穿孔TV嵌于绝缘包封体210’中。应注意，导电穿孔TV的顶表面、绝缘包封体210’的顶表面及导电柱150的顶表面与保护层160a’的顶表面实质上共面。
参照图9，在形成绝缘包封体210’及保护层160a’之后，在导电穿孔TV的顶表面、绝缘包封体210’的顶表面、导电柱150的顶表面及保护层160a’的顶表面上形成与集成电路200的导电柱150以及导电穿孔TV电连接的前侧重布线路结构220。所制作出的将前侧重布线路结构220与位于其下方的一个或多个连接件电连接。此处，前述连接件可为上述背侧重布线路结构、集成电路200的导电柱150及/或嵌于绝缘包封体210’中的导电穿孔TV。将结合图9来详细阐述前侧重布线路结构220。
参照图9，前侧重布线路结构220包括交替堆叠的多个层间介电层(inter-dielectric layer)222与多个重布线导电层224，且重布线导电层224电连接到集成电路200的导电柱150及嵌于绝缘包封体210’中的导电穿孔TV。导电柱150的顶表面及导电穿孔TV的顶表面被层间介电层222中的最底部的一个层间介电层222局部地覆盖。重布线导电层224中的最顶部的一个重布线导电层224被层间介电层222中的最顶部的一个层间介电层222局部地覆盖，其中重布线导电层224中的最顶部的一个重布线导电层224包括多个球接垫P1且层间介电层222中的最顶部的一个层间介电层222包括与球接垫P1对应的多个接触开口222a。
参照图10，在形成前侧重布线路结构220之后，执行植球工艺(ball placementprocess)。在执行植球工艺之前，可不需要事先在球接垫P1上形成球下金属(under-ballmetallurgy)。因此，集成扇出型封装的制作复杂度及制作成本可降低。以下将详细阐述植球工艺。
植球工艺可包括以下步骤。在前侧重布线路结构220上形成助焊剂材料F1，接着将多个导电球240(例如，焊料球)放置在球接垫P1上。在一些实施例中，可在将导电球240放置在球接垫P1上之前形成助焊剂材料F1。在一些替代性实施例中，可在将导电球240放置在球接垫P1上之后形成助焊剂材料F1。如图10中所示，助焊剂材料F1形成在重布线导电层224中的最顶部的一个的顶表面上且围绕球接垫P1分布；助焊剂材料F1可在接触开口222a外部分布且助焊剂材料F1可通过助焊剂分配工艺(flux dispensing process)、助焊剂印刷工艺(flux printing process)或其他适合的工艺形成在前侧重布线路结构220上；并且导电球240的位置可由接触开口222a来限定。在一些实施例中，助焊剂材料F1可为不含氮化物的环氧系助焊剂膏且助焊剂材料F1中的固含量可介于约10％至约50％范围内。举例来说，助焊剂材料F1可为包括酚醛树脂、酸酐树脂等的环氧系助焊剂。在一些替代性实施例中，助焊剂材料F1可为液态的不含氮化物的环氧系助焊剂且助焊剂材料F1中的固含量可介于约10％至约50％范围内。
在一些替代性实施例中，重布线导电层224中的最顶部的一个重布线导电层224可进一步包括多个连接接垫P2，层间介电层222中的最顶部的一个层间介电层222可进一步包括与连接接垫P2对应的多个接触开口222b，且另一助焊剂材料F3可形成在前侧重布线路结构220上且围绕接触开口222b分布。举例来说，助焊剂材料F1与助焊剂材料F3是相同的材料且可通过同一种工艺形成。如图10中所示，在连接接垫P2上提供至少一个表面安装装置250(例如，无源组件)。举例来说，表面安装装置250包括电极E及形成在表面安装装置250的电极E上的焊料S。
参照图11，执行热工艺(thermal process)或回焊工艺(reflow process)来加热助焊剂材料F1及导电球240，进而使得导电球240与球接垫P1进行接合。在上述热工艺或回焊工艺期间，助焊剂材料F1被加热且充当化学清洁剂(chemical cleaning agent)、流动剂(flowing agent)及/或净化剂(purifying agent)，以促进导电球240与球接垫P1之间的金属接合。此外，执行热工艺来加热助焊剂材料F3及焊料S，进而使得表面安装装置250的电极E与连接接垫P2通过焊料S进行接合。在上述热工艺期间，助焊剂材料F3被加热且充当化学清洁剂、流动剂及/或净化剂，以促进焊料S与连接接垫P2之间的金属接合。
在执行上述热工艺或回焊工艺之后，助焊剂材料F1转变成多个环形助焊剂结构F2且助焊剂材料F3转变成环形助焊剂结构F4。如图11中所示，环形助焊剂结构F2中的每一者的外轮廓可为圆形的。然而，环形助焊剂结构F2中的每一者的外轮廓并不限于此。尽管环形助焊剂结构F2是由助焊剂材料F1制成，但环形助焊剂结构F2的组成不同于助焊剂材料F1的组成。在一些实施例中，环形助焊剂结构F2的材料包括不含氮化物的环氧系助焊剂(例如，酚醛树脂)；不含氮化物的环氧系助焊剂的玻璃转变温度(Tg)可介于约60摄氏度到约180摄氏度范围内；及/或不含氮化物的环氧系助焊剂的杨氏模量可介于约4GPa到约10GPa范围内。在此种实施例中，不含氮化物的环氧系助焊剂在低于玻璃转变温度(Tg)的第一温度下所测量的热膨胀系数(α1-CTE)可介于约30到约60范围内，而环氧系助焊剂在高于玻璃转变温度(Tg)的第二温度下所测量的热膨胀系数(α2-CTE)可介于约100到约160范围内。
如图11中所示，在执行植球工艺之后，形成与球接垫P1进行接合的多个导电端子。导电端子中的每一者包括导电球240及环形助焊剂结构F2中的一者，其中环形助焊剂结构F2中的每一者分别围绕导电球240的底部部分设置且接触导电球240的所述底部部分。在一些实施例中，环形助焊剂结构F2中的每一者填充对应导电球240的底部部分与前侧重布线路结构220之间的空间，其中环形助焊剂结构F2中的每一者包括第一接合表面BS1及第二接合表面BS2，第一接合表面BS1接触对应导电球240的底部部分，第二接合表面BS2接触前侧重布线路结构220。举例来说，环形助焊剂结构F2中的每一者可对应地延伸至其中一个接触开口222a(在图10中示出)。由于环形助焊剂结构F2中的每一者填充对应导电球240的底部部分与前侧重布线路结构220之间的空间，因此可增强导电球240的接合可靠性且可防止最顶部的重布线导电层224与最顶部的层间介电层222之间发生层离。
如图11中所示，环形助焊剂结构F4包封焊料S且局部地覆盖表面安装装置250的电极E。
在一些实施例中，可将环形助焊剂结构F2称作助焊剂材料F1的残留物，且环形助焊剂结构F2是在热工艺期间通过助焊剂材料F1与导电球240的反应而形成。可将环形助焊剂结构F4称作助焊剂材料F3的残留物，且环形助焊剂结构F4是在热工艺期间通过助焊剂材料F3与焊料S的反应而形成。
参照图11及图12，在前侧重布线路结构220上安装导电球240及表面安装装置250之后，使形成在介电层DI的所得产物从剥离层DB剥离，进而使得所得产物及介电层DI从载体C分离。在一些实施例中，可通过紫外(UV)激光照射剥离层DB(例如，所述光-热转换释放层)，进而使得介电层DI从载体C脱落(peel)。
如图12中所示，接着将介电层DI图案化以形成多个接触开口O，进而暴露出导电穿孔TV的底表面。接触开口O的数目及位置对应于导电穿孔TV的数目。在一些实施例中，通过激光钻孔工艺(laser drilling process)或其他适合的图案化工艺形成介电层DI的接触开口O。
参照图13，在介电层DI中形成接触开口O之后，将多个导电球260放置在导电穿孔TV被接触开口O暴露出的底表面上。并且，举例来说，对导电球260进行回焊以使导电球260与导电穿孔TV的底表面进行接合。如图13中所示，在形成导电球240及导电球260之后，具有双侧端子设计(即，导电球240及260)的集成电路200的集成扇出型封装便已初步制作完成。
参照图14，接着提供另一半导体装置300(例如，表面安装型封装)。在一些实施例中，半导体装置300为例如存储器装置或其他适合的半导体装置。半导体装置300堆叠在图12中所示集成扇出型封装之上并通过导电球260电连接到所述集成扇出型封装，进而制作出叠层封装(POP)结构。
在上述实施例中，环形助焊剂结构F2及环形助焊剂结构F4会增强导电球240与球接垫P1之间的接合强度。因此，集成扇出型封装的可靠性增强。
根据本发明的一些实施例，提供一种集成扇出型封装，所述集成扇出型封装包括集成电路组件、绝缘包封体、重布线路结构及多个导电端子。所述绝缘包封体在侧向上包封所述集成电路组件的侧壁。所述重布线路结构设置在所述绝缘包封体及所述集成电路组件上。所述重布线路结构电连接到所述集成电路组件且所述重布线路结构包括多个球接垫。所述导电端子中的每一者包括导电球及环形助焊剂结构，其中所述导电球中的每一者设置在所述球接垫中的一个上且电连接到所述球接垫中的所述一个。所述环形助焊剂结构中的每一者设置在所述重布线路结构上。所述环形助焊剂结构中的每一者围绕所述导电球的底部部分设置且接触所述导电球的所述底部部分。
根据本发明的一些实施例，所述重布线路结构包括交替堆叠的多个重布线导电层与多个层间界电层，所述层间界电层中的最顶部的一个层间界电层包括与所述球接垫对应的多个接触开口，所述导电端子的所述环形助焊剂结构设置在所述层间界电层中的所述最顶部的一个层间界电层上且接触所述层间界电层中的所述最顶部的一个层间界电层。
根据本发明的一些实施例，所述导电球的材料包括焊料。
根据本发明的一些实施例，所述环形助焊剂结构的材料包括不含氮化物的环氧系助焊剂。
根据本发明的一些实施例，所述环氧系助焊剂的玻璃转变温度(Tg)介于约60摄氏度到约180摄氏度范围内。
根据本发明的一些实施例，所述环氧系助焊剂的杨氏模量介于约4GPa到约10GPa范围内。
根据本发明的一些实施例，所述环氧系助焊剂的第一热膨胀系数(α1-CTE)介于约30到约60范围内，所述环氧系助焊剂的第二热膨胀系数(α2-CTE)介于100到180范围内，所述第一热膨胀系数(α1-CTE)是在低于所述玻璃转变温度的温度下测量，且所述第二热膨胀系数(α2-CTE)是在高于所述玻璃转变温度的温度下测量。
根据本发明的替代性实施例，提供一种集成扇出型封装，所述集成扇出型封装包括集成电路组件、绝缘包封体、重布线路结构及多个导电端子。所述绝缘包封体在侧向上包封所述集成电路组件的侧壁。所述重布线路结构设置在所述绝缘包封体及所述集成电路组件上。所述重布线路结构电连接到所述集成电路组件。所述重布线路结构包括交替堆叠的多个重布线导电层与多个层间界电层，所述重布线导电层中的最顶部的一个重布线导电层被所述层间界电层中的最顶部的一个层间界电层覆盖，所述重布线导电层中的所述最顶部的一个重布线导电层包括多个球接垫，且所述层间界电层中的所述最顶部的一个层间界电层包括与所述球接垫对应的多个接触开口。所述导电端子中的每一者包括导电球环形助焊剂结构。所述导电球中的每一者设置在所述球接垫中的一个上且电连接到所述球接垫中的所述一个。所述环形助焊剂结构中的每一者围绕所述导电球的底部部分设置。所述环形助焊剂结构中的每一者填充所述导电球的所述底部部分与所述重布线路结构之间的空间。所述环形助焊剂结构中的每一者包括第一接合表面及第二接合表面，所述第一接合表面接触所述导电球的所述底部部分，所述第二接合表面接触所述重布线路结构。
根据本发明的一些实施例，所述环形助焊剂结构接触所述层间界电层中的所述最顶部的一个层间界电层并延伸到所述接触开口中。
根据本发明的一些实施例，所述导电球的材料包括焊料。
根据本发明的一些实施例，所述环形助焊剂结构的材料包括不含氮化物的环氧系助焊剂。
根据本发明的一些实施例，所述环氧系助焊剂的玻璃转变温度(Tg)介于约60摄氏度到约180摄氏度范围内。
根据本发明的一些实施例，所述环氧系助焊剂的杨氏模量介于约4GPa到约10GPa范围内。
根据本发明的一些实施例，所述环氧系助焊剂的第一热膨胀系数(α1-CTE)介于约30到约60范围内，所述环氧系助焊剂的第二热膨胀系数(α2-CTE)介于100到180范围内，所述第一热膨胀系数(α1-CTE)是在低于所述玻璃转变温度的温度下测量，且所述第二热膨胀系数(α2-CTE)是在高于所述玻璃转变温度的温度下测量。
根据本发明的又一些替代性实施例，提供一种制作集成扇出型封装的方法。所述方法包括以下步骤。在载体上提供集成电路组件。在所述载体上形成绝缘包封体，以包封所述集成电路组件的侧壁。在所述集成电路组件及所述绝缘包封体上形成重布线路结构，其中所述重布线路结构电连接到所述集成电路组件，且所述重布线路结构包括多个球接垫。在所述重布线路结构上形成助焊剂材料，其中所述助焊剂材料是围绕所述球接垫形成。将多个导电球放置在所述球接垫上。通过执行回焊工艺将所述导电球与所述球接垫进行接合，以从所述助焊剂材料形成多个环形助焊剂结构，其中所述环形助焊剂结构设置在所述重布线路结构上，所述环形助焊剂结构中的每一者分别围绕所述导电球中的一个的底部部分设置且接触所述导电球中的所述一个的所述底部部分。
根据本发明的一些实施例，所述助焊剂材料包括不含氮化物的环氧系助焊剂，且所述助焊剂材料中的固含量介于约10％到约50％范围内。
根据本发明的一些实施例，所述环形助焊剂结构的材料包括不含氮化物的环氧系助焊剂。
根据本发明的一些实施例，所述环氧系助焊剂的玻璃转变温度(Tg)介于约60摄氏度到约180摄氏度范围内。
根据本发明的一些实施例，所述环氧系助焊剂的杨氏模量介于约4GPa到约10GPa范围内。
根据本发明的一些实施例，所述环氧系助焊剂的第一热膨胀系数(α1-CTE)介于约30到约60范围内，所述环氧系助焊剂的第二热膨胀系数(α2-CTE)介于100到180范围内，所述第一热膨胀系数(α1-CTE)是在低于所述玻璃转变温度的温度下测量，且所述第二热膨胀系数(α2-CTE)是在高于所述玻璃转变温度的温度下测量。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应理解，其可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本发明的精神及范围，而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (1)

1.一种集成扇出型封装，其特征在于，包括：
集成电路组件；
绝缘包封体，在侧向上包封所述集成电路组件的侧壁；
重布线路结构，设置在所述绝缘包封体及所述集成电路组件上，所述重布线路结构电连接到所述集成电路组件，所述重布线路结构包括多个球接垫；
多个导电端子，所述导电端子中的每一者包括：
导电球，设置在所述球接垫中的一个上且电连接到所述球接垫中的所述一个；以及
环形助焊剂结构，设置在所述重布线路结构上，其中所述环形助焊剂结构围绕所述导电球的底部部分设置且接触所述导电球的所述底部部分。
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