CN109308677A - Picture processing chip and image processing system - Google Patents
Picture processing chip and image processing system Download PDFInfo
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- CN109308677A CN109308677A CN201710616092.XA CN201710616092A CN109308677A CN 109308677 A CN109308677 A CN 109308677A CN 201710616092 A CN201710616092 A CN 201710616092A CN 109308677 A CN109308677 A CN 109308677A
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- 238000010168 coupling process Methods 0.000 claims abstract description 13
- 238000005859 coupling reaction Methods 0.000 claims abstract description 13
- 230000005540 biological transmission Effects 0.000 claims description 27
- 230000009471 action Effects 0.000 claims description 6
- 230000004044 response Effects 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 4
- 230000006870 function Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
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- 238000004519 manufacturing process Methods 0.000 description 3
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
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Abstract
The present invention provides a kind of picture processing chip and image processing system.Picture processing chip includes one first image end, one second image end, an image procossing block and a multiplexer.First image end receives at least one first image data package.Image procossing block is to be converted at least one second image data package at least one first image data package.Multiplexer has a first input end of the first image end of coupling, couples the second input terminal of image procossing block and couples an output end of the second image end.When operating in a first mode, multiplexer couples first input end and output end, so that at least one first image data package is sent to the second image end by the first image end by multiplexer.
Description
Technical field
The present invention relates to a kind of picture processing chip and image processing system more particularly to a kind of utilization tandem package transmissions
The picture processing chip and image processing system of interface.
Background technique
In known technical field, the high-speed transmission interface transmitted by way of tandem package has high pass
The advantages of defeated rate and low transmission foot position.For increase data transmission reliability, can also in the way of differential wave come
It is transmitted, to reduce the influence of electromagnetic interference (Electromagnetic Interference, EMI).On the other hand, for
For certain image processing systems, generally require to strengthen image quality by additional picture processing chip or to original image
Carry out additional image procossing, such as noise suppression or depth calculation etc..However, in certain application situations, at image
Reason chip does not need to carry out image procossing and is only responsible for the original image received being transmitted to another processing chip.
In order to which raw image data is sent to another processing chip, it is known that the practice include in picture processing chip
The input terminal of image processing engine and output end add a bypass, allow well raw image data can around image processing engine and
Do not change.However, the transmission interface controller of picture processing chip still receives power supply supply and is in enable under this practice
State, to solve the raw image data that packetized and packetized are transmitted via tandem package transmission interface.
Summary of the invention
The present invention provides a kind of picture processing chip and image processing system, can low cost reach in picture processing chip
The interior function of carrying out signal bypass.
Picture processing chip of the invention, including one first image end, one second image end, an image procossing block and one
Multiplexer.First image end receives at least one first image data package.Image procossing block couples the first image end, to incite somebody to action
At least one first image data package is converted at least one second image data package.Multiplexer has the first image end of coupling
One first input end, the second input terminal for coupling image procossing block and the output end for coupling the second image end.When operating in
When one first mode, multiplexer couples first input end and output end, so that at least one first image data package passes through multiplexing
Device is sent to the second image end by the first image end.When operating in a second mode, multiplexer couple the second input terminal with it is defeated
Outlet, so that at least one second image data package is sent to the second image end by image procossing block by multiplexer.
Image processing system of the invention, including an image sensor, an application processor and a picture processing chip.Figure
As sensor exports at least one first image data package according to an interface transfer protocol.One control of application processor output refers to
It enables.Picture processing chip is coupled between image sensor and application processor, picture processing chip include one first image end,
One second image end, an image procossing block and a multiplexer.First image end couples image sensor, to receive at least 1 the
One image data package.Second image end couples application processor.Image procossing block couples the first image end, to will at least
One first image data package is converted at least one second image data package.Multiplexer has the one the of the first image end of coupling
One input terminal, the second input terminal for coupling image procossing block and the output end for coupling the second image end.When image procossing core
When piece operates in a first mode in response to control instruction, multiplexer couples first input end and output end, so that at least 1 the
One image data package is sent to the second image end by the first image end by multiplexer.When picture processing chip is in response to control
When instruction operates in a second mode, multiplexer couples the second input terminal and output end, so that at least one second image data is sealed
Packet is sent to the second image end by image procossing block by multiplexer.
Based on above-mentioned, the picture processing chip and image processing system of the embodiment of the present invention, the image of the embodiment of the present invention
Processing chip achievees the effect that bypassing whole image handles block by single multiplexer, also can increase manufacture slightly at
Reach the function that signal bypass is carried out in picture processing chip in the case where sheet and board area.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is the schematic diagram of the image processing system of an embodiment according to the present invention；
Fig. 2 is the schematic diagram of the image processing system of an embodiment according to the present invention；
Fig. 3 is the schematic diagram of the package format of the image data package of an embodiment according to the present invention.
Drawing reference numeral explanation:
10,20: image processing system
11: image sensor
13: application processor
100,200: picture processing chip
110,210: image procossing block
211: receiving interface physical layer
212: receiving interface controller
213,215: buffer
214: image processing module
216: transmission interface controller
217: transmission interface entities layer
300: image data package
310: packet header
310a, 310b, 310c: package field
320: valid data
330: package mark tail
Cmd: control instruction
D1: raw image data
D2: through handling image data
EI1: the first image end
EI2: the second image end
MX1: multiplexer
P1: the first image data package
P2: the second image data package
Specific embodiment
Fig. 1 is the schematic diagram of the image processing system of an embodiment according to the present invention.Fig. 1 is please referred to, in the present embodiment,
Image processing system 10 include image sensor 11, application processor 13 and image procossing (Image Signal Processor,
ISP) chip 100.Picture processing chip 100 couples image sensor 11 and application processor 13, and including image procossing area
Block 110, multiplexer MX1, the first image end EI1 and the second image end EI2.
Picture processing chip 100 couples image sensor 11 to receive at least one first image of the offer of image sensor 11
Data packet P1.Picture processing chip 100 couples application processor 13, with offer at least one first image data package P1 or extremely
Few one second image data package P2 receives the control instruction cmd of the offer of application processor 13 to application processor 13, with
Accordingly operate in first mode or second mode.
First image end EI1 couples image sensor 11, to receive at least one first image of the offer of image sensor 11
Data packet P1.Image procossing block 110 couples the first image end EI1, to receive at least one first by the first image end EI1
Image data package P1, and at least one first image data package P1 is converted at least one second image data package P2.
The first input end of multiplexer MX1 couples the first image end EI1, to receive at least one first image data package P1, multiplexer
The second input terminal of MX1 couples image procossing block 110, to receive at least one second image data package P2, and multiplexer
The output end of MX1 couples the second image end EI2.Second image end EI2 is coupled to application processor 13, to provide at least one first
Image data package P1 or at least one second image data package P2 are to application processor 13.
When picture processing chip 100 operates in first mode, multiplexer MX1 couples first input end and output end, also
I.e. the first image end EI1 is coupled directly to the second image end EI2 by multiplexer MX1, so that at least one first image data is sealed
It wraps P1 and the second image end EI2 is conveyed directly to by the first image end EI1 by multiplexer MX.In other words, work as picture processing chip
100 when operating in first mode, image procossing block 110 can bypassed (bypass) so that image procossing block 110 is not required to
It is to be used, that is, at least one first image data package P1 will not be by by handling, wherein first mode can be considered at image
Manage the bypass data mode of chip 100.
When picture processing chip 100 operates in second mode, multiplexer MX2 couples the second input terminal and output end, also
That is the first image end EI1 is coupled to the second image end EI2 by image procossing block 110, so that image procossing block 110 is near
Few one first image data package P1 is converted at least one second image data package P2, and at least one second image data is sealed
Packet P2 can be sent to the second image end EI2 by image procossing block 110 by multiplexer MX1.In other words, work as picture processing chip
100 when operating in second mode, and image procossing block 110 can handle at least one first image data package P1 and generate at least one
Second image data package P2, wherein second mode can be considered the data processing mode of picture processing chip 100.
According to above-mentioned, the picture processing chip of the embodiment of the present invention reaches bypass whole image processing by single multiplexer
The effect of block, can also reach in the case where increasing manufacturing cost and board area slightly picture processing chip into
The function of row signal bypass.
In addition, in embodiments of the present invention, when picture processing chip 100 operates in first mode, due to image procossing
The needs that block does not start, therefore image procossing block 110 can be set to power down (power down) power domain, also
Power domain locating for image procossing block 110 is set as power down power domain.When picture processing chip 10 operates in second mode
When, since image procossing block need to be to be used, power domain locating for image procossing block can be set as powering on
(power up) power domain.Whereby, when picture processing chip 100 operates in first mode, only multiplexer MX1 can consume electricity
Power, the power consumption of picture processing chip 100 is greatly reduced.
In an embodiment of the present invention, image processing system 10 can be by multiple electronic components in an action electronic device
And it forms.Above-mentioned action electronic device is, for example, the electronics that smart phone, tablet computer or digital camera etc. have camera function
Device.Image sensor 11 may include camera lens and photosensitive element.Photosensitive element is, for example, charge coupled cell (Charge
Coupled Device, CCD), Complimentary Metal-Oxide semiconductor (Complementary Metal-Oxide
Semiconductor, CMOS) element or other elements, image sensor 11 may also include apertures elements etc., the embodiment of the present invention
It is not limited.
Application processor (Application Processor, AP) 13 is to operate various functions and its peripheral equipment such as
Image sensor, display or memory etc..Application processor 13 can be by using integrated circuit (Integrated
Circuit, IC) or System on Chip/SoC (System On Chip, SoC) implement, the embodiment of the present invention is not limited.Also,
Picture processing chip 100 is a kind of chip with image-capable, can receive external image data and provides at image
Function is managed, and is consequently adapted to be set in image acquiring device or image display device.For example, picture processing chip 100
Can have the function of noise suppression, depth calculation, image intensification etc., the present invention is not intended to limit this.In general, image procossing core
Piece 100 can be interconnected via various coffret and other chips or electronic component, and according to corresponding interface transfer protocol
Carry out the exchange and transmission of image data.
Fig. 2 is the schematic diagram of the image processing system of an embodiment according to the present invention.Please refer to Fig. 1 and Fig. 2, image procossing
System 20 is approximately identical to image processing system 10, the difference is that the image procossing block of picture processing chip 200
210, wherein same or similar element uses same or similar label.Also, it below will be using interface transfer protocol as action industry
It is illustrated for processor interface (Mobile Industry Processor Interface, MIPI) agreement, but this hair
Bright embodiment is not limited.Furthermore, it is understood that image sensor 11 is according to MIPI agreement output at least one first picture number
According to package P1 to picture processing chip 200, and application processor 13 is reached an agreement on by defined MIPI and MIPI interface and figure
As processing chip 200 is communicated.
In the present embodiment, image procossing block 210 include receiving interface physical layer 211, receiving interface controller 212,
Buffer 213, image processing module 214, buffer 215, transmission interface controller 216, transmission interface entities layer 217.It receives
Interface entities layer 211, which couples the first image end EI1 and reaches an agreement on according to MIPI, receives at least one first image data package P1.It receives
Interface controller 212 couples receiving interface physical layer 211.Buffer 213 couples receiving interface controller 212.Image procossing mould
Block 214 is coupled between buffer 213 and buffer 215, that is, is coupled to receiving interface controller 212 and transmission Interface Controller
Between device 216.It transmits interface controller 216 and couples buffer 215.Transmit the coupling transmission interface controller of interface entities layer 217
216, and couple the second input terminal of multiplexer MX1.
When picture processing chip 200, which is based on MIPI agreement, is linked up with image sensor 11 and application processor 13,
Receiving interface physical layer 211 and transmission interface entities layer 217 can be MIPI D-PHY circuit, and the MIPI D-PHY electricity
Road may include a period of time Maitong road (clock lane) and an at least data channel (data lane).Also, receiving interface controller
Interface between 212 and receiving interface physical layer 211 can be physical layer agreement interface (Physical defined in MIPI agreement
Protocol Interface, PPI), and the interface between transmission interface controller 216 and transmission interface entities layer 217
PPI defined in can reaching an agreement on for MIPI.
In the present embodiment, when picture processing chip 200 operates in first mode in response to control instruction cmd, until
Few one first image data package P1 is conveyed directly to the second image end EI2 by the first image end EI1 by multiplexer MX1.When
When picture processing chip 200 operates in second mode in response to control instruction cmd, at least one first image data package P1 warp
Image procossing is carried out by image procossing block 210.
Furthermore, it is understood that receiving interface physical layer 211 receives at least one first image data envelope by the first image end EI1
Wrap P1.Then, receiving interface controller 212 receives at least one first image data package P1 simultaneously from receiving interface physical layer 211
It solves packetized at least one first image data package P1 and obtains raw image data D1, wherein receiving interface controller 212 can
According to MIPI agreement solution packetized at least one first image data package P1, raw image data D1 is exported to buffer
213 are cached, and buffer 213 can be line buffer.
Image processing module 214 obtains raw image data D1 from buffer 213, then carries out to raw image data D1
Image procossing and generate through handle image data D2, wherein image processing module 214 may include one or more image processing engines
With data lines (data pipeline), generated with carrying out image procossing to raw image data D1 through handling image data
D2.Image processing module 214 can will be sent to buffer 215 through processing image data D2 and cache, and wherein buffer 215 can
Think line buffer.
Transmission interface controller 216 is received from buffer 215 through processing image data D2 and packetized is through handling picture number
At least one second image data package P2 is generated according to D2, causes to transmit the transmission of interface entities layer 217 at least one second picture number
According to package P2 to application processor 13.
Fig. 3 is the schematic diagram of the package format of the image data package of an embodiment according to the present invention.Referring to figure 3., exist
In the present embodiment, MIPI reach an agreement on standardized image data package 300 include packet header (Packet Header, PH) 310,
Valid data (Payload data) 320 and package mark tail (Packet Footer, PF) 330.Therefore, receiving interface controls
Device 212 can reach an agreement on standardized package format solution packetized at least one first image data package P1 according to MIPI, and obtain accordingly
Take the valid data at least one first image data package P1, and image processing module 214 can to raw image data D1 into
Row image procossing.In addition, packet header 310 includes package field 310a, 310b and 310c.Package field 310a stores image
The identification code of date (Data Identifier, DI) of data packet 300, package field 310b store image data package 300
Serial data sum (Word Count, WC), package field 310c store the bug patch code (Error of image data package 300
Correction Code, ECC).Similar, transmission interface controller 216 can be according to the package format envelope that MIPI reaches an agreement on standardized
Bao Huajing handles image data D2 and generates at least one second image data package P2.It should be noted that example shown in Fig. 3 with
It is only exemplary illustrated to modify identification code of date, is not intended to limit the invention.
In conclusion the picture processing chip and image processing system of the embodiment of the present invention, the image of the embodiment of the present invention
Processing chip achievees the effect that bypassing whole image handles block by single multiplexer, also can increase manufacture slightly at
Reach the function that signal bypass is carried out in picture processing chip in the case where sheet and board area.Also, work as image procossing
Chip operation, due to the needs that image procossing block does not start, image procossing block can be arranged when first mode
In power down power domain, also power domain locating for image procossing block can be set as power down power domain.Whereby, work as image procossing
For chip operation when first mode, only multiplexer can consume electric power, the power consumption of picture processing chip is greatly reduced.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field
Middle technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore protection of the invention
Subject to range ought be defined depending on claim.
Claims (10)
1. a kind of picture processing chip characterized by comprising
First image end receives at least one first image data package；
Second image end；
Image procossing block, couple the first image end, to by at least one first image data package be converted to
Few one second image data package；And
Multiplexer has the second input of the first input end, coupling described image processing block at coupling the first image end
Hold and couple the output end of second image end；
Wherein, when operating in first mode, the multiplexer couples the first input end and the output end, so that described
At least one first image data package is sent to second image end by the first image end by the multiplexer, works as behaviour
When making in second mode, the multiplexer couples second input terminal and the output end, so that at least one second figure
Second image end is sent to as data packet handles block by described image by the multiplexer.
2. picture processing chip according to claim 1, which is characterized in that described when operating in the first mode
Image procossing block is in power down power domain, and when operating in the second mode, described image processing block, which is in, powers on electricity
Power domain.
3. picture processing chip according to claim 2, which is characterized in that described image handles block and includes:
Receiving interface physical layer couples the first image end and receives at least one first figure according to an interface transfer protocol
As data packet；
Receiving interface controller couples the receiving interface physical layer；
Interface entities layer is transmitted, second input terminal of the multiplexer is coupled；
Interface controller is transmitted, the transmission interface entities layer is coupled；And
Image processing module is coupled between the receiving interface controller and the transmission interface controller,
Wherein, when operating in the second mode, the receiving interface controller is from described in receiving interface physical layer reception
At least one first image data package simultaneously solves at least one first image data package described in packetized and obtains raw image data,
Described image processing module carries out image procossing to the raw image data and generates and handled image data, and the transmission connects
Mouthful controller receives described through being generated described at least one second described in processing image data and packetized through processing image data
Image data package causes the transmission interface entities layer to transmit at least one second image according to the interface transfer protocol
Data packet.
4. picture processing chip according to claim 3, which is characterized in that the interface transfer protocol is action Enterprise Administration Office
Manage the agreement of device interface.
5. picture processing chip according to claim 1, which is characterized in that the first image end couples image sensing
Device, to receive at least one first image data package described in the offer of described image sensor.
6. picture processing chip according to claim 1, which is characterized in that described image handles chip according to application processing
The control instruction that device provides operates in the first mode or the second mode.
7. a kind of image processing system characterized by comprising
Image sensor exports at least one first image data package according to interface transfer protocol；
Application processor exports control instruction；And
Picture processing chip is coupled between described image sensor and the application processor, and described image handles chip packet
It includes:
First image end couples described image sensor, to receive at least one first image data package；
Second image end couples the application processor；
Image procossing block, couple the first image end, to by at least one first image data package be converted to
Few one second image data package；And
Multiplexer has the second input of the first input end, coupling described image processing block at coupling the first image end
Hold and couple the output end of second image end；
Wherein, when described image processing chip operates in first mode in response to the control instruction, the multiplexer coupling
The first input end and the output end, so that at least one first image data package is by the multiplexer by described
First image end is sent to second image end, when described image processing chip operates in second in response to the control instruction
When mode, the multiplexer couples second input terminal and the output end, so that at least one second image data is sealed
Packet handles block by described image by the multiplexer and is sent to second image end.
8. image processing system according to claim 7, which is characterized in that described when operating in the first mode
Image procossing block is in power down power domain, and when operating in the second mode, described image processing block, which is in, powers on electricity
Power domain.
9. image processing system according to claim 7, which is characterized in that described image handles block and includes:
Receiving interface physical layer couples the first input end and receives described at least one first according to the interface transfer protocol
Image data package；
Receiving interface controller couples the receiving interface physical layer；
Interface entities layer is transmitted, second input terminal is coupled；
Interface controller is transmitted, the transmission interface entities layer is coupled；And
Image processing module is coupled between the receiving interface controller and the transmission interface controller,
Wherein, when operating in the second mode, the receiving interface controller is from described in receiving interface physical layer reception
At least one first image data package simultaneously solves at least one first image data package described in packetized and obtains raw image data,
Described image processing module carries out image procossing to the raw image data and generates and handled image data, and the transmission connects
Mouthful controller receives described through being generated described at least one second described in processing image data and packetized through processing image data
Image data package causes the transmission interface entities layer to transmit at least one second image according to the interface transfer protocol
Data packet.
10. image processing system according to claim 9, which is characterized in that the interface transfer protocol is action industry
Processor interface agreement.
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| CN201710616092.XA CN109308677A (en) | 2017-07-26 | 2017-07-26 | Picture processing chip and image processing system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710616092.XA CN109308677A (en) | 2017-07-26 | 2017-07-26 | Picture processing chip and image processing system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113763906A (en) * | 2020-06-05 | 2021-12-07 | 格科微电子（上海）有限公司 | Image signal processing device, terminal |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050007373A1 (en) * | 2003-07-08 | 2005-01-13 | Lim Ricardo Te | Graphics controller providing flexible access to a graphics display device by a host |
| CN101018179A (en) * | 2007-03-07 | 2007-08-15 | 今创集团有限公司 | Data bus bridge and its working method |
| CN104516841A (en) * | 2013-10-02 | 2015-04-15 | 三星电子株式会社 | System on chip including configurable image processing pipeline, and system including the same |
| CN106303152A (en) * | 2015-05-25 | 2017-01-04 | 聚晶半导体股份有限公司 | Picture processing chip and image processing system |
-
2017
- 2017-07-26 CN CN201710616092.XA patent/CN109308677A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050007373A1 (en) * | 2003-07-08 | 2005-01-13 | Lim Ricardo Te | Graphics controller providing flexible access to a graphics display device by a host |
| CN101018179A (en) * | 2007-03-07 | 2007-08-15 | 今创集团有限公司 | Data bus bridge and its working method |
| CN104516841A (en) * | 2013-10-02 | 2015-04-15 | 三星电子株式会社 | System on chip including configurable image processing pipeline, and system including the same |
| CN106303152A (en) * | 2015-05-25 | 2017-01-04 | 聚晶半导体股份有限公司 | Picture processing chip and image processing system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113763906A (en) * | 2020-06-05 | 2021-12-07 | 格科微电子（上海）有限公司 | Image signal processing device, terminal |
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