CN109300921A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN109300921A CN109300921A CN201811362562.5A CN201811362562A CN109300921A CN 109300921 A CN109300921 A CN 109300921A CN 201811362562 A CN201811362562 A CN 201811362562A CN 109300921 A CN109300921 A CN 109300921A
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- metal
- metal routing
- overlapping portion
- array substrate
- routing
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- 239000000758 substrate Substances 0.000 title claims abstract description 45
- 239000002184 metal Substances 0.000 claims abstract description 178
- 229910052751 metal Inorganic materials 0.000 claims abstract description 178
- 239000010410 layer Substances 0.000 description 50
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 239000010409 thin film Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- NCMAYWHYXSWFGB-UHFFFAOYSA-N [Si].[N+][O-] Chemical class [Si].[N+][O-] NCMAYWHYXSWFGB-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4822—Beam leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02373—Layout of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02375—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
A kind of array substrate, including viewing area and non-display area, non-display area includes that multiple groups are fanned out to cabling, it includes being superposed and the first metal routing insulated from each other, the second metal routing and third metal routing that every group, which is fanned out to cabling, second metal routing includes the first overlapping portion and the second overlapping portion, first overlapping portion partly overlaps with the first metal routing for being fanned out to cabling with third metal routing, and the first metal routing that the second overlapping portion is fanned out to cabling with adjacent another group partly overlaps with third metal routing.Array substrate of the invention is able to achieve narrow frame, while mentioning high display quality.The invention further relates to a kind of display panels.
Description
Technical field
The present invention relates to display technology field, in particular to a kind of array substrate and display panel.
Background technique
Fig. 1 a is the structural schematic diagram of an existing array substrate.Fig. 1 b is the structural representation of another existing array substrate
Figure.As illustrated in figs. 1A and ib, array substrate has effective display area and non-display area.Configured with multiple in effective display area
For pixel to form pixel array, non-display area is then equipped with perimeter circuit.Each pixel generally comprises at least thin film transistor (TFT) (Thin
Film Transistor, TFT) and thin film transistor (TFT) connection pixel electrode, and each pixel is adjacent by two
Scan line and two adjacent data lines surround.These scan lines and data line extend to non-display from effective display area
Area, and be electrically connected by the perimeter circuit of non-display area with driving chip.Perimeter circuit is by the one of connection scan line and data line
It holds to driving chip region and concentrates and constitute and be fanned out to cabling.
Since the metal routing being fanned out in cabling is relatively more, required wiring space is big, cause the frame of array substrate without
Method narrows.By alternately or being superimposed the first metal layer M1 and second metal layer M2 of distribution and reducing wiring space, although can be with
The frame of array substrate is set to become smaller, but frame diminution is limited.Moreover, the first metal layer M1 and second metal layer M2 are in interlayer pair
It is easy to appear offset when the processing procedure of position, causes the capacitance difference of interlayer excessive, influences to show quality.
Summary of the invention
In view of this, the present invention provides a kind of array substrate, it is able to achieve narrow frame, while mentioning high display quality.
A kind of array substrate, including viewing area and non-display area, non-display area include that multiple groups are fanned out to cabling, and every group is fanned out to away
Line includes being superposed and the first metal routing insulated from each other, the second metal routing and third metal routing, the second metal are walked
Line includes the first overlapping portion and the second overlapping portion, the first overlapping portion and the first metal routing and third metal routing that are fanned out to cabling
It partly overlaps, the first metal routing and third metal routing part weight that the second overlapping portion is fanned out to cabling with adjacent another group
It is folded.
In an embodiment of the present invention, above-mentioned second metal routing further includes interconnecting piece, and the interconnecting piece is connected to described
Between first overlapping portion and second overlapping portion.
In an embodiment of the present invention, above-mentioned interconnecting piece is connected to the end of first overlapping portion and second overlapping portion
Portion.
In an embodiment of the present invention, above-mentioned first overlapping portion is parallel to second overlapping portion, first overlapping portion
It is equal to the overlap length of first metal routing, the third metal routing and second overlapping portion and first gold medal
Belong to the overlap length of cabling, the third metal routing.
In an embodiment of the present invention, above-mentioned non-display area is provided with the first metal layer, second metal layer and third metal
Layer；
The first metal layer includes at least one the first metal routings；
The second metal layer includes at least one the second metal routings；
The third metal layer includes at least one third metal routing.
In an embodiment of the present invention, above-mentioned non-display area is provided with the first insulating layer and second insulating layer, and described first
Insulating layer is set between the first metal layer and the second metal layer, and the second insulating layer is set to second gold medal
Belong between layer and the third metal layer.
In an embodiment of the present invention, above-mentioned array substrate further includes underlay substrate, and the first metal layer is arranged in institute
It states on underlay substrate, first insulating layer is arranged on the first metal layer and the underlay substrate.
In an embodiment of the present invention, above-mentioned first metal routing, second metal routing and the third metal are walked
The metal line width of line is equal, and the spacing of first metal routing and second metal routing is equal to second metal routing
With the spacing of the third metal routing, the weight of first overlapping portion and second overlapping portion and first metal routing
Folded width is equal to the line width of 1/3 first metal routing, first overlapping portion and second overlapping portion and the third
The overlapping widths of metal routing are equal to the line width of the 1/3 third metal routing.
In an embodiment of the present invention, above-mentioned viewing area includes a plurality of signal lead, and the non-display area includes driving core
Piece is fanned out to cabling described in multiple groups and is electrically connected between the signal lead and the driving chip.
The present invention also provides a kind of display panels, including above-mentioned array substrate.
The non-display area of array substrate of the invention includes that multiple groups are fanned out to cabling, every group be fanned out to cabling include be superposed and
First metal routing, the second metal routing and third metal routing insulated from each other, the second metal routing include the first overlapping portion
With the second overlapping portion, the first overlapping portion partly overlaps with the first metal routing for being fanned out to cabling with third metal routing, the second weight
The first metal routing that folded portion is fanned out to cabling with adjacent another group partly overlaps with third metal routing.Of the invention is fanned out to away
The area of non-display area shared by line can be reduced, realize narrow frame, while can compensate because OVL deviate caused by layer capacitance difference
Property, the RC Loading between the first metal routing, the second metal routing and third metal routing is effectively reduced, improves display
Quality.
Detailed description of the invention
Fig. 1 a is the structural schematic diagram of an existing array substrate.
Fig. 1 b is the structural schematic diagram of another existing array substrate.
Fig. 2 is the positive structure diagram of array substrate of the invention.
Fig. 3 is the broken section structural schematic diagram of array substrate shown in Fig. 2.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to implementation of the invention
Mode is further described.
Fig. 2 is the positive structure diagram of array substrate of the invention.Fig. 3 is the partial cutaway of array substrate shown in Fig. 2
Depending on structural schematic diagram.As shown in Figures 2 and 3, array substrate 100 includes viewing area 10 and non-display area 20.
Viewing area 10 includes a plurality of signal lead 11, and a plurality of signal lead 11 may include for providing gate drive signal
Multi-strip scanning line, the multiple data lines for providing display data signal and for providing the touch drive signal line of touching signals
Deng.Configured with multiple pixels to form pixel array in viewing area 10, each pixel includes at least thin film transistor (TFT) (Thin
Film Transistor, TFT) and thin film transistor (TFT) connection pixel electrode, and each pixel is adjacent by two
Scan line and two adjacent data lines surround.
Non-display area 20 includes that multiple groups are fanned out to cabling 21 and driving chip 22.It is fanned out to cabling 21 and is electrically connected at signal lead
Between 11 and driving chip 22.It includes being superposed and the first metal routing 212, second insulated from each other that every group, which is fanned out to cabling 21,
Metal routing 213 and third metal routing 214, the second metal routing 213 are located at the first metal routing 212 and third metal routing
Between 214.Specifically, the first metal routing 212, one end of the second metal routing 213 and third metal routing 214 and signal are walked
Line 11 connects, the other end and driving chip 22 of the first metal routing 212, the second metal routing 213 and third metal routing 214
Connection, can specifically be electrically connected with the pad of driving chip 22.Illustratively, referring to fig. 2, the one of the first metal routing 212
End is connect with data line, and the other end of the first metal routing 212 is connect with driving chip 22；One end of second metal routing 213
It is connect with data line, the other end of the second metal routing 213 is connect with driving chip 22；One end of third metal routing 214 with
Data line connection, the other end of third metal routing 214 are connect with driving chip 22.
As shown in figure 3, array substrate 100 further includes underlay substrate 23, the first insulating layer 24 and second insulating layer 25.Multiple groups
Be fanned out to cabling 21 to be located on underlay substrate 23, specifically, the first metal layer M1 be formed on underlay substrate 23, using exposure,
Developing process forms at least one the first metal routings 212 on the first metal layer M1；It is arranged first on the first metal layer M1
Second metal layer M2 is arranged in insulating layer 24 on the first insulating layer 24, using exposure, developing process shape on second metal layer M2
At at least one the second metal routings 213；Second insulating layer 25 is sequentially formed on second metal layer M2, in second insulating layer
Third metal layer M3 is set on 25, forms at least one third metal on third metal layer M3 using exposure, developing process and walks
Line 214, wherein the first insulating layer 24, between the first metal layer M1 and second metal layer M2, second insulating layer 25 is located at second
Between metal layer M2 and third metal layer M3；Third insulating layer is also formed on third metal layer M3.
In the present embodiment, the first metal routing 212, the second metal routing 213 and third metal routing 214 can be by gold
Belong to material (such as silver, copper) to be made, and its constituent material can be the same or different from each other.
First insulating layer 24 is gate insulation layer, and material can be Si oxide, silicon nitride or silicon nitrogen oxides, but not
It is limited to this, general gate insulator layer material；Second insulating layer 25 and third insulating layer are protective layer, and material can be oxygen
SiClx, silicon nitride or organic material.
As shown in Figures 2 and 3, in the present embodiment, the second metal routing 213 includes the first overlapping portion 213a, the second weight
Folded portion 213b and interconnecting piece 213c.Interconnecting piece 213c is connected between the first overlapping portion 213a and the second overlapping portion 213b, and first
Overlapping portion 213a partly overlaps with the first metal routing 212 for being fanned out to cabling 21 with third metal routing 214, the second overlapping portion
The first metal routing 212 that 213b is fanned out to cabling 21 with adjacent another group partly overlaps with third metal routing 214.
In a preferred embodiment, the first overlapping portion 213a and the second overlapping portion 213b mutually stagger setting, wherein the
One overlapping portion 213a and the first metal routing 212 are Chong Die with the latter half of third metal routing 214 (along being fanned out to cabling 21
Length direction), the second overlapping portion 213b and the first metal routing 212 it is Chong Die with the first half of third metal routing 214 (along
It is fanned out to the length direction of cabling 21).
In a preferred embodiment, interconnecting piece 213c is connected to the end of the first overlapping portion 213a and the second overlapping portion 213b
Portion, and interconnecting piece 213c is perpendicular to the first overlapping portion 213a and the second overlapping portion 213b.
In a preferred embodiment, the first overlapping portion 213a is parallel to the second overlapping portion 213b, the first overlapping portion 213a
It is equal to the second overlapping portion 213b and the first metal routing with the overlap length of the first metal routing 212, third metal routing 214
212, the overlap length of third metal routing 214.
In a preferred embodiment, the first metal routing 212, the second metal routing 213 and third metal routing 214
Metal line width is equal, and the spacing of the first metal routing 212 and the second metal routing 213 is equal to the second metal routing 213 and third
The spacing of metal routing 214, the overlapping widths etc. of the first overlapping portion 213a and the second overlapping portion 213b and the first metal routing 212
In the line width of 1/3 first metal routing 212, the first overlapping portion 213a and the second overlapping portion 213b and third metal routing 214
Overlapping widths are equal to the line width of 1/3 third metal routing 214, at this time the first metal routing 212, the second metal routing 213 and the
The OVL=0 (offset of interlayer alignment) of three metal routings 214.
The non-display area 20 of array substrate 100 of the invention includes that multiple groups are fanned out to cabling 21, and every group is fanned out to cabling 21 and includes
It is superposed and the first metal routing 212 insulated from each other, the second metal routing 213 and third metal routing 214, the second metal
Cabling 213 includes that the first overlapping portion 213a, the second overlapping portion 213b and interconnecting piece 213c, interconnecting piece 213c are connected to the first overlapping
Between portion 213a and the second overlapping portion 213b, the first overlapping portion 213a and the first metal routing 212 and third for being fanned out to cabling 21
Metal routing 214 partly overlaps, the first metal routing 212 that the second overlapping portion 213b is fanned out to cabling 21 with adjacent another group with
Third metal routing 214 partly overlaps.The area for being fanned out to non-display area 20 shared by cabling 21 of the invention can be reduced, and be realized narrow
Frame, at the same can compensate because OVL offset caused by layer capacitance otherness, the first metal routing 212, the second metal is effectively reduced
RC Loading between cabling 213 and third metal routing 214, improves display quality.
The present invention also provides a kind of display panel, the display panel includes above-mentioned array substrate 100, about display surface
The structure and function of plate please refers to the prior art, and details are not described herein again.
The present invention is not limited to the specific details in the above embodiment, within the scope of the technical concept of the present invention, can be with
Various simple variants of the technical solution of the present invention are made, these simple variants all belong to the scope of protection of the present invention.Above-mentioned
Each particular technique feature described in specific embodiment can pass through any suitable side in the case of no contradiction
Formula is combined.In order to avoid unnecessary repetition, the invention will not be further described in various possible combinations.
Claims (10)
1. a kind of array substrate characterized by comprising
Viewing area (10)；
Non-display area (20), including multiple groups are fanned out to cabling (21), and it includes being superposed and insulated from each other that every group, which is fanned out to cabling (21),
The first metal routing (212), the second metal routing (213) and third metal routing (214), second metal routing
It (213) include the first overlapping portion (213a) and the second overlapping portion (213b) that first overlapping portion (213a) is fanned out to away with described
The first metal routing (212) of line (21) partly overlaps with third metal routing (214), second overlapping portion (213b) and phase
The first metal routing (212) of cabling (21) is fanned out to described in adjacent another group and third metal routing (214) partly overlaps.
2. array substrate as described in claim 1, which is characterized in that second metal routing (213) further includes interconnecting piece
(213c), the interconnecting piece (213c) are connected between first overlapping portion (213a) and second overlapping portion (213b).
3. array substrate as claimed in claim 2, which is characterized in that the interconnecting piece (213c) is connected to first overlapping
The end in portion (213a) and second overlapping portion (213b).
4. array substrate as claimed in claim 2, which is characterized in that first overlapping portion (213a) is parallel to described second
Overlapping portion (213b), first overlapping portion (213a) and first metal routing (212), the third metal routing
(214) overlap length is equal to second overlapping portion (213b) and walks with first metal routing (212), the third metal
The overlap length of line (214).
5. array substrate as described in claim 1, which is characterized in that the non-display area (20) be provided with the first metal layer,
Second metal layer and third metal layer；
The first metal layer includes at least one the first metal routings (212)；
The second metal layer includes at least one the second metal routings (213)；
The third metal layer includes at least one third metal routing (214).
6. array substrate as claimed in claim 5, which is characterized in that the non-display area (20) is provided with the first insulating layer
(24) and second insulating layer (25), first insulating layer (24) be set to the first metal layer and the second metal layer it
Between, the second insulating layer (25) is set between the second metal layer and the third metal layer.
7. array substrate as claimed in claim 6, which is characterized in that the array substrate further includes underlay substrate (23), institute
The first metal layer is stated to be arranged on the underlay substrate (23), first insulating layer (24) setting in the first metal layer and
On the underlay substrate (23).
8. array substrate as claimed in claim 6, which is characterized in that first metal routing (212), second metal
The metal line width of cabling (213) and the third metal routing (214) is equal, first metal routing (212) and described the
The spacing of two metal routings (213) is equal to the spacing of second metal routing (213) and the third metal routing (214),
The overlapping widths etc. of first overlapping portion (213a) and second overlapping portion (213b) and first metal routing (212)
In the line width of 1/3 first metal routing (212), first overlapping portion (213a) and second overlapping portion (213b) with
The overlapping widths of the third metal routing (214) are equal to the line width of the 1/3 third metal routing (214).
9. array substrate as described in claim 1, which is characterized in that the viewing area (10) includes a plurality of signal lead
(11), the non-display area (20) includes driving chip (22), and cabling (21) is fanned out to described in multiple groups and is electrically connected at the signal
Between cabling (11) and the driving chip (22).
10. a kind of display panel, which is characterized in that including array substrate described in any one of claim 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811362562.5A CN109300921B (en) | 2018-11-15 | 2018-11-15 | Array substrate and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811362562.5A CN109300921B (en) | 2018-11-15 | 2018-11-15 | Array substrate and display panel |
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| Publication Number | Publication Date |
|---|---|
| CN109300921A true CN109300921A (en) | 2019-02-01 |
| CN109300921B CN109300921B (en) | 2020-09-01 |
Family
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| CN201811362562.5A Active CN109300921B (en) | 2018-11-15 | 2018-11-15 | Array substrate and display panel |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110837820A (en) * | 2019-11-26 | 2020-02-25 | 厦门天马微电子有限公司 | Array substrate and display panel |
| CN111367129A (en) * | 2020-04-09 | 2020-07-03 | 深圳市华星光电半导体显示技术有限公司 | Fan-out routing structure and display panel |
| WO2021103086A1 (en) * | 2019-11-26 | 2021-06-03 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| WO2023168724A1 (en) * | 2022-03-07 | 2023-09-14 | 武汉华星光电技术有限公司 | Display panel and display device |
| WO2023236294A1 (en) * | 2022-06-07 | 2023-12-14 | 武汉华星光电半导体显示技术有限公司 | Display panel and display terminal |
| WO2024087192A1 (en) * | 2022-10-28 | 2024-05-02 | 京东方科技集团股份有限公司 | Display module and preparation method therefor, and display apparatus |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105158998A (en) * | 2015-09-14 | 2015-12-16 | 深圳市华星光电技术有限公司 | Liquid crystal display device and display panel thereof |
| US20160125833A1 (en) * | 2014-10-30 | 2016-05-05 | Samsung Electronics Co., Ltd. | Semiconductor device, display driver integrated circuit including the device, and display device including the device |
| CN106444182A (en) * | 2016-10-31 | 2017-02-22 | 厦门天马微电子有限公司 | Array substrate and display panel |
| CN106647071A (en) * | 2017-02-15 | 2017-05-10 | 上海中航光电子有限公司 | Array substrate, display panel and display device |
-
2018
- 2018-11-15 CN CN201811362562.5A patent/CN109300921B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160125833A1 (en) * | 2014-10-30 | 2016-05-05 | Samsung Electronics Co., Ltd. | Semiconductor device, display driver integrated circuit including the device, and display device including the device |
| CN105158998A (en) * | 2015-09-14 | 2015-12-16 | 深圳市华星光电技术有限公司 | Liquid crystal display device and display panel thereof |
| CN106444182A (en) * | 2016-10-31 | 2017-02-22 | 厦门天马微电子有限公司 | Array substrate and display panel |
| CN106647071A (en) * | 2017-02-15 | 2017-05-10 | 上海中航光电子有限公司 | Array substrate, display panel and display device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110837820A (en) * | 2019-11-26 | 2020-02-25 | 厦门天马微电子有限公司 | Array substrate and display panel |
| WO2021103086A1 (en) * | 2019-11-26 | 2021-06-03 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| CN110837820B (en) * | 2019-11-26 | 2022-05-31 | 厦门天马微电子有限公司 | Array substrate and display panel |
| CN111367129A (en) * | 2020-04-09 | 2020-07-03 | 深圳市华星光电半导体显示技术有限公司 | Fan-out routing structure and display panel |
| WO2023168724A1 (en) * | 2022-03-07 | 2023-09-14 | 武汉华星光电技术有限公司 | Display panel and display device |
| WO2023236294A1 (en) * | 2022-06-07 | 2023-12-14 | 武汉华星光电半导体显示技术有限公司 | Display panel and display terminal |
| WO2024087192A1 (en) * | 2022-10-28 | 2024-05-02 | 京东方科技集团股份有限公司 | Display module and preparation method therefor, and display apparatus |
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| CN109300921B (en) | 2020-09-01 |
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