CN109300499B - Data storage circuit, data reading and writing method, array substrate and display device - Google Patents
Data storage circuit, data reading and writing method, array substrate and display device Download PDFInfo
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- CN109300499B CN109300499B CN201811123121.XA CN201811123121A CN109300499B CN 109300499 B CN109300499 B CN 109300499B CN 201811123121 A CN201811123121 A CN 201811123121A CN 109300499 B CN109300499 B CN 109300499B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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Abstract
The invention discloses a data storage circuit, which comprises at least one resistance change unit; after the setting process of different currents, the resistance change unit can form different resistance values to be used as data to be stored. The invention also discloses an array substrate, a display device, a data writing method and a data reading method. The data storage circuit, the data reading and writing method thereof, the array substrate and the display device provided by the invention can solve the problem that the existing production information is difficult to set or read.
Description
Technical Field
The invention relates to the technical field of display, in particular to a data storage circuit, a data reading and writing method thereof, an array substrate and a display device.
Background
In the production process of a display panel factory, the liquid crystal display usually records panel ID information in a mode of laser marking a metal film layer (two-dimensional code) and the like; however, after the display panel is thinned, the panel ID information cannot be read normally in a display module factory due to appearance reasons such as pits and dirt.
However, the two-dimensional code must be exposed due to the reading method and cannot be hidden in the display panel, so that a position for disposing the two-dimensional code needs to be additionally reserved on the display panel. When the existing display products are designed, narrow frames are increasingly pursued, and due to the fact that the frames of some products are too narrow, the two-dimensional codes cannot be placed on the narrow frames, or the two-dimensional codes cannot be placed but are difficult to read.
Meanwhile, in the module production process, a module factory also needs to record module production data in a mode of generating module ID information; if the function of recording production information (such as defective products (NG), good products (OK), NG positions, NG reasons, Sensor data and the like) in real time is not available, the defective products generated at the client are difficult to trace back to the production source.
Disclosure of Invention
In view of the above, an objective of the embodiments of the present invention is to provide a data storage circuit, a data reading/writing method thereof, an array substrate, and a display device, which can solve the problem of difficult production information setting or reading in the prior art.
In view of the above object, a first aspect of embodiments of the present invention provides a data storage circuit, including at least one resistance change unit; after the setting process of different currents, the resistance change unit can form different resistance values to be used as data to be stored.
Optionally, the data storage circuit includes at least one storage unit; the memory unit comprises at least one thin film transistor and at least one resistive unit; and the resistance change unit completes data writing and/or reading under the on-off control of the thin film transistor.
Optionally, the memory unit includes a first thin film transistor, a second thin film transistor, a first resistive switching unit, and a second resistive switching unit; the control electrode of the first thin film transistor and the first electrode of the second thin film transistor are connected with a first signal line, the control electrode of the second thin film transistor and the first electrode of the first thin film transistor are connected with a second signal line, the second electrode of the first thin film transistor is connected with the first end of the first resistance changing unit, the second electrode of the second thin film transistor is connected with the first end of the second resistance changing unit, and the second end of the first resistance changing unit and the second end of the second resistance changing unit are connected with a third signal line.
Optionally, the data storage circuit includes a memory cell array with N rows and M columns; the control electrode of the first thin film transistor and the first electrode of the second thin film transistor of the same row of memory cells are both connected with the same signal line, the control electrode of the second thin film transistor of the same row of memory cells and the first electrode of the first thin film transistor are both connected with the same signal line, the second end of the first resistance change unit of the same row is both connected with the same signal line, and the second end of the second resistance change unit of the same row is both connected with the same signal line.
Optionally, the thin film transistor includes a gate insulating layer and a source drain, and the resistance change unit includes a metal substrate, an insulating layer, and a metal electrode; the gate insulating layer and the insulating layer of the resistance change unit are the same layer, and the film layer where the source and drain electrodes are located is the same layer as the metal electrode or the metal substrate.
Optionally, the resistive unit includes a metal substrate, an insulating layer, and a metal electrode; the metal substrate is made of Al, Cu, Ti or Mo, the insulating layer is made of silicon oxide, and the metal electrode is made of Al, Cu, Ti or Mo.
In a second aspect of the embodiments of the present invention, there is provided an array substrate, including the data storage circuit as described in any one of the preceding claims, the data storage circuit being configured to store production information of the array substrate.
Optionally, the array substrate is used for forming a liquid crystal cell in a box-to-box manner with a color film substrate, the color film substrate includes a first light-shielding layer and a color resistor, and the first light-shielding layer is used for shielding light rays except for light rays passing through the color resistor; after the array substrate and the color film substrate are in box matching, the data storage circuit is located in the orthographic projection of the first shading layer.
Optionally, the array substrate includes a second light-shielding layer and a thin film transistor array, where the second light-shielding layer is used to shield light incident from the back of the array substrate to prevent the light from irradiating an active layer in the thin film transistor array; the resistance change unit comprises a metal substrate; the metal substrate and the second shading layer are the same layer.
In a third aspect of the embodiments of the present invention, there is provided a display device, including the array substrate as described in any one of the preceding claims.
In a fourth aspect of the embodiments of the present invention, there is provided a data writing method of the data storage circuit, including:
acquiring data to be stored;
analyzing the data to be stored, and converting the data to be stored into a resistance value of a corresponding resistance change unit;
and determining a set current corresponding to the resistance change unit according to the resistance value, and inputting the set current to the resistance change unit to complete setting.
In a fifth aspect of the embodiments of the present invention, there is provided a data reading method of the data storage circuit, including:
reading the resistance value of the resistance change unit;
and converting the resistance value into storage data according to the corresponding relation between the resistance value and the storage data.
As can be seen from the above, according to the data storage circuit, the data reading and writing method thereof, the array substrate and the display device provided by the embodiment of the invention, the resistance change unit is arranged and the characteristic that the resistance change unit can form different resistance values after being set at different currents is utilized, and the resistance change unit is used as a device for storing data, so that the data storage circuit for storing data can obtain the stored data by reading the resistance value of the resistance change unit in the circuit in the subsequent conversion without obtaining the stored data in a physical identification (such as laser scanning) manner. Therefore, the specially designed data storage circuit stores/reads information, an optical two-dimensional code adopted in the prior art can be omitted, the two-dimensional code is prevented from being bad in production, an exposed space does not need to be reserved for the two-dimensional code additionally, and the narrow frame of the display device can be realized.
Drawings
Fig. 1 is a schematic structural diagram of a resistance change unit in an embodiment of the invention;
FIG. 2 is a schematic structural diagram of an embodiment of a memory cell in an embodiment of the invention;
FIG. 3 is a schematic structural diagram of another embodiment of a memory cell according to the present invention;
FIG. 4 is a schematic diagram of a data storage circuit according to an embodiment of the present invention;
FIG. 5a is a schematic diagram of a data write waveform of a data storage circuit according to an embodiment of the present invention;
FIG. 5b is a schematic diagram of a data write waveform of the data storage circuit according to the embodiment of the present invention;
FIG. 5c is a schematic diagram of a reset waveform of the data storage circuit according to the embodiment of the present invention;
FIG. 5d is a schematic diagram of a further reset waveform of the data storage circuit according to the embodiment of the present invention;
FIG. 6 is a schematic structural diagram of an array substrate according to an embodiment of the invention;
FIG. 7 is a flowchart illustrating a data writing method according to an embodiment of the present invention;
fig. 8 is a flowchart illustrating a data reading method according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
A first aspect of embodiments of the present invention provides a data storage circuit, which can solve the problem of difficulty in setting or reading existing production information.
The data storage circuit comprises at least one resistance change unit; after the setting process of different currents, the resistance change unit can form different resistance values to be used as data to be stored.
In the foregoing embodiment of the present invention, by setting the resistance change unit and using the characteristic that the resistance change unit can form different resistance values after being set at different currents, the resistance change unit is used as a device for storing data, so that the data storage circuit for storing data can obtain the stored data by reading the resistance value of the resistance change unit in the circuit in the following step without obtaining the stored data in a physical identification (such as laser scanning) manner. Therefore, the specially designed data storage circuit stores/reads information, an optical two-dimensional code adopted in the prior art can be omitted, the two-dimensional code is prevented from being bad in production, an exposed space does not need to be reserved for the two-dimensional code additionally, and the narrow frame of the display device can be realized.
Optionally, as shown in fig. 1a, the resistive switching unit includes a metal substrate 21, an insulating layer 22, and a metal electrode 23, where the metal substrate 21, the insulating layer 22, and the metal electrode 23 form a sandwich structure. When the resistance change unit is activated (set voltage 4.4V), it can write 4 resistance states (as shown in table 1): when the limiting current is 1mA, the resistance of the first resistance state is about 250 omega; when the limiting current is 10 muA, the resistance of the second resistance state is about 19k omega; when the limiting current is 1 muA, the resistance of the third resistance state is about 1.7M omega; correspondingly, the resistance state after all resistance states are reset (reset voltage-0.7V) is a fourth resistance state, and the resistance is about 100M omega. The specific data is shown in FIG. 1 b. Therefore, under the control of a set voltage (or a reset voltage) and different limiting currents, the resistance of the resistance change unit can be changed correspondingly, the resistance value of each resistance state is changed exponentially, and the resistance change unit can be distinguished obviously, so that different resistance states can be used for referring to different information, and the purpose of storing different data is achieved.
TABLE 1 resistance states of resistance change cells
| Resistive state | Resistance value | Voltage of | Electric current |
| First resistance state | 250Ω | 4.4V | 1mA |
| Second resistorState of the art | 19kΩ | 4.4V | 10μA |
| Third resistance state | 1.7MΩ | 4.4V | 1μA |
| Fourth resistance state | 100MΩ | -0.7V | —— |
Optionally, the resistance change unit may be designed according to a principle of a Resistive Random Access Memory (RRAM). The metal substrate 21 may be made of Al, Cu, Ti or Mo, and may have a thickness of about
The insulating layer 22 may be made of silicon oxide and may have a thickness of about
The metal electrode 23 may be made of Al, Cu, Ti or Mo, and the thickness may be about
And the metal electrode 23 may have a diameter of about when it is cylindrical
Of course, it is understood that the optimum film thickness/material can be tested according to actual product requirements, so as to obtain more suitable thickness, material, etc., without limiting the specification to the parameters listed in the embodiments of the present invention.
As an embodiment of the invention, the data storage circuit comprises at least one storage unit; the memory unit comprises at least one thin film transistor T (both N-type and P-type) and at least one resistive unit R, as shown in fig. 2, a Drain (Drain) of the thin film transistor T is connected in series with the resistive unit R, so that the resistive unit R completes data writing and/or reading under the switching control of the thin film transistor T.
As an embodiment of the present invention, the thin film transistor T includes a gate insulating layer (GI) and a Source Drain (SD), and the resistance change unit R includes a metal substrate, an insulating layer, and a metal electrode; the gate insulating layer and the insulating layer of the resistance change unit are the same layer, and the film layer where the source and drain electrodes are located is the same layer as the metal electrode or the metal substrate. In this way, a part of the hierarchical structure of the thin film transistor T and a part of the hierarchical structure of the resistive unit R can be manufactured simultaneously, so that the manufacturing process can be saved, and the efficiency can be improved; meanwhile, the improvement of the embodiment of the invention does not greatly influence the whole manufacturing process of the display device.
Optionally, the same-layer manufacturing process may be adjusted for a Mask (Mask) light-transmitting area of a display device of some models, so that the same-layer manufacturing is realized through a one-time composition process; the metal material Mo, Al, Ti, etc. may be the existing target material in the existing display device manufacturing process, and the replacement metal target material may be added if necessary, including but not limited to Cu, Ag, Pt, etc.
As an embodiment of the present invention, as shown in fig. 3, the memory cell 10 includes a first thin film transistor T1, a second thin film transistor T2, a first resistive switching cell R1, and a second resistive switching cell R2; a control electrode of the first thin film transistor T1 and a first electrode of the second thin film transistor T2 are both connected to a first signal line D1, a control electrode of the second thin film transistor T2 and a first electrode of the first thin film transistor T1 are both connected to a second signal line G2, a second electrode of the first thin film transistor T1 is connected to a first end of the first resistive switching unit R1, a second electrode of the second thin film transistor T2 is connected to a first end of the second resistive switching unit R2, and a second end of the first resistive switching unit R1 and a second end of the second resistive switching unit R2 are connected to a third signal line GND.
It can be seen that the first thin film transistor T1 and the first resistance change unit R1 in the memory cell in this embodiment are a set, and the second thin film transistor T2 and the second resistance change unit R2 are a set; when the first signal line D1 inputs an on signal, the first thin film transistor T1 is turned on, and at the same time, a set signal or a reset signal inputted from the second signal line G1 is inputted to the first resistance change unit R1 through the first thin film transistor T1, thereby changing the resistance value thereof; when the on signal is input from the second signal line G1, the second thin film transistor T2 is turned on, and at the same time, the set signal or the reset signal input from the first signal line D1 is input to the second resistance change unit R2 through the second thin film transistor T2, thereby changing the resistance value thereof.
Because each resistance change unit has 4 resistance states, the 4 resistance states of the two resistance change units can be combined into 16 combinations in different sequences through arrangement and combination, so that one memory cell can record 16-system characters (as shown in table 2). This has the advantage that the 10-system is usually used when recording production information, so that a 16-system memory cell can be realized, and the requirement of recording 10-system data can be met. Meanwhile, with the structure, the first signal line D1 and the second signal line G1 can be multiplexed by two resistance change units, thereby saving pins.
TABLE 2 characters correspondingly stored in memory cells
As an embodiment of the present invention, the data storage circuit includes an array of N rows and M columns of memory cells 11; the control electrode of the first thin film transistor and the first electrode of the second thin film transistor of the same row of memory cells are both connected with the same signal line, the control electrode of the second thin film transistor of the same row of memory cells and the first electrode of the first thin film transistor are both connected with the same signal line, the second end of the first resistance change unit of the same row is both connected with the same signal line, and the second end of the second resistance change unit of the same row is both connected with the same signal line. Through the circuit design, a time-sharing driving mode is adopted, data writing/reading of the whole data storage circuit can be achieved, and the number of pins can be saved. The second ends of the resistance change units are grounded, and can be connected with the same GND signal line in practical application.
For example, the data storage circuit shown in fig. 4 includes 4 rows and 4 columns of 4 × 4 memory cells, one memory cell is disposed at the intersection of each D signal line and G signal line, and a GND signal line is inserted through the ground terminal of the resistance change unit. Thus, one memory cell 11 can realize 16-system character coding, and a 4 × 4 checkerboard data memory circuit can form a 16-bit hexadecimal character string, so that the basic data storage requirement can be met. Of course, the number of the D/G signal lines can be increased to increase the number of the stored characters according to actual needs, for example, the row and column relationship is 5 × 5, 5 × 6, 6 × 6, and so on.
FIG. 5a shows a data write driving waveform diagram (taking an N-type transistor as an example) with the signal line G as an ON signal and the signal line D as an input signal; fig. 5b shows a data write driving waveform diagram (taking an N-type transistor as an example) with the D signal line as an on signal and the G signal line as an input signal. And by adopting a time-sharing driving mode, setting of each resistance change unit in the data storage circuit can be realized. It is noted that, since the resistance of the resistive switching element is related to the magnitude of the limiting current inputted therein, the current at the time of setting is different according to the resistance value (corresponding to the stored data character) required to be stored by the corresponding resistive switching element. The input value of the current can be set depending on an external signal input device, and when the set voltage is input, the limiting current required for forming the corresponding resistance value is input. It should be noted that fig. 5a and 5b are waveform diagrams provided for each resistance change cell that needs to be set, and if some resistance change cells need to be set to the fourth resistance state, they need to be processed with a reset voltage (-0.7V).
FIG. 5c is a reset waveform diagram (taking an N-type transistor as an example) in which the G signal line is a turn-on signal and the D signal line is a reset signal; fig. 5D shows a reset waveform diagram (taking an N-type transistor as an example) in which the D signal line is an on signal and the G signal line is a reset signal. Here, the reset has a role in that data that has been written can be erased to write a new signal, so that the data storage circuit can be reused.
In a second aspect of the embodiments of the present invention, an array substrate is provided, which can solve the problem of difficulty in setting or reading existing production information.
The array substrate comprises any embodiment of the data storage circuit, and the data storage circuit is used for storing production information related to the array substrate.
According to the array substrate provided by the embodiment of the invention, the resistance change unit is arranged and is used as a device for storing data by utilizing the characteristic that the resistance change unit can form different resistance values after being set at different currents, so that the data storage circuit for storing data can obtain the stored data by converting the resistance value of the resistance change unit in the reading circuit in the follow-up process without acquiring the stored data in a physical identification (such as laser scanning) mode. Therefore, the specially designed data storage circuit stores/reads information, an optical two-dimensional code adopted in the prior art can be omitted, the two-dimensional code is prevented from being bad in production, an exposed space does not need to be reserved for the two-dimensional code additionally, and the narrow frame of the display device can be realized. Particularly, the borderless can be realized by matching with a Chip On Film (COF) technology.
As an embodiment of the invention, the data storage circuit can be arranged at any free position of the array substrate. Compared with the characteristic that the two-dimensional code in the prior art needs to be exposed, the data storage circuit in the embodiment of the invention can be arranged at any free position of the array substrate (as long as the data storage circuit is put down enough and is convenient for arranging corresponding routing), so that the size of the array substrate is not increased, and the array substrate can realize a narrow frame.
In general, when a liquid crystal display device is manufactured, an array substrate and a color film substrate are required to be aligned to form a liquid crystal cell, the color film substrate includes a first light shielding layer and a color resistor (including RGB three colors), and the first light shielding layer (usually, a black matrix layer BM) is used for shielding light except for light passing through the color resistor, so as to prevent light leakage and light mixing between adjacent color resistors. Therefore, preferably, after the array substrate and the color filter substrate are boxed, the data storage circuit is located in the orthographic projection of the first shading layer, so that in a finally formed liquid crystal display device, the data storage circuit does not need to be shaded by using extra materials for attractiveness, and the first shading layer can achieve the function of shading the data storage circuit. Meanwhile, because extra shielding is not needed, the aperture opening ratio of the liquid crystal display device is not influenced when the data storage circuit is arranged.
Optionally, as shown in fig. 6, the data storage Circuit is disposed at any corner of the array substrate near the fan-out region (either the upper left corner or the upper right corner of the array substrate in fig. 6), and meanwhile, as shown in fig. 6, the lead of the data storage Circuit 10 may be connected to a driver IC (IC) of the display device or a Bonding Pin (Bonding Pin) of a Flexible Printed Circuit Board (FPC) through the fan-out region 30 of the array substrate, so that corresponding data writing/reading is realized by using an external Circuit structure of the display device.
As an embodiment of the present invention, the array substrate includes a second light shielding layer (generally LS) for shielding a backlight source, and a thin film transistor array, wherein the second light shielding layer is used for shielding light (generally light incident from a backlight source of a liquid crystal display device) incident from a back surface of the array substrate to prevent the light from irradiating an active layer (because the active layer generates photo-generated carriers after being irradiated by the light, which affects the working performance of the thin film transistor) in the thin film transistor array, and the resistance change unit includes a metal substrate; the metal substrate and the second shading layer are the same layer. Optionally, the second light shielding layer is a first film layer disposed on a substrate (substrate) of the array substrate, and is mainly used for shielding the backlight source to prevent the active layer from being irradiated by light.
In a third aspect of the embodiments of the present invention, a display device is provided, which can solve the problem that the existing production information is difficult to set or read.
The display device comprises any embodiment of the array substrate.
The display device in this embodiment may be: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator and the like.
According to the display device provided by the embodiment of the invention, the resistance change unit is arranged and is used as a device for storing data by utilizing the characteristic that the resistance change unit can form different resistance values after being set at different currents, so that the data storage circuit for storing data can obtain the stored data by reading the resistance value of the resistance change unit in the circuit in the subsequent conversion mode without acquiring the stored data in a physical identification (such as laser scanning) mode. Therefore, the specially designed data storage circuit stores/reads information, an optical two-dimensional code adopted in the prior art can be omitted, the two-dimensional code is prevented from being bad in production, an exposed space does not need to be reserved for the two-dimensional code additionally, and the narrow frame of the display device can be realized.
In a fourth aspect of the embodiments of the present invention, a data writing method for a data storage circuit is provided, which can solve the problem that the existing production information is difficult to set or read.
As shown in fig. 7, the data writing method of any embodiment of the foregoing data storage circuit includes:
step 41: acquiring data to be stored; optionally, the data to be stored may be a character string including a plurality of characters;
step 42: analyzing the data to be stored, and converting the data to be stored into a resistance value of a corresponding resistance change unit;
optionally, the step 42 may specifically include: converting the characters into the resistance values of the corresponding resistance change units according to the corresponding relation between each character in the data to be stored and the resistance value of the resistance change unit;
step 43: and determining a set current corresponding to the resistance change unit according to the resistance value, and inputting the set current to the resistance change unit to complete setting, thereby completing the storage of the data to be stored.
Optionally, for example, by taking the written information [ 121111111111111F ], corresponding characters need to be written in the corresponding memory cells in sequence, and the characters have a corresponding relationship with the resistance states of two resistance change units in the memory cells (see table 2), when setting (voltage is 4.4V), a corresponding limiting current is input to the resistance change unit in the corresponding resistance state, that is, the resistance value of the corresponding resistance change unit can be set, so as to complete the writing of the required information.
For example, when 1 needs to be written, referring to tables 1 and 2, when the limiting current of the resistive switching element 1 is controlled to 1mA, the resistive switching element 1 is set to the first resistance state (250 Ω), and then the limiting current of the resistive switching element 2 is controlled to 10 μ a, the resistive switching element 2 is set to the second resistance state (19k Ω), so that the memory cell is stored as character 1. Similarly, referring to tables 1 and 2, when the limiting current of the resistance change unit 1 is controlled to be 1mA, the resistance change unit 1 is set to be in the first resistance state (250 Ω), and then the limiting current of the resistance change unit 2 is controlled to be 1 μ a, the resistance change unit 2 is set to be in the third resistance state (1.7M Ω), so that the memory cell is stored as character 2. Similarly, referring to tables 1 and 2, when the set voltage of the resistance change unit 1 is changed to the reset voltage of-0.7V, the resistance change unit 1 is reset to the fourth resistance state (100M Ω), and then the set voltage of the resistance change unit 2 is changed to the reset voltage of-0.7V, and the resistance change unit 2 is also reset to the fourth resistance state (100M Ω), so that the memory cell is stored as the character F. Other memory cells that need to be written with the word 1 can be implemented by referring to the method for writing the word 1, and are not described herein again.
Writing information into the display panel (Cell) can be performed after the manufacturing process of the array substrate is finished; an Original Equipment Manufacturing (OEM) factory may read production information of a previous process or write production information of a current process after a Cutting process (Cutting), and a corresponding read code is designed according to a position (FPC/IC Bonding pin) of a product in a state where a flexible circuit board is bound to a Glass substrate (FPC On Glass, FOG, which is equivalent to an intermediate process of a module process) to a Final inspection (FI, which is equivalent to an end process of the module process).
Optionally, the writing of the storage information of the data storage circuit may be implemented by an Electrical Parameter performance (EPM) detection device in the production line, when the D signal line inputs the start signal, the G signal line may write corresponding data, and when the G signal line inputs the start signal, the D signal line may write corresponding data.
The resistance value of the resistance change unit can be permanently kept after writing, and can also be erased repeatedly.
In a fifth aspect of the embodiments of the present invention, a data reading method for a data storage circuit is provided, which can solve the problem that the existing production information is difficult to set or read.
As shown in fig. 8, the data reading method of the data storage circuit includes:
step 51: reading the resistance value of the resistance change unit;
step 52: converting the resistance value into storage data according to the corresponding relation between the resistance value and the storage data;
optionally, the step 52 may specifically include: and converting the resistance value into characters according to the corresponding relation between the resistance value and the characters, and sequentially forming storage data by the characters.
When information is read, if the resistance value of the resistance change unit 1 in the read memory unit is 250 Ω and the resistance value of the resistance change unit 2 is 19k Ω, the resistance change unit is converted into a character 1; reading the resistance value of the resistance change unit 1 in the memory unit to be 250 omega, and the resistance value of the resistance change unit 2 to be 1.7M omega, and converting the resistance value into a character 2; similarly, the resistance value of the resistance change unit 1 in the read memory cell is 100M Ω, and the resistance value of the resistance change unit 2 is 100M Ω, which is converted into a character F. In this way, the information stored in each memory cell can be obtained, and further the production information stored in the data storage circuit can be obtained.
Optionally, the reading of the storage information of the data storage circuit may be implemented by an Electrical Parameter Monitor (EPM) detection device in the production line, when the D signal line inputs the start signal, the G signal line may read corresponding data, and when the G signal line inputs the start signal, the D signal line may also read corresponding data. Optionally, after the produced product forms a display module state, the resistance value in the circuit can be read through the cooperation of the IC.
The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except for the gate, one of the two poles is referred to as a source, and the other pole is referred to as a drain. Further, the transistors may be classified into N-type transistors or P-type transistors according to their characteristics. In the driving circuit provided by the embodiment of the present invention, all the transistors are illustrated as N-type transistors, and it is conceivable that those skilled in the art can easily conceive of the implementation of P-type transistors without creative efforts, and therefore, the present invention is also within the protection scope of the embodiment of the present invention.
In the embodiment of the invention, the first electrode is the source and the second electrode is the drain for the N-type transistor, and the first electrode is the drain and the second electrode is the source for the P-type transistor.
Those of ordinary skill in the art will understand that: the invention is not to be considered as limited to the specific embodiments thereof, but is to be understood as being modified in all respects, all changes and equivalents that come within the spirit and scope of the invention.
Claims (10)
1. The data storage circuit is characterized by being used for storing production information of an array substrate; the data storage circuit comprises at least one storage unit; the memory unit comprises at least one thin film transistor and at least one resistive unit; after the setting process of different currents, the resistance change unit can form different resistance values to be used as data to be stored; the resistance change unit completes data writing and/or reading under the control of the switch of the thin film transistor;
the memory unit comprises a first thin film transistor, a second thin film transistor, a first resistive switching unit and a second resistive switching unit; the control electrode of the first thin film transistor and the first electrode of the second thin film transistor are both connected with a first signal line, the control electrode of the second thin film transistor and the first electrode of the first thin film transistor are both connected with a second signal line, the second electrode of the first thin film transistor is connected with the first end of the first resistance changing unit, the second electrode of the second thin film transistor is connected with the first end of the second resistance changing unit, and the second end of the first resistance changing unit and the second end of the second resistance changing unit are both connected with a third signal line;
the first thin film transistor and the first resistance change unit form a group, and the second thin film transistor and the second resistance change unit form a group; when the first signal line inputs a starting signal, the first thin film transistor is turned on, and simultaneously a setting signal or a resetting signal input by the second signal line is input to the first resistance change unit through the first thin film transistor, so that the resistance value of the first resistance change unit is changed; when the second signal line inputs a start signal, the second thin film transistor is turned on, and simultaneously a set signal or a reset signal input from the first signal line is input to the second resistance change unit through the second thin film transistor, thereby changing the resistance value thereof.
2. The circuit of claim 1, comprising an array of N rows and M columns of memory cells; the control electrode of the first thin film transistor and the first electrode of the second thin film transistor of the same row of memory cells are both connected with the same signal line, the control electrode of the second thin film transistor of the same row of memory cells and the first electrode of the first thin film transistor are both connected with the same signal line, the second end of the first resistance change unit of the same row is both connected with the same signal line, and the second end of the second resistance change unit of the same row is both connected with the same signal line.
3. The circuit according to claim 1, wherein the thin film transistor comprises a gate insulating layer and a source drain, and the resistive switching unit comprises a metal substrate, an insulating layer and a metal electrode; the gate insulating layer and the insulating layer of the resistance change unit are the same layer, and the film layer where the source and drain electrodes are located is the same layer as the metal electrode or the metal substrate.
4. The circuit according to claim 1, wherein the resistive switching cell comprises a metal substrate, an insulating layer, and a metal electrode; the metal substrate is made of Al, Cu, Ti or Mo, the insulating layer is made of silicon oxide, and the metal electrode is made of Al, Cu, Ti or Mo.
5. An array substrate comprising the data storage circuit of any one of claims 1 to 4.
6. The array substrate according to claim 5, wherein the array substrate is used for forming a liquid crystal cell in a box-to-box manner with a color film substrate, the color film substrate comprises a first shading layer and a color resistor, and the first shading layer is used for shading other light except light passing through the color resistor; after the array substrate and the color film substrate are in box matching, the data storage circuit is located in the orthographic projection of the first shading layer.
7. The array substrate of claim 5, wherein the array substrate comprises a second light shielding layer and a thin film transistor array, the second light shielding layer is used for shielding light incident from the back surface of the array substrate so as to prevent the light from irradiating an active layer in the thin film transistor array; the resistance change unit comprises a metal substrate; the metal substrate and the second shading layer are the same layer.
8. A display device comprising the array substrate according to any one of claims 5 to 7.
9. A method of writing data to a data storage circuit according to any one of claims 1 to 4, comprising:
acquiring data to be stored; the data to be stored is production information of the array substrate;
analyzing the data to be stored, and converting the data to be stored into a resistance value of a corresponding resistance change unit;
and determining a set current corresponding to the resistance change unit according to the resistance value, and inputting the set current to the resistance change unit to complete setting.
10. A method of reading data from a data storage circuit according to any of claims 1 to 4, comprising:
reading the resistance value of the resistance change unit;
converting the resistance value into storage data according to the corresponding relation between the resistance value and the storage data; the storage data is production information of the array substrate.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0439154A2 (en) * | 1990-01-24 | 1991-07-31 | Seiko Epson Corporation | Semiconductor memory device and data processing device using same |
| JPH04221496A (en) * | 1990-03-29 | 1992-08-11 | Intel Corp | Computer memory circuit mounted onto single substrate and method of finishing sequence for erasing computer memory |
| CN104882160A (en) * | 2007-05-31 | 2015-09-02 | 美光科技公司 | Phase Change Memory Structure With Multiple Resistance States And Methods Of Programming And Sensing Same |
| CN105632552A (en) * | 2014-11-26 | 2016-06-01 | 三星电子株式会社 | Resistive memory device and method of operating the same |
| CN105807522A (en) * | 2016-05-25 | 2016-07-27 | 京东方科技集团股份有限公司 | Array substrate, production method thereof and display panel |
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| US7130234B2 (en) * | 2003-12-12 | 2006-10-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0439154A2 (en) * | 1990-01-24 | 1991-07-31 | Seiko Epson Corporation | Semiconductor memory device and data processing device using same |
| JPH04221496A (en) * | 1990-03-29 | 1992-08-11 | Intel Corp | Computer memory circuit mounted onto single substrate and method of finishing sequence for erasing computer memory |
| CN104882160A (en) * | 2007-05-31 | 2015-09-02 | 美光科技公司 | Phase Change Memory Structure With Multiple Resistance States And Methods Of Programming And Sensing Same |
| CN105632552A (en) * | 2014-11-26 | 2016-06-01 | 三星电子株式会社 | Resistive memory device and method of operating the same |
| CN105807522A (en) * | 2016-05-25 | 2016-07-27 | 京东方科技集团股份有限公司 | Array substrate, production method thereof and display panel |
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