CN109285762A - A kind of epitaxy of gallium nitride silicon chip edge processing technology - Google Patents
A kind of epitaxy of gallium nitride silicon chip edge processing technology Download PDFInfo
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- CN109285762A CN109285762A CN201811149564.6A CN201811149564A CN109285762A CN 109285762 A CN109285762 A CN 109285762A CN 201811149564 A CN201811149564 A CN 201811149564A CN 109285762 A CN109285762 A CN 109285762A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02021—Edge treatment, chamfering
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Abstract
The invention discloses a kind of epitaxy of gallium nitride silicon chip edge processing technologys.The damage that thick chamfering for the first time removes edge slice processing is carried out by 1000 mesh grinding wheels after silicon single crystal slice, is then ground and is corroded, silicon wafer is made to have preferable edge quality；Surface is protected by carrying on the back inside front cover silica, surface damage and contamination caused by sucker and grinding wheel when avoiding second of chamfering, while pyroprocess also releases the stress at edge；Second of smart chamfering is carried out using 2000 mesh grinding wheels, so that fillet surface width is reached maximum and is had more fine surface and optimal Chamfer Edge quality is obtained by the light erosion removal surface damage of 50% potassium hydroxide solution and edge stress.The present invention is simple, is easily achieved, and can effectively improve the chamfered edge areas quality of silicon single-crystal polishing plate.
Description
Technical field
The present invention relates to semiconductor material processing technologies, process work more particularly to a kind of epitaxy of gallium nitride silicon chip edge
Skill.
Background technique
Gallium nitride has high saturated electrons rate and the characteristics such as breakdown voltage and high temperature resistant, and it is extremely severe to be utilized production
The high-temperature high-frequency high-power electronic device (FET, HEMT) run under environment is applied to wireless telecommunications (wireless
Station), the fields such as satellite communication.Especially nearly ten years, it is sent out by the semiconductor material with wide forbidden band of representative and device of GaN
The very swift and violent and development to information science technology and application of exhibition have played huge impetus.Therefore, GaN epitaxy material with
The research topic for being prepared into current the supreme arrogance of a person with great power of device, domestic each research institution and university all concentrate on main attention
Epitaxy technology research and device performance are promoted above, have been achieved with breakthrough simultaneously as most promising silicon based gallium nitride epitaxy technology
Applied to production.And the especially 6 inches of silicon substrate materials of the silicon substrate as proprietary material, depend on import at present more.It is domestic
Major silicon wafer manufacturer is absorbed in discrete device silicon wafer and silicon epitaxy substrate slice more, recognizes deficiency to the particularity of epitaxy of gallium nitride,
Lack corresponding design experiences and unified technical standard, seriously constrains the promotion of the preparation level of substrate.
Currently, domestic power device is focused mostly on gallium nitride epitaxial slice main problem in the fringe region of polished silicon wafer, performance
Chamfer Edge for serious, edge epi layer Hui Rong, marginal mechanical damage of edge skid wire etc., with polished silicon substrate before extension
Area's quality has direct relationship.General chamfering is formed using the thick chamfering+1500# grinding wheel essence chamfer machining of 800# grinding wheel, due to
50-60 μm of the amount of being removed grinding is needed after chamfering, edge impact makes Chamfer Edge re-form new damage, chamfering when grinding
Face width reduces 100 μm or so；It is rotten due to the assembly that chamfered edge areas is multiple crystal orientation crystal faces when carrying out chemical attack again
It is poor to lose rate consistency, be easy to cause the amplification of marginal mechanical damage etch pit, edge chamfer profile sharpened, and make face width
It further decreases, so that fringe region quality is deteriorated after polishing.After gallium nitride high temperature epitaxy due to lattice mismatch is serious,
Stress, which is difficult to mediate, causes the serious even sliver of skid wire.How to reduce the mechanical damage of Chamfer Edge, guarantee chamfering as far as possible
Maximum value, the release edge machining stress of face width, become the problem of epitaxy of gallium nitride silicon substrate development.Chamfer Edge quality control
System is one and is related to the system engineering of the multi-process such as slice, round as a ball, chamfering, grinding, burn into polishing, only by improving chamfering work
Skill is difficult to realize, and needs to redesign entire processing technology.
Summary of the invention
In view of prior art situation, for the particularity of epitaxy of gallium nitride silicon substrate, the present invention provide it is a kind of simple, have
Silicon chip edge processing technology is adopted outside the high-quality gallium nitride imitate, being easily achieved.The present invention removes edge slice by thick chamfering
The damage of processing, is then ground and is corroded, and silicon wafer is made to have preferable edge quality；By back inside front cover silica to table
Face is protected, and is avoided chamfering twice and is caused surface damage and contamination, while pyroprocess also releases the stress at edge；Into
Second of row smart chamfering, makes fillet surface width reach initial chamfer design value and has more fine surface, by light rotten
Etching off removes surface damage and edge stress, has reached optimal surface quality.
The technical solution adopted by the present invention is that: a kind of epitaxy of gallium nitride silicon chip edge processing technology, it is characterized in that: silicon list
Crystalline substance, which is cut into after silicon wafer, first carries out thick chamfer machining for the first time, is then ground to silicon wafer, chemical attack, silicon wafer grinding,
Using back inside front cover silica as sealer after corrosion, second of smart chamfering is then carried out, uses alkali after smart chamfering
Solution is gently corroded, and is being protected surface not increased polished silicon wafer fillet surface width to greatest extent by while contamination, is being avoided edge
The generation of damage, technique are as follows:
(1), silicon single crystal progress outer diameter is round as a ball, rolling diameter: 151.2 ± 0.2mm.
(2), silicon single crystal is subjected to multi-wire saw, slice thickness: 1100 μm ± 20 μm.
(3), thick chamfering is carried out to silicon slice using fully-automatic chamfering machine, encloses removal amount 0.2mm.
(4), twin grinding is carried out using alumina powder, grinding removal amount is 50 ± 5 μm.
(5), two-sided corrosion is carried out using sour etching technique, erosion removal amount is 30 ± 5 μm.
(6), using the two-sided back inside front cover silica of LPCVD technique, back seals 700 DEG C of temperature, silicon dioxide layer thickness: 3000 ±
1000Å。
(7), second of smart chamfering is carried out using silicon wafer of the fully-automatic chamfering machine to two-sided back inside front cover silica, encloses removal amount
0.1mm。
(8), caustic corrosion is carried out using 50% ± 5% potassium hydroxide solution of concentration.
(9), surface silica dioxide is eroded using 49% ± 10% hydrofluoric acid solution of concentration, carries out single-sided polishing after cleaning.
Thick chamfering is carried out in step (3) of the present invention, using 1000 mesh R type chamfering abrasive wheels, R value: 0.508mm, angle
It is 22 ° ± 1 °, grinding wheel speed: 4000 ± 500RPM, sucker revolving speed: 10 ± 2mm/s, chamfering diameter: 150.4 ± 0.2mm.
Twin grinding is carried out using 8 ± 0.5 micrometer alumina powder of partial size in step (4) of the present invention.
Second of smart chamfering is carried out in step (7) of the present invention, using 2000 mesh R type chamfering abrasive wheels, R value:
0.508mm, angle are 22 ° ± 1 °, grinding wheel speed: 4000 ± 500RPM, sucker revolving speed: 10 ± 2mm/s, chamfering diameter: 150.0
±0.2mm。
Caustic corrosion is carried out in step (8) of the present invention, corrosion temperature: 90 ± 5 DEG C, etching time 10s.
The present invention has the advantage that is with beneficial effect: using this technique, can realize nitrogen in general silicon product processing line
The Precision Machining for changing gallium silicon substrate bevel edge, that is, ensure that the consistency and maximization of two sides fillet surface width, also avoid the
Surface contamination and scuffing caused by sucker and grinding wheel make polished silicon wafer in the case where cannot achieve edge polishing when secondary chamfering
Fringe region quality reaches the requirement for most preferably meeting epitaxy of gallium nitride edge quality.The method is in 4-6 inches of gallium nitride silicon
In substrate processing, it will be used widely.
Specific embodiment
The invention will be further described with reference to embodiments:
Embodiment: silicon single crystal specification: p-type<111>boron-doping, resistivity are as follows: 0.002-0.005 Ω ㎝, diameter :≤153mm.Tool
Body implementation steps are as follows:
(1) silicon single crystal progress outer diameter is round as a ball, rolling diameter: 151.2 ± 0.2mm.
(2) silicon single crystal is subjected to multi-wire saw, slice thickness: 1100 μm ± 20 μm.
(3) thick chamfering is carried out to silicon slice using fully-automatic chamfering machine, using 1000 mesh R type chamfering abrasive wheels, R value:
0.508mm, angle are 22 ° ± 1 °, grinding wheel speed: 4000RPM, sucker revolving speed: 10mm/s encloses removal amount 0.2mm, encloses removal amount
Refer to that silicon wafer turns around the removal amount of silicon wafer diameter with sucker, total removal amount is 0.8mm, aimed dia: 150.4 ± 0.2mm.
(4) twin grinding is carried out using 8 micrometer alumina powder, grinding removal amount is 50 μm.
(5) two-sided corrosion is carried out using sour etching technique, erosion removal amount is 30 μm.
(6) the two-sided back inside front cover silica of LPCVD technique is used, back seals 700 DEG C of temperature, silicon dioxide layer thickness: 3000 ±
1000Å。
(7) second of smart chamfering is carried out using silicon wafer of the fully-automatic chamfering machine to back inside front cover silica, using 2000 mesh R types
Chamfering abrasive wheel, R value: 0.508mm, angle are 22 ° ± 1 °, grinding wheel speed: 4000RPM, sucker revolving speed: 10mm/s encloses removal amount
0.1mm, total removal amount are 0.4mm, aimed dia: 150.0 ± 0.2mm.
(8) caustic corrosion is carried out using 50% potassium hydroxide solution of concentration, corrosion temperature: 90 DEG C, etching time 10s.
(9) surface silica dioxide is eroded using 49% hydrofluoric acid solution of concentration, carries out single-sided polishing after cleaning.
By process above, edge slice is removed by 1000 mesh grinding wheels progress first time thick chamfering after silicon single crystal slice and is added
The damage of work, is then ground and is corroded, and silicon wafer is made to have preferable edge quality；By back inside front cover silica to surface
It is protected, surface damage and contamination caused by sucker and grinding wheel when avoiding second of chamfering, while pyroprocess also discharges
The stress at edge；Second of smart chamfering is carried out using 2000 mesh grinding wheels, so that fillet surface width is reached maximum and has more smart
Thin surface obtains optimal bevel edge marginal plasma by the light erosion removal surface damage of 50% potassium hydroxide solution and edge stress
Amount.The present invention is simple, is easily achieved, and can effectively improve the chamfered edge areas quality of silicon single-crystal polishing plate.
Technical effect is examined: examined after silicon wafer polishing, polished silicon wafer surface is qualified, the back side without pickup, without scuffing, Chamfer Edge
It is smooth, burnishing surface and bevel edge junctional area without stain, it is not damaged, without etch pit, observe edge-smoothing under microscope, it is not damaged, just
Surface chamfer face width be 480 μm, back face chamfer face width be 530 μm, epitaxy of gallium nitride back edge without Hui Rong, without skid wire, without sliver.
The inspection result shows: surface protection done using silica back envelope, second of smart chamfering is carried out after corrosion,
The chamfered edge areas quality that polished silicon wafer can greatly be improved has important application meaning in specialities technique.
Claims (5)
1. a kind of epitaxy of gallium nitride silicon chip edge processing technology, it is characterized in that: silicon single crystal cutting, which is cut into after silicon wafer, first carries out first
Secondary thick chamfer machining, then grinds silicon wafer, chemical attack, and silicon wafer is after grinding, corrosion using back inside front cover silica
As sealer, second of smart chamfering is then carried out, uses aqueous slkali gently to be corroded after smart chamfering, on protection surface
Not by the generation for increasing polished silicon wafer fillet surface width to greatest extent while contamination, avoiding edge damage, technique are as follows:
(1), silicon single crystal progress outer diameter is round as a ball, rolling diameter: 151.2 ± 0.2mm；
(2), silicon single crystal is subjected to multi-wire saw, slice thickness: 1100 μm ± 20 μm；
(3), thick chamfering is carried out to silicon slice using fully-automatic chamfering machine, encloses removal amount 0.2mm；
(4), twin grinding is carried out using alumina powder, grinding removal amount is 50 ± 5 μm；
(5), two-sided corrosion is carried out using sour etching technique, erosion removal amount is 30 ± 5 μm；
(6), using the two-sided back inside front cover silica of LPCVD technique, 700 DEG C of temperature of back envelope, silicon dioxide layer thickness: 3000 ± 1000
Å；
(7), second of smart chamfering is carried out using silicon wafer of the fully-automatic chamfering machine to two-sided back inside front cover silica, encloses removal amount
0.1mm；
(8), caustic corrosion is carried out using 50% ± 5% potassium hydroxide solution of concentration；
(9), surface silica dioxide is eroded using 49% ± 10% hydrofluoric acid solution of concentration, carries out single-sided polishing after cleaning.
2. a kind of epitaxy of gallium nitride according to claim 1 silicon substrate Chamfer Edge processing technology, it is characterized in that: described
Thick chamfering is carried out in step (3), using 1000 mesh R type chamfering abrasive wheels, R value: 0.508mm, angle are 22 ° ± 1 °, grinding wheel speed:
4000 ± 500RPM, sucker revolving speed: 10 ± 2mm/s, chamfering diameter: 150.4 ± 0.2mm.
3. a kind of epitaxy of gallium nitride according to claim 1 silicon substrate Chamfer Edge processing technology, it is characterized in that: described
Twin grinding is carried out using 8 ± 0.5 micrometer alumina powder of partial size in step (4).
4. a kind of epitaxy of gallium nitride according to claim 1 silicon substrate Chamfer Edge processing technology, it is characterized in that: described
Second of smart chamfering is carried out in step (7), using 2000 mesh R type chamfering abrasive wheels, R value: 0.508mm, angle are 22 ° ± 1 °, sand
Wheel speed: 4000 ± 500RPM, sucker revolving speed: 10 ± 2mm/s, chamfering diameter: 150.0 ± 0.2mm.
5. a kind of epitaxy of gallium nitride according to claim 1 silicon substrate Chamfer Edge processing technology, it is characterized in that: described
Caustic corrosion is carried out in step (8), corrosion temperature: 90 ± 5 DEG C, etching time 10s.
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Cited By (8)
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| CN110385606A (en) * | 2019-08-01 | 2019-10-29 | 西安奕斯伟硅片技术有限公司 | A kind of processing method and dicing method of silicon crystal bar |
| CN110625835A (en) * | 2019-09-12 | 2019-12-31 | 西安奕斯伟硅片技术有限公司 | Silicon wafer forming processing method |
| CN111872780A (en) * | 2020-07-20 | 2020-11-03 | 上海新欣晶圆半导体科技有限公司 | Method for improving edge warping of silicon wafer |
| CN114496726A (en) * | 2021-12-17 | 2022-05-13 | 上海中欣晶圆半导体科技有限公司 | Edge removing method for improving silicon slag and self-doping after substrate slice epitaxy |
| CN114792622A (en) * | 2022-06-27 | 2022-07-26 | 西安奕斯伟材料科技有限公司 | Silicon wafer processing method and silicon wafer |
| CN115446999A (en) * | 2022-09-27 | 2022-12-09 | 河北同光半导体股份有限公司 | Method for improving local contour quality of silicon carbide substrate |
| CN117116740A (en) * | 2023-08-02 | 2023-11-24 | 山东有研半导体材料有限公司 | Processing technology of large-size wafer edge |
| CN117161839A (en) * | 2023-11-01 | 2023-12-05 | 山东有研艾斯半导体材料有限公司 | Method for improving mechanical damage of edge of silicon polishing sheet |
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| CN110385606A (en) * | 2019-08-01 | 2019-10-29 | 西安奕斯伟硅片技术有限公司 | A kind of processing method and dicing method of silicon crystal bar |
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| CN114496726A (en) * | 2021-12-17 | 2022-05-13 | 上海中欣晶圆半导体科技有限公司 | Edge removing method for improving silicon slag and self-doping after substrate slice epitaxy |
| CN114792622A (en) * | 2022-06-27 | 2022-07-26 | 西安奕斯伟材料科技有限公司 | Silicon wafer processing method and silicon wafer |
| CN115446999A (en) * | 2022-09-27 | 2022-12-09 | 河北同光半导体股份有限公司 | Method for improving local contour quality of silicon carbide substrate |
| CN117116740A (en) * | 2023-08-02 | 2023-11-24 | 山东有研半导体材料有限公司 | Processing technology of large-size wafer edge |
| CN117161839A (en) * | 2023-11-01 | 2023-12-05 | 山东有研艾斯半导体材料有限公司 | Method for improving mechanical damage of edge of silicon polishing sheet |
| CN117161839B (en) * | 2023-11-01 | 2024-02-06 | 山东有研艾斯半导体材料有限公司 | Method for improving mechanical damage of edge of silicon polishing sheet |
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