CN109283260A - A kind of acquisition, processing and the control circuit of ultrasonic phase array borehole wall imaging system - Google Patents
A kind of acquisition, processing and the control circuit of ultrasonic phase array borehole wall imaging system Download PDFInfo
- Publication number
- CN109283260A CN109283260A CN201710589631.5A CN201710589631A CN109283260A CN 109283260 A CN109283260 A CN 109283260A CN 201710589631 A CN201710589631 A CN 201710589631A CN 109283260 A CN109283260 A CN 109283260A
- Authority
- CN
- China
- Prior art keywords
- chip
- borehole wall
- processing
- data
- acquisition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
- G01N29/44—Processing the detected response signal, e.g. electronic circuits specially adapted therefor
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N2291/00—Indexing codes associated with group G01N29/00
- G01N2291/02—Indexing codes associated with the analysed material
- G01N2291/028—Material parameters
- G01N2291/0289—Internal structure, e.g. defects, grain size, texture
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/21—Pc I-O input output
- G05B2219/21137—Analog to digital conversion, ADC, DAC
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Biochemistry (AREA)
- General Health & Medical Sciences (AREA)
- Signal Processing (AREA)
- Immunology (AREA)
- Pathology (AREA)
- Automation & Control Theory (AREA)
- Investigating Or Analyzing Materials By The Use Of Ultrasonic Waves (AREA)
Abstract
The invention discloses acquisition, processing and the control circuits of a kind of ultrasonic phase array borehole wall imaging system, the circuit includes: fpga chip (1), dsp chip (2), CAN interface chip (4) and SRAM storage chip (6)；The CAN interface chip (4) for the parameter setting of ground system and order to be sent to dsp chip (2), and is responsible for the packaged data after dsp chip (2) processing being transmitted to ground system；The dsp chip (2) for the parameter setting of ground system and order to be sent to fpga chip (1), while being read the data being stored in SRAM storage chip (6) and being handled；The fpga chip (1), the various orders issued for explaining ground system, it completes borehole wall echo wave signal acquisition and Digital Signal Processing is carried out to acquisition data, the extraction for realizing the digital beam froming and borehole wall echo amplitude and then data of echo-signal, finally writes the result after extraction in SRAM storage chip (6).
Description
Technical field
The present invention relates to oil exploration equipment technical fields, and in particular to a kind of ultrasonic phase array borehole wall imaging system is adopted
Collection, processing and control circuit.
Background technique
Underground environment locating for oil well is severe, and the borehole wall is also easy to produce crack, burn into deformation equivalent damage, to cause security risk
Shorten the oil well service life, therefore has very important significance for the detection and protection of oil-well wall.Ultrasonic borehole wall image checking
Technology is that borehole wall situation is shown with the formal intuition of echo amplitude figure using oil-well wall reflection echo amplitude information, from
And achieve the purpose that monitor wall quality.As one kind of ultrasonic borehole wall image checking, ultrasonic phase array borehole wall image checking skill
Art due to having many advantages, such as without rotation of popping one's head in, focus point is adjustable, obtained extensive concern in recent years and had wide to answer
Use prospect.
Acquisition, processing and control circuit are the particularly important component parts of ultrasonic phase array borehole wall image-forming detecting system,
Complete the control to each channel emission parameter of phased array system, and acquisition process and gain to received borehole wall echo-signal
It adjusts.Compared to the underground imaging system that traditional single-shot list receives formula probe, the hair of ultrasonic phase array borehole wall image-forming detecting system
Penetrate/receiving channel is numerous, therefore the data volume of electric circuit in well acquisition and processing doubles therewith, and need and ground control system it
Between carry out real time communication, this just proposes more acquisition, processing and the data throughput capabilities of control circuit and data processing speed
High requirement.Also, it in view of current underground universal cordage uses CAN bus communication mode, is calculated if the bus protocol is converted
Method is integrated in electric circuit in well, will necessarily occupy more hardware resource.
At present in ultrasound phase-control array 1 system frequently with acquisition, processing and control circuit basic framework mainly using being based on
The design of DSP or FPGA.DSP has good computing capability, and versatile, the development cycle is short.But dsp chip flexibility is poor,
And its calculating process still controls hardware realization by software, it, can not in the case where being limited to downhole cable message transmission rate
A large amount of borehole wall echo data is handled in time and is uploaded to ground system, the final real-time for influencing borehole wall imaging system.
FPGA is reconfigurable logical device, is good at the parallel processing for realizing sequential logic and multichannel phased array echo-signal.But
It realizes that the integrating process of the related protocol transfer algorithm of interface communication is complex using FPGA, is not easy in electric circuit in well real
It is existing.
In summary, the principle features of ultrasonic phase array borehole wall imaging system determine it to underground acquisition, processing and control
The data throughput capabilities and data processing speed of circuit processed require height, and its data is required to upload mode and general logger
Bus communication mode has compared with highly compatible.In addition to this, it is desirable that entire circuit can steady operation at high temperature under high pressure, at present
Common ground ultrasonic phase array acquisition, processing are not met by above-mentioned requirements with control circuit.
Summary of the invention
It is an object of the present invention to the present invention is in view of the above-mentioned problems existing in the prior art, with the ultrasonic phase array borehole wall at
Picture system acquisition, processing and control circuit design and implementation are point of penetration, have researched and analysed its realization principle, and provide a kind of energy
Enough it is applied to the ultrasonic phase array borehole wall imaging system acquisition under real well, handles the design scheme with control circuit, the program
It can satisfy requirement of the underground ultrasonic phased array system to data throughput capabilities, data processing speed, and can be with general well logging
Instrument bus is compatible, can be applied in practical subsurface environment.
To achieve the goals above, the present invention provides a kind of acquisition of ultrasonic phase array borehole wall imaging system, processing with
Control circuit, the circuit include: fpga chip 1, dsp chip 2, CAN interface chip 4 and SRAM storage chip 6；
The CAN interface chip 4, for the parameter setting of ground system and order to be sent to dsp chip 2, and
It is responsible for the packaged data after the processing of dsp chip 2 being transmitted to ground system；
The dsp chip 2 for the parameter setting of ground system and order to be sent to fpga chip 1, while reading and depositing
It stores up the data in SRAM storage chip 6 and is handled；
Ultrasonic phase array transmit circuit is completed in the fpga chip 1, the various orders issued for explaining ground system
Fire pulse width, transmitting array element, the control of emission delay and the automatic control of signal gain, complete borehole wall echo wave signal acquisition
And to acquisition data carry out Digital Signal Processing, realize echo-signal digital beam froming and borehole wall echo amplitude with then
The extraction of data finally writes the result after extraction in SRAM storage chip 6.
As a kind of improvement of above-mentioned apparatus, the circuit further include: several ADC sampling A/D chips 3, the ADC sampling
Chip 3 is used to received borehole wall analogue echoes signal being converted into digital signal, and is sent to the fpga chip 1.
As a kind of improvement of above-mentioned apparatus, the circuit further include: clock chip 5, it is brilliant on external or plate for receiving
The digital dock that vibration generates, and clock sources needed for for each chip are generated according to the clock, guarantee each core in circuit
Piece is in synchronous working.
As a kind of improvement of above-mentioned apparatus, between 6 three of the fpga chip 1, dsp chip 2 and SRAM storage chip
Communication and data transmission are carried out using XINTF bus.
As a kind of improvement of above-mentioned apparatus, the fpga chip 1 includes: ultrasound emission reception control unit 11, echo
Signal processing unit 12 and data upload and device control unit 13；
Transmitting control is completed in the ultrasound emission reception control unit 11, the various orders issued for explaining ground system
System, signal processing, data upload and amplifier gain control；
The echo signal processing unit 12 is realized for handling borehole wall echo-signal digitized after sampling
The digital beam froming of phased echo-signal extracts borehole wall echo amplitude and then data, is output to data upload and device control
Unit 13 processed；
The data upload and device control unit 13, and the data for exporting echo signal processing unit 12 are according to number
According to protocol packing and SRAM storage chip 6 is written, and writes logical code for each device and guarantees each chip and FPGA
The normal communication of chip 1.
As a kind of improvement of above-mentioned apparatus, the dsp chip 2 includes: that DSP initialization unit 21, host computer parameter add
Carrier unit 22, processing result uploading unit 23 and working state control unit 24；
The DSP initialization unit 21, for being initialized to the dsp chip 2；
The host computer parameter loading unit 22, in the parameter setting write-in fpga chip 1 by ground system；
The processing result uploading unit 23, for reading the data being stored in SRAM storage chip 6；
The working state control unit 24, controls for the working condition to dsp chip 2.
Present invention has an advantage that
1, the acquisition, processing and the control circuit that design of the present invention not only it is prominent be utilized FPGA timing control precisely, interface
Feature abundant, parallel processing capability is powerful has also given full play to the integrated CAN interface function of DSP, it is super to meet underground
Timing requirements sound phased array transmitting and receive control, by complicated phased array borehole wall echo signal processing algorithm integration in well
Under, reduce the communication pressure between ground system；
2, the circuit more concision and compact that the present invention designs, can realize ultrasonic phase array well on one piece of lesser circuit board
Acquisition, processing and the control of wall imaging system, and circuit at different levels all meets the high temperature resistant requirement of underground hot environment, so that underground
Phased array supersonic imaging is achieved.
Detailed description of the invention
Fig. 1 is acquisition of the invention, processing and control circuit structural representation；
Fig. 2 a is that XINTF bus of the invention writes timing diagram；
Fig. 2 b is that XINTF bus of the invention reads timing diagram；
Fig. 3 is FPGA internal logic functional block diagram of the invention；
Fig. 4 is the software flow pattern of dsp chip of the invention.
Attached drawing mark
1, fpga chip 2, dsp chip 3, ADC chip
4, CAN interface chip 5, clock chip 6, SRAM storage chip
11, ultrasound emission reception control unit 12, echo signal processing unit
13, data upload and device control unit 21, DSP initialization unit
22, host computer parameter loading unit 23, processing result uploading unit
24, working state control unit
Specific embodiment
The present invention is described in detail in the following with reference to the drawings and specific embodiments.
A kind of borehole wall imaging system based on cylinder ultrasonic phase array, the system comprises: ground controller, power supply are short
Section, circuit pipe nipple, sonic system pipe nipple and external mechanical part are constituted.The sonic system pipe nipple includes cylinder ultrasonic phase array probe,
Cylinder ultrasonic phase array probe is by several transducer array element circumferential arrays at cylinder；The circuit pipe nipple is according to ground
The control signal that controller is sent controls each transducer array element in cylinder ultrasonic phase array probe and circumferentially realizes that ultrasonic wave is believed
Number the focusing of focus emission and echo-signal receive, and the echo data collected is sent to ground controller；It is described
Ground controller be imaged according to the echo data received.The circuit pipe nipple includes digital processing circuit plate and simulation
Circuit board.
Acquisition, processing and the control circuit that the present invention designs are the digital processing circuit plate of circuit pipe nipple；Using being based on
The hardware structure of FPGA+DSP, circuit specifically include that on-site programmable gate array FPGA, digital signal processor DSP, simulation with
Digital quantizer ADC and CAN interface chip.Wherein, FPGA be responsible for emit signal phased timing_delay estimation, and to by
The borehole wall echo-signal of ADC acquisition is handled；DSP is responsible for and CAN interface chip is communicated, and realizes ground system pair
The parameter setting of FPGA and operation control, and the data processed result of FPGA is uploaded to ground system carries out imaging and show.
As shown in Figure 1, a kind of acquisition, processing and the control circuit of ultrasonic phase array borehole wall imaging system, the circuit packet
It includes: fpga chip 1, dsp chip 2, ADC chip 3, CAN interface chip 4, clock chip 5 and SRAM storage chip 6.Below
It is the concrete function of each section:
Fpga chip 1, the various orders issued for explaining ground system complete ultrasonic phase array transmit circuit and emit arteries and veins
Width, transmitting array element, the control of emission delay and the automatic control of signal gain are rushed, completes the acquisition of signal and to acquisition number
According to Digital Signal Processing is carried out, the digital beam froming of phased echo-signal and proposing for borehole wall echo amplitude and then data are realized
It takes, the result after extraction is finally sent to SRAM memory module；
Dsp chip 2 configures the register of fpga chip 1 for being communicated with CAN interface chip 4,
The data being stored in SRAM storage chip 6 are read by dma mode simultaneously；
ADC sampling A/D chip 3 turns for receiving the echo-signal in analog circuit board after signal condition, and by analogue echo
Change digital signal into；
CAN interface chip 4 for receiving the parameter setting of ground controller, and is responsible for 2 processing of dsp chip
Packaged data afterwards are transmitted to CAN bus by the interface chip；
Clock chip 5 is generated for receiving the digital dock that crystal oscillator generates on external or plate, and according to the clock for each
Clock sources needed for chip guarantee that each chip in circuit is in synchronous working；
SRAM storage chip 6 is read for receiving the data of writing of fpga chip 1, and by dsp chip 2.
It is communicated and data between 6 three of fpga chip 1, dsp chip 2 and SRAM storage chip using XINTF bus
Transmission, XINTF bus write timing and read timing it is as shown in Figure 2 a and 2 b.When carrying out the transmitting of ultrasound phase-control signal, first
CAN interface chip 4 is passed through to the transmission parameter initialization order of dsp chip 2 and register parameters from ground controller, then by
Fpga chip 1 receives the data of dsp chip 2 by XINTF bus, and the parameter being arranged on upper computer software interface is written one by one
Fpga chip 1, fpga chip 1 send control signals to ultrasound emission after a series of phased array elements and scanning element calculate
Circuit realizes the phase control emission of system.Data flow during this are as follows: host computer → 2 → fpga chip of dsp chip 1 → ultrasound
Transmit circuit.
When borehole wall imaging system carries out ultrasonic echo reception, echo-signal is completed by front-end A/D C sampling A/D chip 3 first
Acquisition, then by fpga chip 1 collected signal is filtered, phased superposition, envelope transformation, borehole wall echo information are extracted etc.
Digital Signal Processing.When data processing, which finishes preparation, to be uploaded, dsp chip 2 discharges XINTF bus, and fpga chip 1 leads to data
It crosses XINTF and passes to SRAM storage chip 6.Data discharge XINTF bus after being transmitted, then read SRAM by dsp chip 2 and deposit
Store up chip 6 in data, finally by dsp chip 2 by data by CAN bus be uploaded to ground controller carry out imaging display with
Data save.Data flow during this are as follows: 6 → dsp chip of ADC sampling A/D chip 3 → fpga chip, 1 → SRAM storage chip 2
→ ground controller.
Fig. 3 is the internal logic functional block diagram of fpga chip.The fpga chip 1 includes: that ultrasound emission receives control list
Member 11, echo signal processing unit 12, data upload and device control unit 13；It is the concrete function of each unit below:
The ultrasound emission reception control unit 11, for completing emission control, signal processing, data upload, amplifier
Gain control；
The echo signal processing unit 12, for realizing borehole wall echo-signal digitized after sampling in fpga chip 1
Interior phased array borehole wall echo algorithm processing, extracts borehole wall information；
The data upload and device control unit 13, the processing result for exporting echo signal processing unit 12 are pressed
Data protocol is packaged and passes to SRAM storage chip 6, and write logical code for each device and guarantee each chip with
The normal communication of fpga chip 1.
Fig. 4 is the software flow pattern of dsp chip.The dsp chip 2 includes: DSP initialization unit 21, host computer parameter
Loading unit 22, processing result uploading unit 23 and working state control unit 24:
The DSP initialization unit 21, for completing:
(a) initialize system and external equipment clock: system master clock is set as 150MHz；
(b) GPIO is initialized: setting XHOLD for GPIO14 function, direction is set as inputting；GPIO15 function is arranged
For XHOLDA, direction is set as exporting；Common IO is set by GPIO0, direction is set as exporting；
(c) interrupt initialization: enabled 7.1DMA Ch1 is interrupted；Enabled 9.7EcanB RX is interrupted；
(d) external bus Xintf is initialized: being set as 16 BITBUS network modes；XTIMCLK is set as 75Mhz；Setting
The specific time sequence parameter of Zone6 and Zone7, wherein the read-write LEAD/ACTIVE/TRAIL time sequence parameter of Zone6 is 1/1/0,
The read-write LEAD/ACTIVE/TRAIL time sequence parameter of Zone7 is 1/2/1；
(e) Ecan module initialization: CANTXB is set by GPIO20 function；CANRXB is set by GPIO21 function；
Communication speed is set as 1Mbit/s；No. 0 mailbox is to send mailbox；No. 16 mailboxes are to receive mailbox.
The host computer parameter loading unit 22, for realizing:
(a) read-write of the parameter register in fpga chip 1: the parameter initialization function of upper computer software is by host computer circle
Fpga chip 1 is written in the parameter configured on face one by one；The parameter testing function of upper computer software is posted what is specified in fpga chip 1
The value of storage reads out to host computer interface；
(b) compensation coefficient of amplitude is loaded into dsp chip 2；
(c) compensation coefficient then is loaded into fpga chip 1.
The processing result uploading unit 23 is that dsp chip 2 passes through Ecan module to host computer under different working modes
Transmission raw radar data or the amplitude of acquisition, geometry amplitude, data then, when being adapted to.
The working state control unit 24, for realizing:
(a) system is ready to: upper computer software clicks the reset button of control panel, and dsp chip 2 can reinitialize respectively
Global variable and fractional hardware, while notifying PC that oneself is ready.
(b) after dsp system program, which is surprisingly run, to fly or enter stuck state, logical house dog after a period of time can be forced
Dsp system resets.
It should be noted last that the above examples are only used to illustrate the technical scheme of the present invention and are not limiting.Although ginseng
It is described the invention in detail according to embodiment, those skilled in the art should understand that, to technical side of the invention
Case is modified or replaced equivalently, and without departure from the spirit and scope of technical solution of the present invention, should all be covered in the present invention
Scope of the claims in.
Claims (6)
1. a kind of acquisition, processing and the control circuit of ultrasonic phase array borehole wall imaging system, the circuit includes: fpga chip
(1), dsp chip (2), CAN interface chip (4) and SRAM storage chip (6)；
The CAN interface chip (4), for the parameter setting of ground system and order to be sent to dsp chip (2), and
It is responsible for the packaged data after dsp chip (2) processing being transmitted to ground system；
The dsp chip (2) for the parameter setting of ground system and order to be sent to fpga chip (1), while being read and being deposited
It stores up the data in SRAM storage chip (6) and is handled；
The hair of ultrasonic phase array transmit circuit is completed in the fpga chip (1), the various orders issued for explaining ground system
Penetrate pulse width, transmitting array element, the control of emission delay and the automatic control of signal gain, complete borehole wall echo wave signal acquisition with
And to acquisition data carry out Digital Signal Processing, realize echo-signal digital beam froming and borehole wall echo amplitude with then count
According to extraction, finally the result after extraction is write in SRAM storage chip (6).
2. acquisition, processing and the control circuit of ultrasonic phase array borehole wall imaging system according to claim 1, feature exist
In the circuit further include: several ADC sampling A/D chips (3), the ADC sampling A/D chip (3) are used for received borehole wall echo
Analog signal is converted into digital signal, and is sent to the fpga chip (1).
3. acquisition, processing and the control circuit of ultrasonic phase array borehole wall imaging system according to claim 1, feature exist
In the circuit further include: clock chip (5), for receiving the digital dock that crystal oscillator generates on external or plate, and when according to this
Clock generates each chip guaranteed in circuit for clock sources needed for each chip and is in synchronous working.
4. acquisition, processing and the control circuit of ultrasonic phase array borehole wall imaging system according to claim 1, feature exist
In, between the fpga chip (1), dsp chip (2) and SRAM storage chip (6) three using XINTF bus carry out communication and
Data transmission.
5. acquisition, processing and the control circuit of ultrasonic phase array borehole wall imaging system according to claim 1, feature exist
In, the fpga chip (1) include: ultrasound emission reception control unit (11), on echo signal processing unit (12) and data
Biography and device control unit (13)；
The ultrasound emission reception control unit (11), the various orders issued for explaining ground system, completion emission control,
Signal processing, data upload and amplifier gain control；
The echo signal processing unit (12) realizes phase for handling borehole wall echo-signal digitized after sampling
The digital beam froming of echo-signal is controlled, borehole wall echo amplitude and then data are extracted, is output to data upload and device control
Unit (13)；
The data upload and device control unit (13), and the data for exporting echo signal processing unit (12) are according to number
According to protocol packing and be written SRAM storage chip (6), and for each device write logical code and guarantee each chip with
The normal communication of fpga chip (1).
6. acquisition, processing and the control circuit of ultrasonic phase array borehole wall imaging system according to claim 1, feature exist
In, the dsp chip (2) include: DSP initialization unit (21), host computer parameter loading unit (22), leaflet in processing result
First (23) and working state control unit (24)；
The DSP initialization unit (21), for being initialized to the dsp chip (2)；
The host computer parameter loading unit (22), in parameter setting write-in fpga chip (1) by ground system；
The processing result uploading unit (23), for reading the data being stored in SRAM storage chip (6)；
The working state control unit (24), for controlling the working condition of dsp chip (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710589631.5A CN109283260A (en) | 2017-07-19 | 2017-07-19 | A kind of acquisition, processing and the control circuit of ultrasonic phase array borehole wall imaging system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710589631.5A CN109283260A (en) | 2017-07-19 | 2017-07-19 | A kind of acquisition, processing and the control circuit of ultrasonic phase array borehole wall imaging system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109283260A true CN109283260A (en) | 2019-01-29 |
Family
ID=65184895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710589631.5A Pending CN109283260A (en) | 2017-07-19 | 2017-07-19 | A kind of acquisition, processing and the control circuit of ultrasonic phase array borehole wall imaging system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109283260A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112543018A (en) * | 2020-12-11 | 2021-03-23 | 深圳开立生物医疗科技股份有限公司 | Ultrasonic equipment chip resetting method and device and ultrasonic system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101493438A (en) * | 2009-02-18 | 2009-07-29 | 宁波工程学院 | Phased array ultrasonic detection, data acquisition and process device |
| CN101576536A (en) * | 2009-06-18 | 2009-11-11 | 浙江大学 | Multi-mode micro-driving force source based on phased array technology |
| CN201407032Y (en) * | 2009-04-29 | 2010-02-17 | 西安思坦仪器股份有限公司 | Digital induction logging tool |
| CN103175900A (en) * | 2013-03-19 | 2013-06-26 | 中国科学院声学研究所 | Phased-array non-destructive inspection device and system |
-
2017
- 2017-07-19 CN CN201710589631.5A patent/CN109283260A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101493438A (en) * | 2009-02-18 | 2009-07-29 | 宁波工程学院 | Phased array ultrasonic detection, data acquisition and process device |
| CN201407032Y (en) * | 2009-04-29 | 2010-02-17 | 西安思坦仪器股份有限公司 | Digital induction logging tool |
| CN101576536A (en) * | 2009-06-18 | 2009-11-11 | 浙江大学 | Multi-mode micro-driving force source based on phased array technology |
| CN103175900A (en) * | 2013-03-19 | 2013-06-26 | 中国科学院声学研究所 | Phased-array non-destructive inspection device and system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112543018A (en) * | 2020-12-11 | 2021-03-23 | 深圳开立生物医疗科技股份有限公司 | Ultrasonic equipment chip resetting method and device and ultrasonic system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102004219B (en) | Infrared focal plane array detector simulation device and method | |
| CN109946666A (en) | MMW RADAR SIGNAL USING processing system based on MPSoC | |
| CN102053254B (en) | Laser ultrasonic detection system and detection method thereof | |
| CN101185580A (en) | Method and apparatus for gathering ultrasonic diagnosis system high-speed radio-frequency echo wave data | |
| CN103743453B (en) | A kind of control method of radar level gauge system | |
| CN104865560B (en) | A kind of phased-array radar Digital Beamformer module verification method and its verification platform based on UVM | |
| CN107219513A (en) | Underwater movement objective analogue echoes method and transceiving integrated device | |
| CN109633758B (en) | Multi-frequency composite ground penetrating radar system | |
| CN105277947B (en) | A kind of signal processing system and method based on FPGA laser velocimeters | |
| CN108023658A (en) | High precision clock sync identification method and apparatus | |
| CN201352213Y (en) | Phased array ultrasonic test data acquisition and processing device | |
| CN102866390B (en) | Synthetic aperture radar echo simulator and echo simulation processing method | |
| CN103941579B (en) | A kind of moment for oceanographic instrumentation records and clock synchronizing method | |
| CN104569938B (en) | A kind of synthetic aperture radar echo simulation device | |
| CN109856599A (en) | A kind of array radar signal processing system and method based on DSP and server | |
| CN109283260A (en) | A kind of acquisition, processing and the control circuit of ultrasonic phase array borehole wall imaging system | |
| CN103207396A (en) | Docking system for simulating Doppler log seabed echo signals on basis of field programmable gata array (FPGA) | |
| CN105662463B (en) | Automatic calibration method and system for scanning precision of ultrasonic probe | |
| CN204255419U (en) | Dual-frequency ultrasonic wave flow tester | |
| CN207936934U (en) | A kind of ultrasonic thickness measurement harvester | |
| Gül et al. | Smartphone controlled ultrasonic nondestructive testing system design | |
| CN101975966B (en) | Towrope simulator board for geophysical exploration | |
| CN107656273A (en) | Radar signal gathers reductor | |
| CN104407051B (en) | A kind of wireless acoustic detector and method | |
| CN113900089A (en) | FPGA and DSP based agile coherent target detection device and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190129 |
|
| RJ01 | Rejection of invention patent application after publication |