CN201352213Y - Phased array ultrasonic test data acquisition and processing device - Google Patents
Phased array ultrasonic test data acquisition and processing device Download PDFInfo
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- CN201352213Y CN201352213Y CN 200920113870 CN200920113870U CN201352213Y CN 201352213 Y CN201352213 Y CN 201352213Y CN 200920113870 CN200920113870 CN 200920113870 CN 200920113870 U CN200920113870 U CN 200920113870U CN 201352213 Y CN201352213 Y CN 201352213Y
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Abstract
The utility model discloses a phased array ultrasonic test data acquisition and processing device which comprises a USB bus and a main control computer; the communication of the USB bus is connected with a data acquisition and processing card module and 64-array element ultrasonic phased array transducer in sequence; the data acquisition and processing card module includes 16 totally identical data acquisition and processing cards; the data acquisition and processing card consists of four paths of ultrasound transmitting/receiving and signal pre-processing circuits which are connected in a matching way, an A/D converting module, an FPGA module and a DSP microprocessor module, a reset circuit and a power module; and the data acquisition and processing card module is provided with 64 input channels and 16 output channels, wherein every four input channels and one output channel correspond to one data acquisition and processing card. By controlling the time delay for excitation and pulse receiving of all arrays in a transducer array, the device changes the phase relation when transmitted or received ultrasounds of all arrays arrive at or come from a certain point in an object, realizes flexible deflection and focusing of a sound beam, and also realizes transverse movement of the position of the sound beam by selecting and using the required array element group.
Description
Technical field
The utility model relates to a kind of detection data acquisition and treating apparatus field, relates in particular to a kind of phased array ultrasonic detection data acquisition and treating apparatus.Be used for the high-speed multiple channel data acquisition and the processing of default of marine platform structure phased array ultrasonic detection.
Background technology
Offshore platform structure environment of living in is abominable, and along with the growth of active time, offshore platform structure can occur in various degree, multi-form damage, and the existence of these damage defects is with the military service safety and the reliability of serious threat offshore platform structure.Therefore, for guaranteeing the safe operation of offshore platform structure, must carry out the regular or irregular detection of platform structure.
The spud leg of offshore platform structure generally is welded by the steel pipe of some kinds of specifications, and its water upper and lower weld seam position and body need carry out safety detection and maintenance, to guarantee safety, the steady operation of offshore platform structure and various device.At present, Ultrasonic Detection is a kind of offshore platform structure Dynamic Non-Destruction Measurement commonly used, and in ultrasonic detection equipment, ultrasound data collection and processing are one of critical components.When carrying out the default of marine platform structure Ultrasonic Detection, because hyperacoustic centre frequency very high (generally can reach 5MHz), causing modulus (A/D) to change sample frequency can be up to 40MHz, so its data acquisition and treating apparatus must be handled the ultrasound data of high-speed high capacity in real time.And existing in the market ultrasound data collection and treating apparatus port number are few and sample frequency does not reach requirement, and conventional ultrasound data acquisition and treating apparatus are to use the A/D conversion that single-chip microcomputer (MCU) or digital signal processor (DSP) are gathered by software control data, the so frequently operation of interrupt system, the speed of data acquisition and processing also will be subjected to very big restriction.
Summary of the invention
Technical problem to be solved in the utility model is the present situation at prior art, and a kind of accurate quick, good, easy and simple to handle, reliable and stable, broad-spectrum phased array supersonic data acquisition and treating apparatus with high-speed multiple channel of real-time of data that detect is provided.Be used for the comprehensive detection of the various defectives of offshore platform structure all size body, thereby detect defectives such as the inside and outside crackle of offshore platform structure body and corrosion quickly and accurately, further improve the detectability of pick-up unit.
The technical scheme that the prior art problem that solves the utility model is adopted is: a kind of phased array ultrasonic detection data acquisition and treating apparatus comprise usb bus and the main control computer that is connected thereof; Wherein: the usb bus communication link is connected to data acquisition and transaction card assembly, and data acquisition and transaction card assembly are connected with 64 array element ultrasonic phased array transducers; Data acquisition and transaction card assembly contain 16 identical data acquisitions and transaction card; Data acquisition includes four tunnel ultrasound emission/reception and signal pre-processing circuit, A/D modular converter, FPGA module, DSP microprocessor module, reset circuit and the power module that matches and be connected with transaction card, data acquisition and transaction card assembly have 64 input channels, 16 output channels, wherein, per 4 input channels and 1 output channel are to having a data collection and transaction card; Have one 4 to select 1 analog switch in data acquisition and transaction card, selecting one of them passage, 1 selection to 16 passages has realized the gating of ultrasonic phased array transducer array element number; All integrated identical four tunnel ultrasound emission/reception and signal pre-processing circuits in 16 data collections and the transaction card; 64 array element ultrasonic phased array transducers can be realized hyperacoustic emission and reception, by the excitation of each array element or the time delay of received pulse in the control transducer array, change is by the emission of each array element or receive that sound wave arrives or from the phase relation during certain point in the object, realize the flexible deflection and the focusing of acoustic beam, select for use required array element group also can realize the transverse movement of acoustic beam position.
Four tunnel above-mentioned ultrasound emission/receptions and signal pre-processing circuit include ultrasonic phased array transducer signal input circuit, multiway analog switch, bandwidth-limited circuit, pre-amplifying circuit and controllable gain amplifying circuit; The ultrasonic phased array transducer signal input circuit links to each other with the input end of multiway analog switch, the output terminal of multiway analog switch links to each other with the input end of bandwidth-limited circuit, the output terminal of bandwidth-limited circuit links to each other with the input end of pre-amplifying circuit, the output terminal of pre-amplifying circuit links to each other with the input end of controllable gain amplifying circuit, the output terminal of controllable gain amplifying circuit links to each other with the input end of A/D modular converter, be used for gating one road ultrasound echo signal and it is amplified and bandpass filtering treatment, and deliver to the A/D modular converter and wait for sampling.
Above-mentioned FPGA module comprises fpga chip, FPGA configuration circuit, crystal oscillating circuit, jtag interface circuit, AS interface circuit; First interface of fpga chip connects the DSP microprocessor module, be used to control A/D and sample, after sampling finishes, store sampled result among the FPGA FIFO buffer area, generate a sampling simultaneously and finish the external interrupt signal of pulse signal as DSP, notice DSP extracts sampled result; Second interface of fpga chip connects the jtag interface circuit, is used for downloading and debugged program; The 3rd interface of fpga chip connects the FPGA configuration circuit, and the FPGA configuration circuit connects the AS interface circuit, downloads to the FPGA configuration circuit with the AS pattern, and inner program is for the FPGA module invokes, even program code can not disappear yet after the power down; The 4th interface of fpga chip connects crystal oscillating circuit, and crystal oscillating circuit provides the oscillator signal of 100MHz, and utilizes the frequency dividing circuit of fpga chip inside to obtain sampling clock, and the highest sample frequency of single channel is 62.5MHz.
Above-mentioned DSP microprocessor module carries out interrupt response to the phase-locked pulse of fpga chip generation and the sampling end pulse of A/D sampling end back generation, extract sampled value in the FIFO buffer memory from fpga chip, be used for the data after the A/D conversion before being transferred to main control computer, carrying out the data pre-service; First interface of DSP microprocessor module links to each other with the flash memory NORFLASH circuit with 32M byte, is used to store the start-up code of number extraction system, as the startup chip of system, deposits DSP program and other preparation data; Second interface of DSP microprocessor module links to each other with the SDRAM circuit, is used for keeping in user's ephemeral data and allotment extraction system stack space; The 3rd interface of DSP microprocessor module links to each other with the usb bus interface circuit, realize that the data between DSP microprocessor module and the main control computer transmit, the usb bus interface circuit links to each other with usb bus, sampled data is sent into main control computer carry out subsequent treatment.
Four tunnel above-mentioned ultrasound emission/receptions and signal pre-processing circuit adopt four passage time sharing modes, ultrasound emission is carried out in four passage timesharing, four road ultrasound echo signals behind multiway analog switch one road signal by gating, carrying out signal amplifies and bandpass filtering, carry out buffer memory at the fifo module of after the A/D modular converter is converted to digital signal, sending into the FPGA inside modules under the control of FPGA module then by the FPGA module controls, after the buffer storage is full, send interrupt request to the DSP microprocessor module, the DSP microprocessor module reads and stores data by data bus; The DSP microprocessor module carries out filtering, denoising to the data of reading in, extract the eigenwert of signal, with the FPGA module as peripheral control unit, the usb bus interface circuit is controlled, the data acquisition result transmission is carried out that waveform shows, the subsequent treatment of defect image reconstruct in the main control computer by usb bus.
The four tunnel above-mentioned ultrasound emission/receptions and the activation of signal pre-processing circuit are finished by the FPGA module, when the burst pulse of FPGA module output was added in one of them four tunnel ultrasound emission/reception in 16 identical data acquisitions and the transaction card and signal pre-processing circuit, this four tunnel ultrasound emission/reception and signal pre-processing circuit were just started working; Four tunnel ultrasound emission/receptions and signal pre-processing circuit are mainly used in and produce the high voltage narrow pulse signal, this high voltage narrow pulse signal loading is on the piezoelectric chip of ultrasonic transducer, convert electrical energy into acoustic energy and produce ultrasonic signal, the while can receive ultrasound echo signal and it is amplified and bandpass filtering.
Four tunnel above-mentioned ultrasound emission/receptions and the pre-amplifying circuit in the signal pre-processing circuit and controllable gain amplifying circuit adopt three controllable gain operational amplifiers and a slice 10 bit resolution D/A converters to form, by the FPGA module its gain is dynamically controlled, three controllable gain operational amplifiers connect into the three-stage cascade mode, each grade be arranged to-and 10dB is to the gain margin of+30dB, adopt the AC coupling mode between three grades, with the drift of avoiding the prime DC voltage through after after level amplifies, fallen into oblivion useful echoed signal; Gain-controlled voltage is controlled by the FPGA module, and the control voltage conversion range is adjusted gain amplifier gain multiple by the comparator circuit of FPGA inside modules in the data acquisition, to improve the resolution characteristic to feeble signal automatically by 0V to 2.5V.
Above-mentioned A/D modular converter output data is 8, and A/D modular converter data are input to the FPGA module, and through being output as 16 after the FPGA module, design can be given full play to the 16 bit data transmittabilities of DSP like this, has improved the work efficiency of system.
Above-mentioned reset circuit is connected with corresponding chip reset pin respectively and carries out reset operation; Power module is connected with other each module respectively to provide power supply to supply with.
Compared with prior art, the utility model mainly has following outstanding advantage owing to adopted above technical scheme:
(1) described device has designed the signal pre-processing circuit that has signal attenuation, gains functions such as amplification and filtering, adopting 8 precision, high sampling rate is the A/D modular converter of 100MSPS, operating voltage is+3V, parallel output interface, compatible TTL/CMOS form can be used with the FPGA module easily.(2) utilize extremely flexible, the programmable characteristics of FPGA module, realized the control of FIFO and logical sequence therein, simplified circuit structure greatly, and provide convenience synchronously for the sequential of entire circuit.(3) the DSP microprocessor module is realized the pre-service digital filtering card inner control of acquired signal, makes detection speed improve greatly, and can alleviate the signal Processing burden of main control computer.Data acquisition and transaction card can carry out 4 channel data collections simultaneously, and each passage can carry out attenuation multiple, sample rate and gain amplifier setting, and the analog output channel is provided simultaneously, are used to realize waveform generation and analog-driven function.(4) behind the use asynchronous FIFO, can realize: first, the batch of data is uploaded, because the acquisition speed of acquisition system front end lags far behind the work period of DSP microprocessor module, batch data is uploaded and has been reduced the number of times that the response of DSP microprocessor module is interrupted, reduced the time that the DSP microprocessor module is used for data acquisition, made the DSP microprocessor module better application in the analysis and the processing of signal; The second, embedded fifo module replaces the FIFO on the hardware.Because FIFO still had a semispace can continue to deposit the data of collection when application was interrupted, the DSP microprocessor module has one period surge time, guaranteed that like this data of being gathered can be not busy because of the DSP microprocessor module when transmission, response in time and cause loss of data, improve the reliability and the work efficiency of data acquisition system (DAS), and can carry out data transmission better.(5) the usb bus interface circuit can be finished the transmission of data acquisition and state, control signal.The simple equipment of the utility model utilization has been realized high-speed multiple channel large capacity data acquisition and processing.
Description of drawings
Fig. 1 is the general structure block diagram of the utility model embodiment;
Fig. 2 is corresponding data collection of Fig. 1 and transaction card block diagram.
Embodiment
Embodiment describes in further detail the utility model below in conjunction with accompanying drawing.
As shown in Figure 1, a kind of phased array ultrasonic detection data acquisition and treating apparatus, the main control computer 4 that comprises usb bus 3 and be connected; Wherein: usb bus 3 communication link are connected to data acquisition and transaction card assembly 2, and data acquisition and transaction card assembly 2 are connected with 64 array element ultrasonic phased array transducers 1; Data acquisition and transaction card assembly 2 contain 16 identical data acquisitions and transaction card 21; Data acquisition includes four tunnel ultrasound emission/receptions and signal pre-processing circuit 5, A/D modular converter 6, FPGA module 7, DSP microprocessor module 8, reset circuit 9 and the power module 10 that matches and be connected with transaction card 21, data acquisition and transaction card assembly 2 have 64 input channels, 16 output channels, wherein, per 4 input channels and 1 output channel are to having a data collection and transaction card 21; Have one 4 to select 1 analog switch in data acquisition and transaction card 21, selecting one of them passage, 1 selection to 16 passages has realized the gating of ultrasonic phased array transducer array element number; All integrated identical four tunnel ultrasound emission/receptions and signal pre-processing circuit 5 in 16 data collections and the transaction card 21; 64 array element ultrasonic phased array transducers 1 can be realized hyperacoustic emission and reception, by the excitation of each array element or the time delay of received pulse in the control transducer array, change is by the emission of each array element or receive that sound wave arrives or from the phase relation during certain point in the object, realize the flexible deflection and the focusing of acoustic beam, select for use required array element group also can realize the transverse movement of acoustic beam position.
Be corresponding data collection of Fig. 1 and transaction card block diagram as shown in Figure 2.FPGA module 7 comprises fpga chip 71, FPGA configuration circuit 72, crystal oscillating circuit 73, jtag interface circuit 74, AS interface circuit 75; First interface of fpga chip 71 connects DSP microprocessor module 8, being used to control A/D samples, after sampling finishes, store sampled result among the FPGA FIFO buffer area, generate a sampling simultaneously and finish the external interrupt signal of pulse signal as DSP, notice DSP extracts sampled result; Second interface of fpga chip 71 connects jtag interface circuit 74, is used for downloading and debugged program; The 3rd interface of fpga chip 71 connects FPGA configuration circuit 72, and FPGA configuration circuit 72 connects AS interface circuit 75, downloads to FPGA configuration circuit 72 with the AS pattern, and inner program is called for FPGA module 7, even program code can not disappear yet after the power down; The 4th interface of fpga chip 71 connects crystal oscillating circuit 73, and crystal oscillating circuit 73 provides the oscillator signal of 100MHz, and utilizes the frequency dividing circuit of fpga chip 71 inside to obtain sampling clock, and the highest sample frequency of single channel is 62.5MHz.
The sampling that produces after phase-locked pulse that 8 pairs of fpga chips of DSP microprocessor module 71 produce and A/D sampling finish finishes pulse and carries out interrupt response, extract sampled value in the FIFO buffer memory from fpga chip 71, be used for the data after the A/D conversion before being transferred to main control computer, carrying out the data pre-service; First interface of DSP microprocessor module 8 links to each other with the flash memory NORFLASH circuit 81 with 32M byte, is used to store the start-up code of number extraction system, as the startup chip of system, deposits DSP program and other preparation data; Second interface of DSP microprocessor module 8 links to each other with SDRAM circuit 82, is used for keeping in user's ephemeral data and allotment extraction system stack space; The 3rd interface of DSP microprocessor module 8 links to each other with usb bus interface circuit 31, realize that the data between DSP microprocessor module 8 and the main control computer 4 transmit, usb bus interface circuit 31 links to each other with usb bus 3, sampled data is sent into main control computer 4 carry out subsequent treatment.
Four tunnel ultrasound emission/receptions and signal pre-processing circuit 5 adopt four passage time sharing modes, ultrasound emission is carried out in four passage timesharing, four road ultrasound echo signals behind multiway analog switch one road signal by gating, carrying out signal amplifies and bandpass filtering, carry out buffer memory at the fifo module of after A/D modular converter 6 is converted to digital signal, sending into FPGA module 7 inside under the control of FPGA module 7 then by FPGA module 7 control, after the buffer storage is full, send interrupt request to DSP microprocessor module 8, DSP microprocessor module 8 reads and stores data by data bus; 8 pairs of data of reading in of DSP microprocessor module are carried out filtering, denoising, extract the eigenwert of signal; FPGA module 7 as peripheral control unit, is controlled usb bus interface circuit 31, the data acquisition result transmission is carried out that waveform shows, the subsequent treatment of defect image reconstruct in the main control computer 4 by usb bus 3.
The activation of four tunnel ultrasound emission/receptions and signal pre-processing circuit 5 is finished by FPGA module 7, when the burst pulse of FPGA module 7 output was added in one of them four tunnel ultrasound emission/reception in 16 identical data acquisitions and the transaction card 21 and signal pre-processing circuit 5, these four tunnel ultrasonic emitting/receiving circuit and signal pre-processing circuit 5 were just started working; Four tunnel ultrasonic emitting/receiving circuit and signal pre-processing circuit 5 are mainly used in and produce the high voltage narrow pulse signal, this high voltage narrow pulse signal loading is on the piezoelectric chip of ultrasonic transducer, convert electrical energy into acoustic energy and produce ultrasonic signal, the while can receive ultrasound echo signal and it is amplified and bandpass filtering.
A/D modular converter 6 output datas are 8, and A/D modular converter 6 data are input to FPGA module 7, and through being output as 16 after the FPGA module 7, design can be given full play to the 16 bit data transmittabilities of DSP like this, has improved the work efficiency of system.
Most preferred embodiment of the present utility model is illustrated, and various variations or the remodeling made by those of ordinary skills can not break away from scope of the present utility model.
Claims (4)
1, a kind of phased array ultrasonic detection data acquisition and treating apparatus, the main control computer (4) that comprises usb bus (3) and be connected; It is characterized in that: described usb bus (3) communication link is connected to data acquisition and transaction card assembly (2), and described data acquisition and transaction card assembly (2) are connected with 64 array element ultrasonic phased array transducers (1); Described data acquisition and transaction card assembly (2) contain 16 identical data acquisitions and transaction card (21); Described data acquisition includes four tunnel ultrasound emission/receptions and signal pre-processing circuit (5), A/D modular converter (6), FPGA module (7), DSP microprocessor module (8), reset circuit (9) and the power module (10) that matches and be connected with transaction card (21), described data acquisition and transaction card assembly (2) have 64 input channels, 16 output channels, wherein, per 4 input channels and 1 output channel are to having a described data acquisition and transaction card (21); In described data acquisition and transaction card (21), there is one 4 to select 1 analog switch; All integrated identical four tunnel ultrasound emission/receptions and signal pre-processing circuit (5) in 16 described data acquisitions and the transaction card (21).
2, a kind of phased array ultrasonic detection data acquisition according to claim 1 and treating apparatus is characterized in that: described four tunnel ultrasound emission/receptions and signal pre-processing circuit (5) include ultrasonic phased array transducer signal input circuit (51), multiway analog switch (52), bandwidth-limited circuit (53), pre-amplifying circuit (54) and controllable gain amplifying circuit (55); Ultrasonic phased array transducer signal input circuit (51) links to each other with the input end of multiway analog switch (52), the output terminal of multiway analog switch (52) links to each other with the input end of bandwidth-limited circuit (53), the output terminal of bandwidth-limited circuit (53) links to each other with the input end of pre-amplifying circuit (54), the output terminal of pre-amplifying circuit (54) links to each other with the input end of controllable gain amplifying circuit (55), and the output terminal of controllable gain amplifying circuit (55) links to each other with the input end of A/D modular converter (6).
3, a kind of phased array ultrasonic detection data acquisition according to claim 1 and 2 and treating apparatus is characterized in that: described FPGA module (7) comprises fpga chip (71), FPGA configuration circuit (72), crystal oscillating circuit (73), jtag interface circuit (74), AS interface circuit (75); First interface of described fpga chip (71) connects described DSP microprocessor module (8), being used to control A/D samples, after sampling finishes, store sampled result among the FPGA FIFO buffer area, generate a sampling simultaneously and finish the external interrupt signal of pulse signal as DSP, notice DSP extracts sampled result; Second interface of fpga chip (71) connects jtag interface circuit (74), is used for downloading and debugged program; The 3rd interface of fpga chip (71) connects FPGA configuration circuit (72), FPGA configuration circuit (72) connects AS interface circuit (75), download to FPGA configuration circuit (72) with the AS pattern, inner program is called for described FPGA module (7), even program code can not disappear yet after the power down; The 4th interface of fpga chip (71) connects described crystal oscillating circuit (73).
4, a kind of phased array ultrasonic detection data acquisition according to claim 3 and treating apparatus is characterized in that: first interface of described DSP microprocessor module (8) links to each other with the flash memory NORFLASH circuit (81) with 32M byte; Second interface of described DSP microprocessor module (8) links to each other with SDRAM circuit (82); The 3rd interface of described DSP microprocessor module (8) links to each other with usb bus interface circuit (31).
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101493438B (en) * | 2009-02-18 | 2011-07-20 | 宁波工程学院 | Phased array ultrasonic detection, data acquisition and process device |
| CN102788843A (en) * | 2012-03-26 | 2012-11-21 | 湖南致力工程检测技术有限公司 | Pre-stress pipeline squeezing quality low frequency ultrasonic array detection apparatus |
| CN103377163A (en) * | 2012-04-13 | 2013-10-30 | 深圳市蓝韵实业有限公司 | Ultrasonic imaging system and real-time collected data transmission method therefor |
| CN103575806A (en) * | 2013-10-23 | 2014-02-12 | 广州多浦乐电子科技有限公司 | Low-power-consumption ultrasonic phased-array transmitting and receiving device |
| CN104391045A (en) * | 2014-10-28 | 2015-03-04 | 邢涛 | Sound-wave-based square wood hole-defect recognition system and method |
| CN105806948A (en) * | 2016-03-03 | 2016-07-27 | 奥瑞视（北京）科技有限公司 | Local water leaching coupling manner based medium plate ultrasonic testing method employing single crystal straight probes |
| WO2020191970A1 (en) * | 2019-03-28 | 2020-10-01 | 深圳中凯剑无损检测设备科技有限公司 | Raw data-based ultrasonic phased array detection system and method |
| CN113805162A (en) * | 2021-11-18 | 2021-12-17 | 杭州雅格纳科技有限公司 | Fish growth detection method and device based on ultrasonic phased array |
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2009
- 2009-02-18 CN CN 200920113870 patent/CN201352213Y/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101493438B (en) * | 2009-02-18 | 2011-07-20 | 宁波工程学院 | Phased array ultrasonic detection, data acquisition and process device |
| CN102788843A (en) * | 2012-03-26 | 2012-11-21 | 湖南致力工程检测技术有限公司 | Pre-stress pipeline squeezing quality low frequency ultrasonic array detection apparatus |
| CN103377163A (en) * | 2012-04-13 | 2013-10-30 | 深圳市蓝韵实业有限公司 | Ultrasonic imaging system and real-time collected data transmission method therefor |
| CN103575806A (en) * | 2013-10-23 | 2014-02-12 | 广州多浦乐电子科技有限公司 | Low-power-consumption ultrasonic phased-array transmitting and receiving device |
| CN103575806B (en) * | 2013-10-23 | 2016-02-03 | 广州多浦乐电子科技有限公司 | Low-power consumption ultrasonic phase array R-T unit |
| CN104391045A (en) * | 2014-10-28 | 2015-03-04 | 邢涛 | Sound-wave-based square wood hole-defect recognition system and method |
| CN105806948A (en) * | 2016-03-03 | 2016-07-27 | 奥瑞视（北京）科技有限公司 | Local water leaching coupling manner based medium plate ultrasonic testing method employing single crystal straight probes |
| CN105806948B (en) * | 2016-03-03 | 2019-04-05 | 奥瑞视（北京）科技有限公司 | Cut deal supersonic detection method based on local water logging coupled modes straight probe of single crystal |
| WO2020191970A1 (en) * | 2019-03-28 | 2020-10-01 | 深圳中凯剑无损检测设备科技有限公司 | Raw data-based ultrasonic phased array detection system and method |
| CN113805162A (en) * | 2021-11-18 | 2021-12-17 | 杭州雅格纳科技有限公司 | Fish growth detection method and device based on ultrasonic phased array |
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Granted publication date: 20091125 Termination date: 20120218 |