CN109243975B - Method for manufacturing semiconductor device - Google Patents
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- CN109243975B CN109243975B CN201710557656.7A CN201710557656A CN109243975B CN 109243975 B CN109243975 B CN 109243975B CN 201710557656 A CN201710557656 A CN 201710557656A CN 109243975 B CN109243975 B CN 109243975B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a device substrate; performing first ion implantation on the back surface of the device substrate to form a buffer layer in the device substrate; performing a second ion implantation from the back side of the device substrate to form an implanted layer in the device substrate, the surface of the implanted layer being flush with the back side; carrying out annealing treatment to activate implanted ions in the buffer layer and the implanted layer; removing a portion of the thickness of the implanted layer from the backside to reduce a junction depth of the implanted layer to a target junction depth. The method can avoid the problem of warping of the device substrate.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.
Background
As a vertical discrete device, an Insulated Gate Bipolar Transistor (IGBT) device needs to have a buffer layer (buffer layer) formed on the back surface of the device to withstand a vertical voltage. Meanwhile, a P-type injection layer is required to be formed on the back of the device to serve as a back electrode, so that a large injection effect is achieved, the conduction voltage drop Vcesat of the device is reduced, and the power consumption is reduced.
For 600V-1700V IGBT products, the buffer layer is conventionally formed by combining high-energy ion implantation and laser annealing due to the requirement of back thinning. The backside P-type implanted layer is formed by ion implantation combined with laser annealing.
The buffer layer is arranged to better increase the longitudinal withstand voltage of the device, and the buffer layer needs to increase the junction depth and width and simultaneously reduce the existence of lattice defects as much as possible. These requirements are conventionally achieved by increasing the ion implantation energy and the laser annealing energy.
The back P-type implant layer to better accommodate the large implant effect requires a reduction in the junction depth of the P-type implant layer to achieve a "transparent" like electrode. The conventional process is realized by the reduction of ion implantation energy and laser annealing energy.
Therefore, two-step ion implantation combined with a two-step laser annealing process is conventionally required for implementation. However, such a process is complicated. Meanwhile, the wafer after thinning is warped and is seriously influenced by the subsequent process due to multiple times of laser annealing. Fig. 1 is a schematic diagram of doping concentration profiles of impurities in a buffer layer and a P-type injection layer on the back surface of an IGBT device, which are realized by a two-step laser annealing process, wherein a curve 1 represents an impurity doping concentration profile of the buffer layer, and a curve 2 represents an impurity doping concentration profile of the P-type injection layer.
Therefore, in order to solve the above technical problems, the present invention proposes a new method for manufacturing a semiconductor device.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the shortcomings of the prior art, one aspect of the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a device substrate;
performing first ion implantation on the back surface of the device substrate to form a buffer layer in the device substrate;
performing a second ion implantation from the back side of the device substrate to form an implanted layer in the device substrate, the surface of the implanted layer being flush with the back side;
carrying out annealing treatment to activate implanted ions in the buffer layer and the implanted layer;
removing a portion of the thickness of the implanted layer from the backside to reduce a junction depth of the implanted layer to a target junction depth.
Illustratively, the conductivity type of the buffer layer is N-type, and the conductivity type of the injection layer is P-type.
Illustratively, a method of spin etching is used to remove a portion of the thickness of the implanted layer.
Illustratively, the thickness of the implanted layer removed is in the range of 0.2 μm to 0.4 μm.
Illustratively, the implantation energy range of the first ion implantation is 2 Mev-3 Mev, and the implantation dosage range is 1E 12-5E 13atom/cm2And/or the implantation energy range of the second ion implantation is 20 Kev-40 Kev, and the implantation dosage range is 1E 13-1E 14atom/cm2。
Illustratively, the annealing process is a laser annealing process.
Illustratively, the laser annealing is high-energy laser annealing, and the annealing energy is 1.5J-3J.
Illustratively, the injection layer is located on a top surface of the buffer layer.
Illustratively, the junction depth of the implanted layer after the annealing process before the step of removing the partial thickness of the implanted layer ranges from 0.4 μm to 0.8 μm, and the target junction depth ranges from 0.2 μm to 0.4 μm.
Illustratively, before the first ion implantation, the method further comprises the step of thinning the back side of the device substrate.
Illustratively, before the thinning, the method further comprises the following steps:
forming a bonding layer on the front side of the device substrate;
providing a supporting substrate, and bonding the bonding layer and the supporting substrate.
Illustratively, the semiconductor device is an IGBT device.
The manufacturing method of the invention realizes the activation of the implanted ions in the buffer layer and the implanted layer through a one-step annealing process, can effectively avoid the problem of warping of the device substrate caused by multi-step annealing, and then removes the implanted layer with partial thickness so as to reduce the junction depth of the implanted layer, realize a transparent electrode and ensure the performance of the device, therefore, the method of the invention can improve the yield and the performance of the device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1 shows a doping concentration distribution diagram of impurities of a buffer layer and an injection layer on the back surface of an IGBT device, which is realized by a conventional two-step laser annealing process;
fig. 2A to 2D are schematic cross-sectional views of devices obtained at relevant steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3 shows a process flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, detailed steps will be set forth in the following description in order to explain the technical solutions proposed by the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In view of the foregoing technical problems, attempts have been made to realize a buffer layer by a method employing hydrogen ion implantation. The activation energy of the light ions is low, and effective activation can be realized at about 400 ℃. This eliminates the need for laser annealing to activate the buffer layer. Laser annealing is only required to achieve activation of the backside P-type implant layer. This reduces the negative effects of multiple laser anneals on wafer warpage after thinning. However, the equipment capable of achieving H ion implantation is very expensive, and the overall production cost increases.
Example one
In order to solve the foregoing technical problem, the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 3, the method mainly includes the following steps:
step S1, providing a device substrate;
step S2 of performing first ion implantation on the back surface of the device substrate to form a buffer layer in the device substrate;
step S3, performing second ion implantation from the back surface of the device substrate to form an implantation layer in the device substrate, wherein the surface of the implantation layer is flush with the back surface;
step S4, annealing treatment is carried out to activate the implanted ions in the buffer layer and the implanted layer;
step S5, removing a portion of the thickness of the implanted layer from the back side to reduce the junction depth of the implanted layer to a target junction depth.
The manufacturing method of the invention realizes the activation of the implanted ions in the buffer layer and the implanted layer through a one-step annealing process, can effectively avoid the problem of warping of the device substrate caused by multi-step annealing, and then removes the implanted layer with partial thickness to reduce the junction depth of the implanted layer, realize a transparent electrode and ensure the performance of the device, therefore, the method of the invention can improve the yield and the performance of the device, and has low cost and simple process.
A method for manufacturing a semiconductor device of the present invention is described in detail below with specific reference to fig. 2A to 2D. Fig. 2A to 2D are schematic cross-sectional views of devices obtained at steps related to a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Specifically, as shown in fig. 2A to 2D, in one example, the semiconductor device of the present invention may be an IGBT device, or may be another semiconductor device.
First, a first step is performed to provide a device substrate.
Specifically, as shown in fig. 2A, a device substrate 200 is provided.
Wherein the device substrate 200 is a bulk silicon substrate, which may be at least one of the following mentioned materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III/V compound semiconductors, as well as multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-stacked germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI), and the like. Further, the substrate can also be an N-type substrate or a P-type substrate. But also an N-type lightly doped substrate.
An isolation structure is formed in a substrate, wherein the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. Various well structures and channel layers on the surface of the substrate are also formed in the semiconductor substrate.
In one example, a front side structure including, for example, a base region, an emitter region, a gate oxide layer, a gate, an emitter, and the like, has been formed on a front side of the device substrate before performing a backside process of the device substrate.
In order to make the device substrate smaller in size, the back surface of the device substrate 200 is also subjected to thinning treatment.
In this step, the thinning method may be a method commonly used in the art, for example, a method such as mechanical grinding, Chemical Mechanical Polishing (CMP), chemical etching, plasma etching, or the like may be used. Optionally, the thickness of the thinned device substrate 200 ranges from 50 μm to 200 μm.
Illustratively, in order to facilitate the operation on the back side of the device wafer, before the thinning, the method further comprises the following steps:
first, a bonding layer (not shown) is formed on the front side of the device substrate.
The bonding layer is bonding glue, the bonding glue can be but not limited to organic polymer materials or ultraviolet-modified organic materials, and the bonding glue has viscosity.
A bond paste layer may be formed on the front side of the device substrate using a method such as coating.
Then, a supporting substrate is provided, and the bonding layer and the supporting substrate are jointed.
The support substrate may be a semiconductor substrate such as a silicon substrate, glass, or a ceramic material. The device substrate is used for supporting the device substrate, and the back side of the device substrate is convenient to operate.
Illustratively, to facilitate handling of the back side of the device wafer, the front side of the device substrate 200 may also be bonded to a support substrate, which serves to support the device substrate.
And then, executing a second step of carrying out first ion implantation on the back surface of the device substrate so as to form a buffer layer in the device substrate.
Specifically, as shown in fig. 2A, a first ion implantation is performed on the back surface (i.e., the back surface) of the device substrate 200 to form a buffer layer 201 in the device substrate 200.
Illustratively, a drift region (not shown) is further formed on the front surface of the device substrate, the drift region has the same conductivity type as the buffer layer 201, and optionally, the drift region is an N-drift region. The buffer layer is positioned at the bottom in the device substrate and is in contact with the drift region, and the buffer layer 201 is used for increasing the longitudinal voltage resistance of the device.
Illustratively, the doping type of the buffer layer 201 may be N type, and especially, the doping type may be heavily N type. That is, the impurity doping concentration of the buffer layer is greater than the impurity doping concentration of the drift region.
In one example, when the buffer layer 201 is an N-type buffer layer, the implanted ions of the first ion implantation are N-type doped ions, including but not limited to at least one of phosphorus or arsenic.
The buffer layer 201 may be implemented by ion implantation on the back side of the substrate, and the depth of the ion implantation is controlled by controlling the implantation energy. Optionally, the implantation energy range of the first ion implantation is 2Mev to 3Mev, and the implantation dose range is 1E12 to 5E13atom/cm2This range of values is by way of example only.
And then, performing a third step of performing second ion implantation from the back surface of the device substrate to form an implantation layer in the device substrate, wherein the surface of the implantation layer is flush with the back surface of the device substrate.
Specifically, as shown in fig. 2B, a second ion implantation is performed on the back surface of the device substrate 200 to form an implantation layer in the device substrate 200, and the surface of the implantation layer 202 is flush with the back surface of the device substrate 200.
Illustratively, the injection layer 202 may serve as a collector region of an IGBT device.
In one example, i.e., the injection layer 202 and the buffer layer 201 have opposite conductivity types, for example, the buffer layer 201 is N-type, the injection layer 202 is P-type, and in particular, the injection layer 202 is heavily doped P-type.
Illustratively, the implanted layer 202 is formed by ion implantation, and when the implanted layer 202 is P-type, the implanted ions are of P-type dopant impurities, such as boron.
In one example, the depth of the ion implantation is controlled by controlling the implantation energy, for example, the second ion implantation has an implantation energy ranging from 20Kev to 40Kev and an implantation dose ranging from 1E13 to 1E14atom/cm2Such known ranges are exemplary only and are not to be construed as limiting the invention.
Further, the depth of the buffer layer is greater than the depth of the injection layer, that is, the distance from the bottom of the buffer layer to the back surface of the device substrate is greater than the distance from the injection layer to the back surface of the device substrate, so that the injection layer is located on the top surface of the buffer layer.
And then, executing step four, and carrying out annealing treatment to activate the implanted ions in the buffer layer and the implanted layer.
Specifically, as shown in fig. 2C, after the first ion implantation and the second ion implantation, an annealing step is required to activate the implanted ions in the buffer layer and the implanted layer, but a two-step laser annealing process is often used in the conventional process at present, but such a process is complicated, and multiple laser anneals may cause the warpage of the thinned device substrate to be increased, which may cause a large negative effect on the subsequent process.
In order to solve the technical problem, in this embodiment, the implanted ions in the buffer layer and the implanted layer are activated through a one-step annealing process, and the lattice defects on the surface of the device substrate caused by the ion implantation are repaired.
Illustratively, the annealing process may use any annealing process known to those skilled in the art, including but not limited to rapid thermal annealing, furnace annealing, spike annealing, laser annealing, and the like. In this embodiment, the annealing process preferably uses laser annealing, which has the advantage of local heating, and can anneal only the region to be annealed without causing thermal damage to other regions except the region.
Illustratively, the laser anneal may be a high energy laser anneal, such as a high energy laser anneal with an anneal energy of 1.5J to 3J, or may include other suitable anneal energies.
After one-step annealing (e.g., high-energy laser annealing), the junction depth of the buffer layer 201 can reach, for example, 2.2 μm to 2.4 μm, while the junction depth of the injection layer 202 is increased significantly, for example, the junction depth reaches 0.4 μm to 0.8 μm, which is far greater than the junction depth requirement of the "transparent" electrode. For some IGBT devices such as FS-IGBT (Field-Stop IGBT) or some non-punch-through IGBT devices, a transparent collector technology is usually required, and the electron current component in the current passing through the collector junction is greater than 50%, so that, in the device turn-off process, a large amount of electrons accumulated in the highly conductance-modulated N-type base region can flow out to the collector through the collector region (the collector region is virtually transparent to electrons), and meanwhile, holes without electron attraction also flow out from the emitter above, so as to achieve fast turn-off of the device, and meanwhile, the trailing current is small, the switching loss is small, and therefore, the "transparent" electrode is very important for improving the performance of the IGBT.
Thus, the requirement of "transparent" electrodes for junction depth is met by performing the following step five, wherein step five comprises: removing a portion of the thickness of the implanted layer from the back side of the device substrate to reduce the junction depth of the implanted layer to a target junction depth.
Specifically, as shown in fig. 2D, a portion of the thickness of the implanted layer 202 is removed from the back side of the device substrate to reduce the junction depth of the implanted layer 202 to a target junction depth.
A portion of the thickness of the implant layer 202 may be removed by performing steps such as etching, grinding, etc. on the backside of the device substrate 200.
It is worth mentioning that the junction depth of the implanted layer refers to the distance between the bottom of the implanted layer and the back surface of the device substrate.
In the present embodiment, a spin silicon etch (spin silicon etch) method is preferably used to remove a portion of the thickness of the implanted layer, especially a single spin etch process.
The single wafer spin etch process processes only one device substrate at a time. In the single chip rotary etching process, the clamper fixes the device substrate 200 and makes the back of the device substrate face upwards, the device substrate horizontally rotates, the spray pipe above the device substrate sprays etching solution to the back of the device substrate, the back of the device substrate is etched, and the injection layer 202 is tightly attached to the back, so that the injection layer 202 with partial thickness is removed while the back of the device substrate is etched, for example, the removed thickness range of the injection layer 202 is 0.2-0.4 μm.
Illustratively, the etching solution may be an acidic solution, an organic base, or an inorganic base. Illustratively, the inorganic base may be KOH, NaOH, NH4OH and the like; the organic base can be tetramethylammonium hydroxide (TMAH), etc.; the acidic solution may be diluted hydrofluoric acid or the like.
In one example, after removing a portion of the thickness of the implanted layer 202, the junction depth of the implanted layer reaches a target junction depth, which may range from 0.2 μm to 0.4 μm, which satisfies the junction depth requirement of the "transparent" electrode.
Therefore, the invention ensures the junction depth of the injection layer (collector region) by removing part of the injection layer by using a method such as a rotary etching process, realizes a 'transparent' electrode to ensure the performance of the IGBT device, is simple and easy to operate, has good compatibility with the prior art, is easy to produce in mass production, uses an etching method to replace laser annealing, and reduces the process cost.
Subsequently, in one example, a metal layer may also be formed on the surface of the implanted layer and annealed to form a metal silicide, and the metal layer may include, for example, Ti metal.
Illustratively, a collector (not shown) may also be formed on the surface of the implant layer 202. Wherein the material of the collector comprises a metal including, but not limited to, aluminum, copper, titanium, or chromium, etc.
Subsequently, in one example, a de-bonding process is performed to separate the device substrate and the support substrate.
Specifically, the device substrate and the supporting substrate may be separated by any method known to those skilled in the art for debonding, for example, heating at a high temperature to denature the bonding layer such as bonding paste to lose adhesiveness, and then peeling the bonding layer from which adhesiveness is lost.
Thus, the introduction of the key steps of the method for manufacturing a semiconductor device of the present invention is completed, and other steps are required for the complete device fabrication, which is not described in detail herein.
In summary, the manufacturing method of the present invention realizes activation of the implanted ions in the buffer layer and the implanted layer through a one-step annealing process (especially a one-step laser annealing process), which can effectively avoid the problem of warpage of the device substrate caused by multiple annealing processes, and then removes the implanted layer with a part of thickness to reduce the junction depth of the implanted layer, realize a "transparent" electrode, and ensure the performance of the device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (12)
1. A method of manufacturing a semiconductor device, comprising:
providing a device substrate;
performing first ion implantation on the back surface of the device substrate to form a buffer layer in the device substrate;
performing a second ion implantation from the back side of the device substrate to form an implanted layer in the device substrate, the surface of the implanted layer being flush with the back side;
carrying out annealing treatment to activate implanted ions in the buffer layer and the implanted layer;
removing a portion of the thickness of the implanted layer from the backside to reduce a junction depth of the implanted layer to a target junction depth.
2. The method of claim 1, wherein the buffer layer has a conductivity type of N-type and the implant layer has a conductivity type of P-type.
3. The method of manufacturing of claim 1, wherein a partial thickness of the implanted layer is removed using a spin etch process.
4. The method of claim 1, wherein the thickness of the implanted layer removed is in a range of 0.2 μm to 0.4 μm.
5. The method of claim 1, wherein the first ion implantation has an implantation energy ranging from 2Mev to 3Mev and an implantation dose ranging from 1E12 to 5E13atom/cm2And/or the implantation energy range of the second ion implantation is 20 Kev-40 Kev, and the implantation dosage range is 1E 13-1E 14atom/cm2。
6. The manufacturing method according to claim 1, wherein the annealing treatment is a laser annealing treatment.
7. The method of manufacturing according to claim 6, wherein the laser annealing process is a high energy laser annealing process having an annealing energy of 1.5J to 3J.
8. The method of manufacturing of claim 1, wherein the injection layer is located on a top surface of the buffer layer.
9. The method of claim 1, wherein a junction depth of the implanted layer after the annealing is in a range of 0.4 μm to 0.8 μm before the step of removing the partial thickness of the implanted layer, and wherein the target junction depth is in a range of 0.2 μm to 0.4 μm.
10. The method of manufacturing of claim 1, further comprising the step of thinning a backside of the device substrate prior to performing the first ion implantation.
11. The method of manufacturing of claim 10, further comprising, prior to said thinning, the steps of:
forming a bonding layer on the front side of the device substrate;
providing a supporting substrate, and bonding the bonding layer and the supporting substrate.
12. The manufacturing method according to claim 1, wherein the semiconductor device is an IGBT device.
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