CN109213252A - A kind of adaptive LDO circuit - Google Patents
A kind of adaptive LDO circuit Download PDFInfo
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- CN109213252A CN109213252A CN201811397496.5A CN201811397496A CN109213252A CN 109213252 A CN109213252 A CN 109213252A CN 201811397496 A CN201811397496 A CN 201811397496A CN 109213252 A CN109213252 A CN 109213252A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
This application provides a kind of adaptive LDO circuits, comprising: open loop networks circuit and closed network circuit, wherein the open loop networks circuit is used to run when load current is lower than the first preset value；The closed network circuit is used to detect the size of the load current, and brings into operation when detecting that the load current increases to first preset value.The adaptive LDO circuit, there is extremely low quiescent dissipation in zero load, and the variation of heavily loaded load current can be tracked at any time, closed network can determine work according to the size of load current or not work in this way, avoid additional circuit load, whole power consumption is reduced, and circuit operation is a coherent process from low-load to high load, transient response is good.
Description
Technical field
This application involves technical field of integrated circuits more particularly to a kind of adaptive LDO circuits.
Background technique
With making constant progress for electronic product, power management techniques have obtained answering extensively in various electronic systems
With, however, no matter which kind of electronic product, all suffer from a problem, i.e., how efficiently to realize power management extend use
Service life and improving performance, therefore, just to power management chip, more stringent requirements are proposed for this.Most of chips are answered in view of a variety of
With scene, plurality of operating modes, including operating mode, standby mode etc. are generally used.
As shown in Figure 1, traditional structure is that (Low Dropout Regulator, low pressure difference linearity are steady using two kinds of LDO
Depressor) architecture combined forms, and it is that chip is powered respectively in different modes.Obvious this framework had both increased the complexity of circuit
Degree, and due to carrying out pattern switching by the Mode in Fig. 1, selection left side in the case of low-load when switch mode controls
Low-load path, the high load path on selection right side under high load condition, this control process is a discrete process, to defeated
The transient response of voltage is affected out, influences the performance of chip, and power consumption is higher.
Extremely low quiescent dissipation is consumed under unloaded load current conditions in view of this, how to design, and combines normal work
The complexity of operation mode circuit promotes the performance of chip, is still very important research topic.
Summary of the invention
In view of this, consuming pole in the case where guaranteeing unloaded load current conditions this application provides a kind of adaptive LDO circuit
On the basis of low quiescent dissipation, the complexity of normal mode of operation circuit is combined, promotes the performance of chip.
To achieve the goals above, this application provides following technical schemes:
A kind of adaptive LDO circuit, comprising: open loop networks circuit and closed network circuit, wherein
The open loop networks circuit is used to run when load current is lower than the first preset value；
The closed network circuit is used to detect the size of the load current, and is detecting the load current increase
It brings into operation when to first preset value.
Preferably, the open loop networks circuit includes: the first N-type metal-oxide-semiconductor MN1, the second N-type metal-oxide-semiconductor MN2, the first positive-negative-positive
Triode PNP1 and first resistor R1；Wherein,
The grid of the first N-type metal-oxide-semiconductor MN1 and drain electrode simultaneously with current source IBIAS2 and the second N-type metal-oxide-semiconductor
The grid of MN2 is connected, and the source electrode of the first N-type metal-oxide-semiconductor MN1 passes through the first resistor R1 and three pole of the first positive-negative-positive
The emitter of pipe PNP1 is connected, the base stage and grounded collector of the first PNP type triode PNP1；The second N-type metal-oxide-semiconductor
The drain electrode of MN2 is connected with power supply, and the source electrode of the second N-type metal-oxide-semiconductor MN2 passes through load current Rload in parallel and load electricity
Hold Cload ground connection.
Preferably, the closed network circuit includes: current mirroring circuit unit, detection circuit unit and the 9th N-type MOS
Pipe MN9；
The current mirroring circuit unit includes: third N-type metal-oxide-semiconductor MN3, the 4th N-type metal-oxide-semiconductor MN4, the 5th N-type metal-oxide-semiconductor
MN5, the 7th N-type metal-oxide-semiconductor MN7, the 8th N-type metal-oxide-semiconductor MN8, third p-type metal-oxide-semiconductor MP3 and the 4th p-type metal-oxide-semiconductor MP4；
The detection circuit unit includes: the first p-type metal-oxide-semiconductor MP1, the second p-type metal-oxide-semiconductor MP2, the 5th N-type metal-oxide-semiconductor
MN5, the 6th N-type metal-oxide-semiconductor MN6 and the 7th N-type metal-oxide-semiconductor MN7；
Wherein, the grid of the third N-type metal-oxide-semiconductor MN3 and drain electrode simultaneously with current source IBIAS1 and the 4th N-type
The grid of metal-oxide-semiconductor MN4, the 5th N-type metal-oxide-semiconductor MN5 grid be connected, the source level of the third N-type metal-oxide-semiconductor MN3, described the
The source grounding of the source electrode of four N-type metal-oxide-semiconductor MN4 and the 5th N-type metal-oxide-semiconductor MN5；
The drain electrode of the 4th NMOS tube MN4 and drain electrode, the 9th N-type metal-oxide-semiconductor of the third p-type metal-oxide-semiconductor MP3
The grid of MN9 is connected；
Grid and drain electrode, twoth P of the drain electrode of the 5th N-type metal-oxide-semiconductor MN5 with the first p-type metal-oxide-semiconductor MP1
The grid of type metal-oxide-semiconductor MP2 is connected；
The source electrode of the second N-type metal-oxide-semiconductor MN2 in the source level of the first p-type metal-oxide-semiconductor MP1 and the open loop networks circuit,
The source electrode of the 9th N-type metal-oxide-semiconductor MN9 is connected；
The source level of the second p-type metal-oxide-semiconductor MP2 is connected with the source level of the 6th N-type metal-oxide-semiconductor MN6, second p-type
Drain electrode and the grid of the 7th N-type metal-oxide-semiconductor MN7 and the grid phase of drain electrode, the 8th N-type metal-oxide-semiconductor MN8 of metal-oxide-semiconductor MP2
Even；
The source level of the 7th N-type metal-oxide-semiconductor MN7 and the source grounding of the 8th N-type metal-oxide-semiconductor MN8；
Grid and drain electrode, threeth P of the drain electrode of the 8th N-type metal-oxide-semiconductor MN8 with the 4th p-type metal-oxide-semiconductor MP4
The grid of type metal-oxide-semiconductor MP3 is connected；
The drain electrode of the 9th N-type metal-oxide-semiconductor MN9, the third p-type metal-oxide-semiconductor MP3 source level, the 6th N-type metal-oxide-semiconductor
The drain electrode of MN6 and the source level of the 4th p-type metal-oxide-semiconductor MP4 are connected with power supply；
The grid of the 6th N-type metal-oxide-semiconductor MN6 and the grid of the first N-type metal-oxide-semiconductor MN1 in the open loop networks circuit
It is connected with drain electrode.
Preferably, the breadth length ratio of the second N-type metal-oxide-semiconductor MN2 is the 50 of the breadth length ratio of the first N-type metal-oxide-semiconductor MN1
Times, current source IBIAS2 is 200nA.
Preferably, the breadth length ratio of the second N-type metal-oxide-semiconductor MN2 is the 100 of the breadth length ratio of the 6th N-type metal-oxide-semiconductor MN6
Times.
From the above technical scheme, it is made of this application provides a kind of open loop networks circuit and closed network circuit
Adaptive LDO circuit, open loop networks circuit are used under the conditions of light load currents, and closed network is used under the conditions of heavy load current.
The adaptive LDO circuit provided by the present application has extremely low quiescent dissipation in zero load, and can track heavily loaded load current at any time
Variation, such closed network can determine work or not work according to the size of load current, avoid additional circuit
Load, reduces whole power consumption, and be a coherent process from low-load to high load, will not influence output voltage
Transient response.
Detailed description of the invention
In order to illustrate the embodiments of the present invention more clearly with technical solution in the prior art, to embodiment and will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the schematic diagram of traditional LDO circuit made of two kinds of LDO architecture combineds；
Fig. 2 is a kind of structure chart for adaptive LDO circuit that the embodiment of the present application one provides；
Fig. 3 is a kind of schematic diagram for adaptive LDO circuit that the embodiment of the present application two provides.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
To guarantee on the basis of consuming extremely low quiescent dissipation under unloaded load current conditions, normal work mould is combined
The complexity of formula circuit promotes the performance of chip, this application provides a kind of adaptive LDO circuit of low-power consumption, specific side
Case is as described below:
Embodiment one
The embodiment of the present application one provides a kind of adaptive LDO circuit, as shown in Fig. 2, Fig. 2 is that the embodiment of the present application one mentions
A kind of structure chart of the adaptive LDO circuit supplied.The adaptive LDO circuit includes: open loop networks circuit 101 and closed network electricity
Road 102, wherein
Open loop networks circuit 101 is used to run when load current is lower than the first preset value；
Closed network circuit 102 is used for the size in detection load current, and is detecting that it is described that load current increases to
It brings into operation when the first preset value.
The adaptive LDO circuit that the embodiment of the present application one provides, comprising: open loop networks circuit and closed network circuit,
Wherein, open loop networks circuit is used to run when load current is lower than the first preset value；Closed network circuit is used in detection institute
The size of load current is stated, and is brought into operation when detecting that the load current increases to first preset value.The application
The adaptive LDO circuit that embodiment one provides, there is extremely low quiescent dissipation in zero load, and can track heavy duty load electricity at any time
The variation of stream, such closed network can determine work according to the size of load current or not work, and avoid additional electricity
Road load, reduces whole power consumption, and be a coherent process from low-load to high load, will not influence output voltage
Transient response.
Embodiment two
On the basis of example 1, the embodiment of the present application two provides a kind of specific circuit structure, as shown in figure 3,
For a kind of schematic diagram for adaptive LDO circuit that the embodiment of the present application two provides.The adaptive LDO circuit includes: open loop networks
Circuit and closed network circuit two parts.Open loop networks circuit is used in the case of light load currents, and circuit itself has extremely low quiet
State power consumption；Closed network circuit is used in the case of heavy load current, is capable of the size of real-time tracking load current, in load current
When increasing to certain value, closed network is started to work, and additional circuit load is avoided, and reduces whole power consumption, and due to
It is a coherent process from low-load to high load, will not influence the transient response of output voltage.
Specifically, open loop networks circuit is used to run when load current is lower than the first preset value；
Closed network circuit is used to detect the size of load current, and is detecting that load current increases to the first preset value
When bring into operation.
As shown in figure 3, open loop networks circuit includes: the first N-type metal-oxide-semiconductor MN1, the second N-type metal-oxide-semiconductor MN2, the first positive-negative-positive
Triode PNP1 and first resistor R1；Wherein,
The grid of first N-type metal-oxide-semiconductor MN1 and drain electrode while the grid with current source IBIAS2 and the second N-type metal-oxide-semiconductor MN2
Extremely it is connected, the source electrode of the first N-type metal-oxide-semiconductor MN1 is connected by first resistor R1 with the emitter of the first PNP type triode PNP1,
The base stage and grounded collector of first PNP type triode PNP1；The drain electrode of second N-type metal-oxide-semiconductor MN2 is connected with power supply, the second N-type
The source electrode of metal-oxide-semiconductor MN2 passes through load current Rload and load capacitance Cload ground connection in parallel.
Closed network circuit includes: current mirroring circuit unit, detection circuit unit and the 9th N-type metal-oxide-semiconductor MN9；
Current mirroring circuit unit includes: third N-type metal-oxide-semiconductor MN3, the 4th N-type metal-oxide-semiconductor MN4, the 5th N-type metal-oxide-semiconductor MN5,
Seven N-type metal-oxide-semiconductor MN7, the 8th N-type metal-oxide-semiconductor MN8, third p-type metal-oxide-semiconductor MP3 and the 4th p-type metal-oxide-semiconductor MP4；
Detection circuit unit includes: the first p-type metal-oxide-semiconductor MP1, the second p-type metal-oxide-semiconductor MP2, the 5th N-type metal-oxide-semiconductor MN5, the 6th
N-type metal-oxide-semiconductor MN6 and the 7th N-type metal-oxide-semiconductor MN7；
Wherein, the grid of third N-type metal-oxide-semiconductor MN3 and drain electrode simultaneously with current source IBIAS1 and the 4th N-type metal-oxide-semiconductor MN4
Grid, the 5th N-type metal-oxide-semiconductor MN5 grid be connected, the source electrode of the source level of third N-type metal-oxide-semiconductor MN3, the 4th N-type metal-oxide-semiconductor MN4
With the source grounding of the 5th N-type metal-oxide-semiconductor MN5；
The drain electrode of 4th NMOS tube MN4 is connected with the grid of the drain electrode of third p-type metal-oxide-semiconductor MP3, the 9th N-type metal-oxide-semiconductor MN9；
The drain electrode of 5th N-type metal-oxide-semiconductor MN5 and the grid of the first p-type metal-oxide-semiconductor MP1 and drain electrode, the second p-type metal-oxide-semiconductor MP2
Grid is connected；
The source level of first p-type metal-oxide-semiconductor MP1 and source electrode, the 9th N-type of the second N-type metal-oxide-semiconductor MN2 in open loop networks circuit
The source electrode of metal-oxide-semiconductor MN9 is connected；
The source level of second p-type metal-oxide-semiconductor MP2 is connected with the source level of the 6th N-type metal-oxide-semiconductor MN6, the leakage of the second p-type metal-oxide-semiconductor MP2
Pole is connected with the grid of the grid of the 7th N-type metal-oxide-semiconductor MN7 and drain electrode, the 8th N-type metal-oxide-semiconductor MN8；
The source level of 7th N-type metal-oxide-semiconductor MN7 and the source grounding of the 8th N-type metal-oxide-semiconductor MN8；
The drain electrode of 8th N-type metal-oxide-semiconductor MN8 and the grid of the 4th p-type metal-oxide-semiconductor MP4 and drain electrode, third p-type metal-oxide-semiconductor MP3
Grid is connected；
The drain electrode of 9th N-type metal-oxide-semiconductor MN9, the source level of third p-type metal-oxide-semiconductor MP3, the drain electrode of the 6th N-type metal-oxide-semiconductor MN6 and
The source level of four p-type metal-oxide-semiconductor MP4 is connected with power supply；
The grid and drain electrode phase of the grid of 6th N-type metal-oxide-semiconductor MN6 and the first N-type metal-oxide-semiconductor MN1 in open loop networks circuit
Even.
Specifically, in this application, can be configured to the parameter of the LOD circuit, for example, the second N-type metal-oxide-semiconductor MN2
Breadth length ratio can be 50 times of breadth length ratio of the first N-type metal-oxide-semiconductor MN1, current source IBIAS2 can be 200nA；Second N-type metal-oxide-semiconductor
The breadth length ratio of MN2 can be 100 times of the breadth length ratio of the 6th N-type metal-oxide-semiconductor MN6；Current source IBIAS1 can be 100nA；Third N-type
The breadth length ratio of metal-oxide-semiconductor MN3 is equal to the breadth length ratio of the 4th N-type metal-oxide-semiconductor MN4；The breadth length ratio of 7th N-type metal-oxide-semiconductor MN7 is equal to the 8th N
The breadth length ratio of type metal-oxide-semiconductor MN8；The breadth length ratio of third p-type metal-oxide-semiconductor MP3 is equal to the breadth length ratio of the 4th p-type metal-oxide-semiconductor MP4.
According to the setting of foregoing circuit parameter, current source IBIAS2 is equal to 200nA, the breadth length ratio of the second N-type metal-oxide-semiconductor MN2
It is 50 times of the breadth length ratio of the first N-type metal-oxide-semiconductor MN1, the breadth length ratio of MN2 is 100 times of the breadth length ratio of MN6, small in load current
In 10uA, i.e. when the first preset value is 10uA, the load current of the 6th N-type metal-oxide-semiconductor MN6 mirror image is less than 100nA, power supply source
IBIAS1 provides 100nA electric current, so the low voltage of B point, then, the 9th N-type metal-oxide-semiconductor MN9 cut-off, closed network circuit is not
Work, only open loop networks circuit work.
According to the setting of foregoing circuit parameter, when load current is greater than 10uA, the load of the 6th N-type metal-oxide-semiconductor MN6 mirror image
Electric current is greater than 100nA, and power supply source IBIAS1 provides 100nA electric current, so B point voltage is higher, then, the 9th N-type metal-oxide-semiconductor MN9
Conducting, closed network circuit are started to work, and biggish driving capability is provided.Specifically, output voltage can in circuit work
To indicate are as follows:
VOUT=VA=VBE1+R1*IBIAS2
Wherein, VA represents voltage at A point, and VBE1 represents the base stage and emitter pressure difference of PNP1 pipe, and IBIAS2 represents biasing
Electric current
In addition, it should be noted that, above-mentioned parameter setting is merely illustrative, it is not limited thereto in practical application, it can
To be arranged accordingly according to actual needs, the application is without limitation.
From the above technical scheme, adaptive LDO circuit that the embodiment of the present application two provides, under idle condition,
The quiescent current needed is very low, at this point, loop stability problem, circuit structure letter under open loop case, is not present in circuit work
Single, circuit work is good；Under fully loaded transportation condition, circuit can track the variation of load current, control closed network circuit work
Or do not work, it can be realized continuous control.Moreover, open loop networks circuit and being closed when biggish step occurs in load current
Loop network circuit can mutually switch rapidly, and transient response is good, and output ripple is smaller.In addition, the configuration of the present invention is simple, only
It is modified in open loop networks, reduces design complexities.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes that
A little elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in the process, method, article or apparatus that includes the element.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
The foregoing description of the disclosed embodiments makes professional and technical personnel in the field can be realized or use the application.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the application.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (5)
1. a kind of adaptive LDO circuit characterized by comprising open loop networks circuit and closed network circuit, wherein
The open loop networks circuit is used to run when load current is lower than the first preset value；
The closed network circuit is used to detect the size of the load current, and is detecting that the load current increases to institute
It brings into operation when stating the first preset value.
2. adaptive LDO circuit according to claim 1, which is characterized in that the open loop networks circuit includes: the first N
Type metal-oxide-semiconductor MN1, the second N-type metal-oxide-semiconductor MN2, the first PNP type triode PNP1 and first resistor R1；Wherein,
The grid of the first N-type metal-oxide-semiconductor MN1 and drain electrode simultaneously with current source IBIAS2 and the second N-type metal-oxide-semiconductor MN2
Grid be connected, the source electrode of the first N-type metal-oxide-semiconductor MN1 passes through the first resistor R1 and first PNP type triode
The emitter of PNP1 is connected, the base stage and grounded collector of the first PNP type triode PNP1；The second N-type metal-oxide-semiconductor
The drain electrode of MN2 is connected with power supply, and the source electrode of the second N-type metal-oxide-semiconductor MN2 passes through load current Rload in parallel and load electricity
Hold Cload ground connection.
3. adaptive LDO circuit according to any one of claims 1 or 2, which is characterized in that the closed network circuit
It include: current mirroring circuit unit, detection circuit unit and the 9th N-type metal-oxide-semiconductor MN9；
The current mirroring circuit unit includes: third N-type metal-oxide-semiconductor MN3, the 4th N-type metal-oxide-semiconductor MN4, the 5th N-type metal-oxide-semiconductor MN5,
Seven N-type metal-oxide-semiconductor MN7, the 8th N-type metal-oxide-semiconductor MN8, third p-type metal-oxide-semiconductor MP3 and the 4th p-type metal-oxide-semiconductor MP4；
The detection circuit unit include: the first p-type metal-oxide-semiconductor MP1, the second p-type metal-oxide-semiconductor MP2, the 5th N-type metal-oxide-semiconductor MN5,
6th N-type metal-oxide-semiconductor MN6 and the 7th N-type metal-oxide-semiconductor MN7；
Wherein, the grid of the third N-type metal-oxide-semiconductor MN3 and drain electrode simultaneously with current source IBIAS1 and the 4th N-type MOS
The grid of pipe MN4, the grid of the 5th N-type metal-oxide-semiconductor MN5 are connected, source level, the 4th N of the third N-type metal-oxide-semiconductor MN3
The source grounding of the source electrode of type metal-oxide-semiconductor MN4 and the 5th N-type metal-oxide-semiconductor MN5；
The drain electrode of the 4th NMOS tube MN4 and the drain electrode of the third p-type metal-oxide-semiconductor MP3, the 9th N-type metal-oxide-semiconductor MN9
Grid is connected；
Grid and drain electrode, the second p-type MOS of the drain electrode of the 5th N-type metal-oxide-semiconductor MN5 with the first p-type metal-oxide-semiconductor MP1
The grid of pipe MP2 is connected；
It is the source electrode of the source level of the first p-type metal-oxide-semiconductor MP1 and the second N-type metal-oxide-semiconductor MN2 in the open loop networks circuit, described
The source electrode of 9th N-type metal-oxide-semiconductor MN9 is connected；
The source level of the second p-type metal-oxide-semiconductor MP2 is connected with the source level of the 6th N-type metal-oxide-semiconductor MN6, the second p-type metal-oxide-semiconductor
The drain electrode of MP2 is connected with the grid of the grid of the 7th N-type metal-oxide-semiconductor MN7 and drain electrode, the 8th N-type metal-oxide-semiconductor MN8；
The source level of the 7th N-type metal-oxide-semiconductor MN7 and the source grounding of the 8th N-type metal-oxide-semiconductor MN8；
Grid and drain electrode, the third p-type MOS of the drain electrode of the 8th N-type metal-oxide-semiconductor MN8 with the 4th p-type metal-oxide-semiconductor MP4
The grid of pipe MP3 is connected；
The drain electrode of the 9th N-type metal-oxide-semiconductor MN9, the source level of the third p-type metal-oxide-semiconductor MP3, the 6th N-type metal-oxide-semiconductor MN6
The source level of drain electrode and the 4th p-type metal-oxide-semiconductor MP4 are connected with power supply；
Grid and the leakage of the grid and the first N-type metal-oxide-semiconductor MN1 in the open loop networks circuit of the 6th N-type metal-oxide-semiconductor MN6
Extremely it is connected.
4. adaptive LDO circuit according to claim 2, which is characterized in that the breadth length ratio of the second N-type metal-oxide-semiconductor MN2
It is 50 times of the breadth length ratio of the first N-type metal-oxide-semiconductor MN1, current source IBIAS2 is 200nA.
5. adaptive LDO circuit according to claim 3, which is characterized in that the breadth length ratio of the second N-type metal-oxide-semiconductor MN2
It is 100 times of the breadth length ratio of the 6th N-type metal-oxide-semiconductor MN6.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111506144A (en) * | 2020-05-20 | 2020-08-07 | 上海维安半导体有限公司 | Low-power consumption method applied to L DO |
| CN114740933A (en) * | 2022-04-27 | 2022-07-12 | 电子科技大学 | Internal reference power rail control circuit for high-voltage LDO (low dropout regulator) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111506144A (en) * | 2020-05-20 | 2020-08-07 | 上海维安半导体有限公司 | Low-power consumption method applied to L DO |
| CN114740933A (en) * | 2022-04-27 | 2022-07-12 | 电子科技大学 | Internal reference power rail control circuit for high-voltage LDO (low dropout regulator) |
| CN114740933B (en) * | 2022-04-27 | 2022-12-02 | 电子科技大学 | Internal reference power rail control circuit for high-voltage LDO (low dropout regulator) |
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| CN109213252B (en) | 2020-06-30 |
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