CN109195329A - A kind of pcb board and its DIP device - Google Patents
A kind of pcb board and its DIP device Download PDFInfo
- Publication number
- CN109195329A CN109195329A CN201811296946.1A CN201811296946A CN109195329A CN 109195329 A CN109195329 A CN 109195329A CN 201811296946 A CN201811296946 A CN 201811296946A CN 109195329 A CN109195329 A CN 109195329A
- Authority
- CN
- China
- Prior art keywords
- pin
- sub
- pcb board
- dip
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
- H05K3/3426—Leaded components characterised by the leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
The invention discloses a kind of pcb board and its DIP devices, including chip and the DIP pin being connect with chip, DIP pin include positioned at chip side, resistivity less than the first preset value the first sub- pin and far from chip side, connect with the first sub- pin, resistivity greater than the second preset value the second sub- pin；First preset value is not more than the second preset value, and pcb board is stretched out in the end of the second sub- pin.The DIP pin of the application design, since the resistivity of the first sub- pin is small, the resistivity of second sub- pin is big, so that chip can be by being sent to other places using pcb board ontology after the first sub- pin, and the second sub- pin of basic negligible resistance rate greatly, signal reflex is greatly reduced, signal quality is improved.In addition, pcb board is stretched out in the end of the second sub- pin, wave soldering is not influenced.DIP pin provided by the present application realize wave soldering well and ensure signal quality between balance.
Description
Technical field
The present invention relates to pin design fields, more particularly to a kind of pcb board and its DIP device.
Background technique
DIP (dual inline-pin package, dual-inline package technology) on the electronic products such as current server
Device is generally existing, and DIP device includes chip and DIP pin.The problem of due to wave-soldering, DIP pin must be beyond outside pcb boards
Certain length (usual 1mm or more), otherwise upper tin is bad, but DIP pin stretching pcb board part will lead to signal reflex and compare
Seriously (Fig. 1 is please referred to, Fig. 1 is signal flow schematic diagram when a kind of DIP device in the prior art is inserted into pcb board), in turn
Lead to signal quality degradation.As it can be seen that DIP pin in the prior art cannot achieve wave soldering and ensure signal quality it
Between balance.
Summary of the invention
The object of the present invention is to provide a kind of pcb board and its DIP devices, greatly reduce signal reflex, improve letter
Number quality, and do not influence wave soldering again, realize wave soldering well and ensure signal quality between balance.
In order to solve the above technical problems, the present invention provides a kind of DIP device, be applied to pcb board, including chip and with institute
The DIP pin of chip connection is stated, the DIP pin includes drawing positioned at chip side, resistivity less than the first son of the first preset value
Foot and far from chip side, connect with the described first sub- pin, resistivity greater than the second preset value the second sub- pin；Described first
Preset value is not more than the second preset value, and the pcb board is stretched out in the end of the second sub- pin.
Preferably, the described first sub- pin is copper pin.
Preferably, the described first sub- pin is tin-coated copper pin.
Preferably, the described second sub- pin is tungsten alloy pin.
Preferably, the described second sub- pin is nickel alloy pin.
Preferably, the pcb board 1mm is stretched out in the end of the described second sub- pin.
Preferably, the length of the described first sub- pin is equal to the thickness of the pcb board.
In order to solve the above technical problems, the present invention also provides a kind of pcb board, including pcb board ontology, it further include as above-mentioned
Described in any item DIP devices.
The DIP pin of the application design, since the resistivity of the first sub- pin is small, the resistivity of the second sub- pin is big, from
And the signal path that impedance can be selected small that chip is exported namely chip can by after the first sub- pin using pcb board
Ontology is sent to other places, and the second sub- pin that basic negligible resistance rate is big, greatly reduces signal reflex, improves signal
Quality.In addition, pcb board is stretched out in the end of the second sub- pin, wave soldering is not influenced.As it can be seen that DIP pin provided by the present application is very
Balance between realizing wave soldering well and ensuring signal quality.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to institute in the prior art and embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the invention
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is signal flow schematic diagram when a kind of DIP device in the prior art is inserted into pcb board；
Fig. 2 is a kind of structural schematic diagram of DIP device provided by the invention；
Fig. 3 is signal flow schematic diagram when one of the application DIP device is inserted into pcb board.
Specific embodiment
Core of the invention is to provide a kind of pcb board and its DIP device, greatly reduces signal reflex, improves letter
Number quality, and do not influence wave soldering again, realize wave soldering well and ensure signal quality between balance.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Referring to figure 2., Fig. 2 is a kind of structural schematic diagram of DIP device provided by the invention, which is applied to PCB
Plate, including chip 1 and the DIP pin connecting with chip 1, DIP pin includes default less than first positioned at 1 side of chip, resistivity
First sub- pin 21 of value and far from 1 side of chip, connect with the first sub- pin 21, resistivity it is second sub greater than the second preset value
Pin 22；First preset value is not more than the second preset value, and pcb board is stretched out in the end of the second sub- pin 22.
It can be seen that, DIP pin in the prior art is all made of the small metallic conductor of resistivity from background technique, thus
So that the signal that chip 1 exports can return again to pcb board by entire DIP pin path and be sent to other places, signal reflex is tighter
Weight.
In order to solve the above-mentioned technical problem, DIP pin is divided into two parts, specifically when designing DIP pin by the application
Ground, DIP pin include the first sub- pin 21 and the second sub- pin 22, and the first sub- 21 one side of pin will undertake and pcb board hardware
On the other hand the function of connection will undertake the function of the signal on transmission pcb board or between other external modules and chip 1.
In order to realize the above functions, the first sub- pin 21 is located at 1 side of chip, connect with chip 1, and the resistivity of the first sub- pin 21 is small
In the first preset value, namely require the resistivity of the first sub- pin 21 small as far as possible, to reduce signal transfer impedance.Second son
Pin 22 is primarily to undertake the effect connecting with CPB plate, namely to meet the requirement of wave soldering.In order to realize the function
Can, the resistivity of the second sub- pin 22 is greater than the second preset value, and the first preset value is not more than the second preset value, the second sub- pin
Pcb board is stretched out in 22 end.
Based on this, since the resistivity of the first sub- pin 21 is small, the resistivity of the second sub- pin 22 is big, so that chip
1 output signal transmission when impedance can be selected small path namely chip 1 can by the first sub- pin 21 after be directly over
Pcb board ontology is sent to other places, and second sub- this path of pin 22 that basic negligible resistance rate is big, greatly reduces signal
Reflection, improves signal quality.It specifically can refer to Fig. 3, Fig. 3 is signal when one of the application DIP device is inserted into pcb board
Flow to schematic diagram.In addition, pcb board is stretched out in the end of the second sub- pin 22, wave soldering is not influenced.As it can be seen that provided by the present application
DIP pin realize wave soldering well and ensure signal quality between balance.
In addition, the application does not limit the specific value of the first preset value and the second preset value particularly, according to reality
Border situation is determined.The application does not also limit the type of chip 1 particularly.
As a kind of preferred embodiment, the first sub- pin 21 is copper pin.
Specifically, select copper pin as the first sub- pin 21, on the one hand, the resistivity of copper is small, good conductivity, at 20 DEG C
When resistivity be 1.72*10-8Ω m, conducive to the transmission of signal；On the other hand, the intensity of copper is big, convenient for pcb board and chip 1
Connection.
As a kind of preferred embodiment, the first sub- pin 21 is tin-coated copper pin.
Specifically, in order to increase the solderability and corrosion resistance of DIP pin, the present embodiment has also selected tin-coated copper pin to make
For the first sub- pin 21.It is, of course, also possible to select other kinds of metallic conductor as the first sub- pin 21, the application is herein not
Make it is special limit, determine according to the actual situation.
As a kind of preferred embodiment, the second sub- pin 22 is tungsten alloy pin.
As a kind of preferred embodiment, the second sub- pin 22 is nickel alloy pin.
Specifically, it is contemplated that the pin that select resistivity big can be selected as the second sub- pin 22, the second sub- pin 22
With tungsten alloy pin or nickel alloy pin, on the one hand, resistivity is big, and on the other hand, intensity is big, is conducive to DIP pin and and PCB
The welding of plate.The type of the application pin 22 sub- for second is not particularly limited, and is able to achieve the scheme of the application.
As a kind of preferred embodiment, pcb board 1mm is stretched out in the end of the second sub- pin 22.
Specifically, although the application is larger in view of the resistivity ratio of the second sub- pin 22, the signal that chip 1 exports
It still has on a small quantity by the second sub- pin 22, from this angle, the shorter second sub- pin 22 the better, but it is also contemplated that wave crest
The needs of welding, the second sub- pin 22 cannot be too short, therefore, in order to realize the balance of wave soldering and signal quality, this implementation
Pcb board 1mm is stretched out in the end of the second sub- pin 22 in example, has not only been able to satisfy the demand of wave soldering at this time, but also can subtract as much as possible
The signal decaying of few signal path.
As a kind of preferred embodiment, the length of the first sub- pin 21 is equal to the thickness of pcb board.
Specifically, the length of the first sub- pin 21 is equal to the thickness of pcb board, so that guarantee that chip 1 connect with pcb board can
By property, guarantee signal transmission.The length of the application pin 21 sub- for first and the thickness of pcb board do not limit particularly, the
As long as a sub- pin 21 does not stretch out pcb board.
It further include the DIP device such as any of the above-described the present invention also provides a kind of pcb board, including pcb board ontology.
Above-described embodiment please referred to for the introduction of the DIP device in pcb board provided by the invention, the present invention is herein no longer
It repeats.
It should be noted that in the present specification, relational terms such as first and second and the like are used merely to one
A entity or operation with another entity or operate distinguish, without necessarily requiring or implying these entities or operation it
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to
Cover non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or setting
Standby intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in the process, method, article or apparatus that includes the element.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (8)
1. a kind of DIP device is applied to pcb board, which is characterized in that including chip and the DIP pin connecting with the chip, institute
Stating DIP pin includes positioned at chip side, resistivity less than the first sub- pin of the first preset value and far from chip side, with described the
One sub- pin connection, resistivity are greater than the second sub- pin of the second preset value；First preset value is not more than the second preset value,
The pcb board is stretched out in the end of the second sub- pin.
2. DIP device as described in claim 1, which is characterized in that the first sub- pin is copper pin.
3. DIP device as described in claim 1, which is characterized in that the first sub- pin is tin-coated copper pin.
4. DIP device as described in claim 1, which is characterized in that the second sub- pin is tungsten alloy pin.
5. DIP device as described in claim 1, which is characterized in that the second sub- pin is nickel alloy pin.
6. DIP device as described in claim 1, which is characterized in that the pcb board is stretched out in the end of the second sub- pin
1mm。
7. DIP device as claimed in any one of claims 1 to 6, which is characterized in that the length of the first sub- pin is equal to institute
State the thickness of pcb board.
8. a kind of pcb board, which is characterized in that further include such as the described in any item DIP dresses of claim 1-7 including pcb board ontology
It sets.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811296946.1A CN109195329B (en) | 2018-11-01 | 2018-11-01 | PCB and DIP device thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811296946.1A CN109195329B (en) | 2018-11-01 | 2018-11-01 | PCB and DIP device thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109195329A true CN109195329A (en) | 2019-01-11 |
| CN109195329B CN109195329B (en) | 2021-04-30 |
Family
ID=64941457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811296946.1A Active CN109195329B (en) | 2018-11-01 | 2018-11-01 | PCB and DIP device thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109195329B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06224364A (en) * | 1992-01-29 | 1994-08-12 | Fujitsu Ltd | Terminal pin |
| CN1141572A (en) * | 1995-07-25 | 1997-01-29 | 北京汇众实业总公司 | Tech. for soldering copper foil for conducting heavy current of circuit board |
| CN103077830A (en) * | 2013-02-25 | 2013-05-01 | 南通新三能电子有限公司 | Pin-molded electrolytic capacitor |
| CN203968495U (en) * | 2011-12-29 | 2014-11-26 | 株式会社村田制作所 | High-frequency signal circuit and electronic equipment |
| CN104582290A (en) * | 2015-01-30 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | High-speed line impedance continuity realization method |
| CN106576431A (en) * | 2014-08-12 | 2017-04-19 | 领先仿生公司 | Methods for connecting a wire to a feedthrough pin and apparatus including the same |
-
2018
- 2018-11-01 CN CN201811296946.1A patent/CN109195329B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06224364A (en) * | 1992-01-29 | 1994-08-12 | Fujitsu Ltd | Terminal pin |
| CN1141572A (en) * | 1995-07-25 | 1997-01-29 | 北京汇众实业总公司 | Tech. for soldering copper foil for conducting heavy current of circuit board |
| CN203968495U (en) * | 2011-12-29 | 2014-11-26 | 株式会社村田制作所 | High-frequency signal circuit and electronic equipment |
| CN103077830A (en) * | 2013-02-25 | 2013-05-01 | 南通新三能电子有限公司 | Pin-molded electrolytic capacitor |
| CN106576431A (en) * | 2014-08-12 | 2017-04-19 | 领先仿生公司 | Methods for connecting a wire to a feedthrough pin and apparatus including the same |
| CN104582290A (en) * | 2015-01-30 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | High-speed line impedance continuity realization method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109195329B (en) | 2021-04-30 |
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