CN109194890B - Image sensor pixel circuit and working method thereof - Google Patents
Image sensor pixel circuit and working method thereof Download PDFInfo
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- CN109194890B CN109194890B CN201811286238.XA CN201811286238A CN109194890B CN 109194890 B CN109194890 B CN 109194890B CN 201811286238 A CN201811286238 A CN 201811286238A CN 109194890 B CN109194890 B CN 109194890B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
- H04N25/58—Control of the dynamic range involving two or more exposures
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Abstract
An image sensor pixel circuit and method of operation thereof, the circuit comprising: a photodiode; the source electrode and the drain electrode of the transmission transistor are respectively and correspondingly connected with the photodiode connection and the first floating diffusion point; the source electrode and the drain electrode of the first additional transistor are respectively and correspondingly connected with the first floating diffusion point and the second floating diffusion point; the drain electrode and the source electrode of the reset transistor are respectively and correspondingly connected with the power line connection and the second floating diffusion point; a capacitor connected to the second floating diffusion point; the drain electrode and the source electrode of the second additional transistor are respectively and correspondingly connected with the power line and the first floating diffusion point, and the second additional transistor and the first additional transistor are suitable for executing a plurality of alternate releasing steps in the extended exposure time sequence step so that the charges stored in the first floating diffusion point are transmitted to the power line; and a column readout line adapted to read out potential information of the first floating diffusion. The performance of the image sensor pixel circuit is improved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to an image sensor pixel circuit and a working method thereof.
Background
An image sensor is a semiconductor device that converts an optical signal into an electrical signal.
Image sensors are classified into Complementary Metal Oxide (CMOS) image sensors and Charge Coupled Device (CCD) image sensors. The CMOS image sensor has the advantages of simple process, easiness in integration of other devices, small size, light weight, low power consumption, low cost and the like. Therefore, with the development of image sensing technology, CMOS image sensors are increasingly used in various electronic products instead of CCD image sensors. At present, CMOS image sensors have been widely used in still digital cameras, digital video cameras, medical imaging devices, vehicle imaging devices, and the like.
However, the performance of the existing image sensor is to be improved.
Disclosure of Invention
The invention provides an image sensor pixel circuit and a working method thereof, which aims to improve the performance of the image sensor pixel circuit.
To solve the above problem, the present invention provides an image sensor pixel circuit, comprising: the image sensor pixel circuit is used for performing a main exposure timing sequence step and an extended exposure timing sequence step, and comprises: a photodiode; the source electrode of the transmission transistor is connected with the photodiode, and the drain electrode of the transmission transistor is connected with the first floating diffusion point; a first additional transistor, wherein the source of the first additional transistor is connected with a first floating diffusion point, and the drain of the first additional transistor is connected with a second floating diffusion point; the drain electrode of the reset transistor is connected with a power line, and the source electrode of the reset transistor is connected with a second floating diffusion point; a capacitor connected to the second floating diffusion point; the drain electrode of the second additional transistor is connected with a power line, the source electrode of the second additional transistor is connected with the first floating diffusion point, and the second additional transistor and the first additional transistor are suitable for executing a plurality of alternate releasing steps in the extended exposure time sequence step so that the charges stored in the first floating diffusion point are transmitted to the power line; a column readout line adapted to read out potential information of the first floating diffusion.
Optionally, the second additional transistor is adapted to be in a conducting state during the releasing step, and the first additional transistor is adapted to be in a disconnecting state during the releasing step.
Optionally, the method further includes: the grid electrode of the source following transistor is connected with the first floating diffusion point, and the drain electrode of the source following transistor is connected with a power line; a select transistor having a drain connected to the source of the source follower transistor and a source connected to the column readout line.
Optionally, the capacitor has a first end and a second end opposite to each other, the first end is connected to the second floating diffusion point, and the second end is grounded.
Optionally, the photodiode has a forward connection terminal and a reverse connection terminal, the forward connection terminal is connected to the source of the transmission transistor, and the reverse connection terminal is grounded.
The invention also provides a working method of the pixel circuit of the image sensor, which comprises the following steps: providing the image sensor pixel circuit; performing a main exposure timing sequence step, wherein in the main exposure timing sequence step, the reset transistor, the transmission transistor and the second additional transistor are all in an off state, and the first additional transistor is in an on state; performing a main readout timing step that is continuous with the main exposure timing step after the main exposure timing step is performed, the second additional transistor being in an off state in the main readout timing step, the main readout timing step including: when the first additional transistor is in an off state, the transmission transistor is turned on, so that the charge in the photodiode carries out first charging on the first floating diffusion point; after the first charging is carried out, under the condition that the first additional transistor is in a disconnected state, the column read-out line carries out first signal data acquisition on the potential information of the first floating diffusion point; after first signal data are collected, the transmission transistor is conducted under the condition that the first additional transistor is in a conducting state, and charges in the photodiode carry out second charging on the first floating diffusion point and the second floating diffusion point; after the second charging, under the condition that the first additional transistor is in a conducting state, the column read-out line carries out second signal data acquisition on the potential information of the first floating diffusion point; performing an extended exposure timing step in which both the reset transistor and the transfer transistor are in an off state, the extended exposure timing step comprising: the second additional transistor and the first additional transistor perform a plurality of alternate release steps to enable the charges stored in the first floating diffusion point to be transmitted to a power line; performing an extended readout sequence step subsequent to the extended exposure sequence step, in which the first additional transistor is in an on state and the transfer transistor and the second additional transistor are in an off state, the extended readout sequence step comprising: and the column readout line is used for carrying out third signal data acquisition on the potential information of the first floating diffusion point.
Optionally, in each release step, the second additional transistor is in a conducting state, and the first additional transistor is in a disconnecting state.
Optionally, in the extended exposure timing step, when the first additional transistor is in an on state, the second additional transistor is in an off state.
Optionally, the reset transistor is in a turned-off state from a start time of the main readout timing step to a termination time of the second signal data acquisition.
Optionally, the main readout timing step further includes: before first charging, under the condition that the first additional transistor, the reset transistor and the transmission transistor are in an off state, the column read-out line carries out first reference data acquisition on potential information of a first floating diffusion point; and acquiring first effective signal data according to the difference between the data acquired by the first reference data and the data acquired by the first signal data.
Optionally, the main readout timing step further includes: after the second signal data is acquired, performing main reset operation, wherein in the main reset operation, the reset transistor and the first additional transistor are in a conducting state, and the transmission transistor is in a disconnecting state; after the main reset operation is carried out, when the reset transistor and the transmission transistor are in a disconnected state and the first additional transistor is in a conducting state, the column read-out line carries out second reference data acquisition on the potential information of the first floating diffusion point; and acquiring second effective signal data according to the difference between the data acquired by the second reference data and the data acquired by the second signal data.
Optionally, the step of extending the readout timing further includes: after the third signal data is acquired, performing extended reset operation, wherein in the extended reset operation, the reset transistor is in a conducting state; after the expansion reset operation is carried out, the column readout line carries out third reference data acquisition on the potential information of the first floating diffusion point when the reset transistor is in a disconnected state; and acquiring third effective signal data according to the difference between the data acquired by the third reference data and the data acquired by the third signal data.
Optionally, after the main exposure timing step and the main readout timing step are performed, the extended exposure timing step and the extended readout timing step are performed.
Optionally, the method further includes: performing an extended clear step after performing the main readout timing step and before performing the extended exposure timing step; in the extended clearing step, the reset transistor, the first additional transistor, and the transfer transistor are in an on state, the second additional transistor is in an off state, and the selection transistor is in an off state.
Optionally, the method further includes: before the main exposure sequence step, a main emptying step is carried out; in the main clearing step, the reset transistor, the first additional transistor and the transfer transistor are in a conducting state, the second additional transistor is in an off state, and the selection transistor is in an off state.
Optionally, after the step of extending the exposure timing and the step of extending the readout timing, the step of main exposure timing and the step of main readout timing are performed; the main exposure timing step and the extended readout timing step are consecutive.
Optionally, the method further includes: before the extended exposure time sequence step, an extended clearing step is carried out; in the extended clearing step, the reset transistor, the first additional transistor, and the transfer transistor are in an on state, the second additional transistor is in an off state, and the selection transistor is in an off state.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the working method of the pixel circuit of the image sensor provided by the technical scheme of the invention, in the step of carrying out the main exposure time sequence, the first additional transistor is in a conducting state, so that when the photodiode is in an overexposure condition, photo-generated electrons in the photodiode can overflow to the first floating diffusion point and the second floating diffusion point through the transmission transistor. Since the second additional transistor is in an off state in the main exposure timing step and the main readout timing step, the charge of the first floating diffusion point is not affected by the second additional transistor and the charge of the first floating diffusion point is not removed in the main exposure timing step and the main readout timing step. And carrying out first charging when the first additional transistor is in an off state, so that photo-generated electrons in the photodiode are transferred to the first floating diffusion point, and because the full-well capacitance of the first floating diffusion point is small, the data acquired by the first signal data is used for representing the information of the image in a dark place. And carrying out second charging when the first additional transistor is in a conducting state, wherein the second charging enables the photo-generated electrons in the photodiode to be transferred to the first floating diffusion point and the second floating diffusion point, and the photo-generated electrons from the photodiode are mainly stored by the parasitic capacitance of the first floating diffusion point and the capacitance. Because the full-well capacitance shared by the first floating diffusion point and the capacitor is larger than that of the first floating diffusion point, under the condition that the photodiode is exposed, the parasitic capacitor of the first floating diffusion point and the capacitor have enough capacitance space to store photo-generated electrons generated by the photodiode, and therefore the image brightness represented by the data acquired by the second signal data is larger than that of the data acquired by the first signal data.
In the extended exposure timing step, the second additional transistor and the first additional transistor perform a plurality of alternate discharging steps to transfer the charges stored in the first floating diffusion point to the power line. In the case of overexposure of the photodiode, the releasing step transfers the photo-generated electrons overflowing from the photodiode to the first floating diffusion point to the power supply line, and the photo-generated electrons overflowing from the photodiode are not stored by the first floating diffusion point and the capacitor within the time of the releasing step. And between adjacent release steps, under the condition of overexposure of the photodiode, photogenerated electrons in the photodiode overflow to the first floating diffusion point and the second floating diffusion point, and the photogenerated electrons from the photodiode are mainly stored by the parasitic capacitance of the first floating diffusion point and the capacitance. This results in a smaller number of photogenerated electrons overflowing from the photodiode during the extended exposure timing step, and therefore the parasitic capacitance of the first floating diffusion point and the capacitance have sufficient capacitance space to store photogenerated electrons from the photodiode. The brightness of the image that can be characterized by the data from the third signal data acquisition is greater than the brightness of the image that can be characterized by the data from the second signal data acquisition, thus improving the dynamic range. In conclusion, the performance of the pixel circuit of the image sensor is improved.
Further, after the extended exposure time sequence step and the extended readout time sequence step are performed, the main exposure time sequence step and the main readout time sequence step are performed, and the main exposure time sequence step and the extended readout time sequence step are continuous, so that the actual exposure time corresponding to the data acquired by the first signal data is increased under the same frame rate, and the detail loss of the dark part in the image is reduced.
Drawings
FIG. 1 is a schematic diagram of an image sensor pixel circuit;
FIG. 2 is a schematic diagram of an image sensor pixel circuit according to an embodiment of the invention;
FIG. 3 is a flow chart of a method for operating a pixel circuit of an image sensor according to an embodiment of the invention;
FIG. 4 is a timing diagram illustrating the operation of the pixel circuit of the image sensor according to one embodiment of the present invention;
fig. 5 is another timing diagram illustrating the operation of the pixel circuit of the image sensor according to an embodiment of the present invention.
Detailed Description
As described in the background, the prior art forms image sensor pixel circuits with poor performance.
An image sensor pixel circuit, please refer to fig. 1, comprising: a photodiode; a pass transistor PtxIs connected with the forward connecting end of the photodiode; a first floating diffusion point sfd, a first floating diffusion point sfd and a transfer transistor PtxIs connected with the drain electrode of the transistor; additional transistor PssAdding a transistor PssThe source electrode is connected with the first floating diffusion point sfd; a second floating diffusion point lfd, a second floating diffusion point lfd and an additional transistor PssIs connected with the drain electrode of the transistor; reset crystalBody pipe PrstReset transistor PrstIs connected to the power supply line vdd, and a reset transistor PrstIs connected with the second floating diffusion point lfd; one end of the capacitor C is connected with the second floating diffusion point lfd, and the other end of the capacitor C is connected with the ground wire; source follower transistor PsfSource follower transistor PsfIs connected to a first floating diffusion point sfd, the source following transistor PsfIs connected to the power supply line vdd; row select transistor PselSaid row select transistor PselAnd the source follower transistor PsfThe row select transistor P, the source connection of the row select transistor PselIs connected to the column readout line bL.
For the image sensor pixel circuit in fig. 1, the exposure time of each frame is the same, and the exposure adopts a long exposure time, so that the stroboscopic phenomenon is overcome.
For the image sensor pixel circuit in fig. 1, according to time sequence, information of a dark place is read out firstly, the data is first data, specifically, after photoelectrons of a photodiode are transferred to a first floating diffusion point sfd, voltage change is generated at the first floating diffusion point sfd, and the potential of the first floating diffusion point sfd passes through a row selection transistor PselAnd a source follower transistor PsfRead out to obtain first data; reading out the information of the bright place according to the time sequence, wherein the data is second data, in particular, photoelectrons of the photodiode pass through the transmission transistor PtxAnd an additional transistor PssTransferring to a second floating diffusion point lfd and a first floating diffusion point sfd, storing photoelectrons from the photodiode corresponding to second data mainly by a capacitor C and a parasitic capacitor of the first floating diffusion point sfd, generating voltage change at the first floating diffusion point sfd, and enabling the potential of the first floating diffusion point sfd to pass through a row selection transistor PselAnd a source follower transistor PsfIs read out to obtain second data. And a picture image is obtained by fusing the first data and the second data, and the dynamic range of the picture image is high.
In the pixel circuit of the image sensor in fig. 1, when the ratio of the capacitance value of the capacitor C to the parasitic capacitance of the first floating diffusion point sfd is 16-32, the dynamic range of the pixel circuit of the image sensor can reach 90dB to 100 dB.
However, in practice, the ratio of the capacitance C to the capacitance of the first floating diffusion cannot take a very high value, for reasons including: the capacitor C is manufactured in one pixel, and the occupied area of the capacitor C is limited, so that the capacitor C cannot be large; if the ratio of the capacitance C to the capacitance of the first floating diffusion point is large, such as 100, the signal-to-noise ratio of the transition region of the first data and the second data is too small, which results in the degradation of the image quality after the second data and the first data are fused.
In summary, since the improvement of the ratio of the capacitance C to the capacitance of the first floating diffusion point is limited, the improvement of the dynamic range of the pixel circuit of the image sensor is limited. Image sensor pixel circuits that achieve over 120dB dynamic range are desirable in practical applications, such as: ultra-high dynamic range image sensor pixel circuits are needed in tunnel environments, all-weather monitoring environments, or in the automotive field.
On this basis, the invention provides an image sensor pixel circuit, comprising: a photodiode; the source electrode of the transmission transistor is connected with the photodiode, and the drain electrode of the transmission transistor is connected with the first floating diffusion point; the source electrode of the first additional transistor is connected with the first floating diffusion point, and the drain electrode of the first additional transistor is connected with the second floating diffusion point; the drain electrode of the reset transistor is connected with a power line, and the source electrode of the reset transistor is connected with a second floating diffusion point; a capacitor connected to the second floating diffusion point; the drain electrode of the second additional transistor is connected with a power line, the source electrode of the second additional transistor is connected with the first floating diffusion point, and the second additional transistor and the first additional transistor are suitable for executing a plurality of alternate releasing steps in the extended exposure time sequence step so that the charges stored in the first floating diffusion point are transmitted to the power line; a column readout line adapted to read out potential information of the first floating diffusion. The performance of the image sensor pixel circuit is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
An embodiment of the present invention provides an image sensor pixel circuit, referring to fig. 2, where the image sensor pixel circuit is configured to perform a main exposure timing step and an extended exposure timing step, and includes:
a photodiode 200;
a transfer transistor 210, a source of the transfer transistor 210 being connected to the photodiode 200, a drain of the transfer transistor 210 being connected to a first floating diffusion FD 1;
a first additional transistor 220, a source of the first additional transistor 220 being connected to the first floating diffusion point FD1, a drain of the first additional transistor 220 being connected to the second floating diffusion point FD 2;
a reset transistor 230, a drain of the reset transistor 230 being connected to a power line L _ VDD, a source of the reset transistor 230 being connected to a second floating diffusion FD 2;
a capacitor 240, the capacitor 240 being connected to the second floating diffusion point FD 2;
a second additional transistor 250, a drain of the second additional transistor 250 being connected to the power line L _ VDD, a source of the second additional transistor 250 being connected to the first floating diffusion FD1, the second additional transistor 250 and the first additional transistor 220 being adapted to perform a plurality of alternate discharging steps in the extended exposure timing step, so that the charges stored in the first floating diffusion FD1 are transferred to the power line L _ VDD;
a column readout line BL adapted to read out potential information of the first floating diffusion FD 1.
The second additional transistor 250 is adapted to be in a conducting state during the releasing step and the first additional transistor 220 is adapted to be in a disconnected state during the releasing step.
The capacitor 240 has opposite first and second terminals, the first terminal being connected to the second floating diffusion FD2, and the second terminal being connected to ground.
The photodiode 200 has a forward connection terminal connected to the source of the transfer transistor 210 and a reverse connection terminal connected to the ground.
The image sensor pixel circuit further comprises: a source follower transistor 260, a gate of the source follower transistor 260 being connected to the first floating diffusion FD1, a drain of the source follower transistor 260 being connected to a power supply line L _ VDD; a selection transistor 270, a drain of the selection transistor 270 being connected to a source of the source follower transistor 260, and a source of the selection transistor 270 being connected to the column readout line BL.
In this embodiment, the requirement of the ratio of the capacitance value of the capacitor 240 to the capacitance of the first floating diffusion point FD1 is low, the area occupied by the capacitor 240 is small, the capacitor 240 is easily fabricated in one pixel, and secondly, the fusion of the subsequent second effective signal data and the first effective signal data is facilitated, and the image quality after the fusion of the second effective signal data and the first effective signal data is good.
In the present embodiment, the ratio of the capacitance of the capacitor 240 to the capacitance of the first floating diffusion point FD1 is 16 to 40, such as 16 to 32.
Referring to fig. 3, the present embodiment further provides a method for operating a pixel circuit of an image sensor, including the following steps:
s01: providing the image sensor pixel circuit described above (see fig. 2);
s02: performing a main exposure timing step in which the reset transistor 230, the transfer transistor 210, and the second additional transistor 250 are all in an off state, and the first additional transistor 220 is in an on state;
s03: after the main exposure timing step, performing a main readout timing step that is consecutive to the main exposure timing step, in which the second additional transistor 250 is in an off state, the main readout timing step including: in the off state of the first additional transistor 220, the transfer transistor 210 is turned on, so that the charge in the photodiode 200 first charges the first floating diffusion FD 1; after the first charging, when the first additional transistor 220 is in an off state, the column readout line BL performs first signal data acquisition on potential information of the first floating diffusion FD 1; after the first signal data acquisition is performed, the transfer transistor 210 is turned on when the first additional transistor 220 is in a conducting state, so that the charge in the photodiode 200 performs a second charge on the first floating diffusion point FD1 and the second floating diffusion point FD 2; after the second charging, when the first additional transistor 220 is in a conducting state, the column readout line BL performs second signal data acquisition on the potential information of the first floating diffusion point FD 1;
s04: an extended exposure timing step is performed in which both the reset transistor 230 and the transfer transistor 210 are in an off state, the extended exposure timing step including: the second additional transistor 250 and the first additional transistor 220 perform several alternate discharging steps to transfer the charges stored in the first floating diffusion FD1 to the power line L _ VDD;
s05: after the extended exposure timing step is performed, an extended readout timing step is performed which is consecutive to the extended exposure timing step, in which the first additional transistor 220 is in a turned-on state and the transfer transistor 210 and the second additional transistor 250 are in a turned-off state, the extended readout timing step including: the column readout line BL performs third signal data acquisition on the potential information of the first floating diffusion point FD 1.
Fig. 4 is a timing diagram illustrating operation of the pixel circuit of the image sensor of fig. 2.
Referring to fig. 4, v (rsel) is a timing signal for the gate of the selection transistor 270, and when v (rsel) is high, the selection transistor 270 is in an on state, and when v (rsel) is low, the selection transistor 270 is in an off state.
Referring to fig. 4, v (rst) is a timing signal of the gate of the reset transistor 230, and when v (rst) is high, the reset transistor 230 is in an on state, and when v (rst) is low, the reset transistor 230 is in an off state.
Referring to fig. 4, v (tg) is a timing signal of the gate of the transfer transistor 210, when v (tg) is high, the transfer transistor 210 is in an on state, and when v (tg) is low, the transfer transistor 210 is in an off state.
Referring to fig. 4, V (SS1) is a timing signal of the gate of the first additional transistor 220, and the first additional transistor 220 is in a turn-on state when V (SS1) is high level and the first additional transistor 220 is in a turn-off state when V (SS1) is low level.
Referring to fig. 4, V (SS2) is a timing signal of the gate of the second additional transistor 250, and the second additional transistor 250 is in a turn-on state when V (SS2) is high level and the second additional transistor 250 is in a turn-off state when V (SS2) is low level.
In this embodiment, after the main exposure timing step and the main readout timing step are performed, the extended exposure timing step and the extended readout timing step are performed.
In this embodiment, the method further includes: before the main exposure sequence step, a main clear step is performed. The main clearing step clears the charge in the photodiode 200.
In the main clearing step, the reset transistor 230, the first additional transistor 220 and the transfer transistor 210 are in a conducting state, the second additional transistor 250 is in an off state, and the selection transistor 270 is in an off state.
In the main exposure timing step, the reset transistor 230, the transfer transistor 210, and the second additional transistor 250 are all in an off state, the first additional transistor 220 is in an on state, and the selection transistor 270 is in an off state.
After the main exposure timing step, a main readout timing step is performed. In the main readout timing step, the second additional transistor 250 is in an off state and the selection transistor 270 is in an on state.
The main readout timing step includes: the column readout line BL performs first reference data acquisition of potential information of the first floating diffusion FD1 with the first additional transistor 220, the reset transistor 230, and the transfer transistor 210 in an off state.
The transfer transistor 210 and the reset transistor 230 are always in an off state from the start time of the main readout timing step to the end time of the first reference data acquisition.
The main readout timing step further comprises: after the first reference data acquisition is performed, the transfer transistor 210 is turned on with the first additional transistor 220 in an off state, so that the charge in the photodiode 200 first charges the first floating diffusion FD 1; after the first charging, the column readout line BL performs first signal data acquisition of potential information of the first floating diffusion FD1 with the first additional transistor 220 in the off state.
In the first charge, the transfer transistor 210 is in a turned-on state, the reset transistor 230 is in a turned-off state, and the first additional transistor 220 is in a turned-off state.
In the first signal data acquisition, the first additional transistor 220, the transfer transistor 210, and the reset transistor 230 are in an off state.
And acquiring first effective signal data according to the difference between the data acquired by the first reference data and the data acquired by the first signal data.
The main readout timing step further comprises: after the first signal data acquisition is performed, the transfer transistor 210 is turned on when the first additional transistor 220 is in a conducting state, so that the charge in the photodiode 200 performs a second charge on the first floating diffusion point FD1 and the second floating diffusion point FD 2; after the second charging, the column readout line BL performs second signal data acquisition on the potential information of the first floating diffusion FD1 with the first additional transistor 220 in the on state.
The reset transistor 230 is in an off state from the start time of the main readout timing step to the end time of the second signal data acquisition.
In the second charge, the reset transistor 230 is in an off state, the transfer transistor 210 is in an on state, and the first additional transistor 220 is in an on state.
In the second signal data acquisition, the transfer transistor 210 is in an off state, the first additional transistor 220 is in an on state, and the reset transistor 230 is in an off state.
The main readout timing step further comprises: after the second signal data acquisition is performed, a main reset operation is performed in which the reset transistor 230 and the first additional transistor 220 are in a turned-on state and the transfer transistor 210 is in a turned-off state; after the main reset operation is performed, the column readout line BL performs second reference data acquisition on potential information of the first floating diffusion FD1 with the reset transistor 230 and the transfer transistor 210 in an off state and the first additional transistor 220 in an on state.
And acquiring second effective signal data according to the difference between the data acquired by the second reference data and the data acquired by the second signal data.
In this embodiment, the method further includes: performing an extended clear step after performing the main readout timing step and before performing the extended exposure timing step; in the extended clearing step, the reset transistor 230, the first additional transistor 220, and the transfer transistor 210 are in a conducting state, the second additional transistor 250 is in an off state, and the selection transistor 270 is in an off state. The expansion clearing step clears the charge in the photodiode 200.
In the extended exposure timing step, the reset transistor 230, the transfer transistor 210, and the selection transistor 270 are all in an off state.
The extended exposure timing step includes: the second additional transistor 250 and the first additional transistor 220 perform several alternate discharging steps to transfer the charges stored in the first floating diffusion FD1 to the power line L _ VDD. Specifically, when the photodiode 200 is overexposed, the discharging step transfers the charge overflowing from the photodiode 200 to the first floating diffusion FD1 to the power supply line L _ VDD.
In each release step, the second additional transistor 250 is in a conducting state and the first additional transistor 220 is in a disconnected state.
In the extended exposure timing step, when the first additional transistor 220 is in the on state and the second additional transistor 250 is in the off state, electrons flowing from the photodiode 200 to the first floating diffusion point FD1 and the second floating diffusion point FD2 are effectively collected.
The start time of each release step corresponds to the turn-on time of the second additional transistor 250, and the end time of each release step corresponds to the turn-off time of the second additional transistor 250.
It should be noted that before the release step is performed, the first additional transistor 220 needs to be turned off to prevent the charge remaining in the capacitor 240 from being cleared; after the release step is performed, the first additional transistor 220 can only be turned on, avoiding that the charge remaining in the capacitor 240 is emptied.
After the extended exposure timing step is performed, an extended readout timing step is performed which is continuous with the extended exposure timing step in which the first additional transistor 220 is in a turned-on state, the transfer transistor 210 and the second additional transistor 250 are in a turned-off state, and the selection transistor 270 is in a turned-on state.
The extended readout timing step includes: the column readout line BL performs third signal data acquisition on the potential information of the first floating diffusion point FD 1.
In the third signal data acquisition, the reset transistor 230 is in an off state.
The extended readout timing step further comprises: after the third signal data is acquired, an extended reset operation is performed, in which the reset transistor 230 is in a conducting state; after the extended reset operation is performed, the column readout line BL performs third reference data acquisition on the potential information of the first floating diffusion FD1 with the reset transistor 230 in the off state.
The reset transistor 230 is in an off state at the start time of the extended readout timing step to the end time of the third signal data acquisition.
And acquiring third effective signal data according to the difference between the data acquired by the third reference data and the data acquired by the third signal data.
In this embodiment, the total time T1 of the main exposure timing step is equal to the total time T2 of the extended exposure timing step. In other embodiments, the total time of the extended exposure timing step is less than the total time of the main exposure timing step.
The time between adjacent release steps is a sub-effective exposure time. The sum of the sub effective exposure times is the extended effective exposure time Te.
In the embodiment, since the second additional transistor 250 and the first additional transistor 220 perform a plurality of release steps at intervals in the extended exposure timing step to transfer the charges stored in the first floating diffusion FD1 to the power line L _ VDD, in the case of overexposure of the photodiode 200, the release step transfers the charges overflowing from the photodiode 200 to the first floating diffusion FD1 to the power line L _ VDD, so that the extended effective exposure time Te is less than the total time T1 of the main exposure timing step, and the image brightness that can be represented by the data acquired by the third signal data is greater than the image brightness that can be represented by the data acquired by the second signal data, which improves the dynamic range.
In this embodiment, the image brightness that can be represented by the data acquired by the second signal data is greater than the image brightness that can be represented by the data acquired by the first signal data.
And fusing the third effective signal data, the second effective signal data and the first effective signal data to obtain a complete image of one frame.
In this embodiment, the multiplying power of the first valid data and the second valid data is equal to (C1+ C)FD1)/CFD1. When merging the first valid data and the second valid data, the second valid data needs to be multiplied by (C1+ C)FD1)/CFD1And fusing the obtained data with the first effective data. Where C1 is the capacitance of capacitor 240, CFD1Is the parasitic capacitance value of the first floating diffusion point FD 1.
In this embodiment, the magnification of the second valid data and the third valid data is equal to T1/Te. When the second valid data is merged with the third valid data, data obtained by multiplying the third valid data by T1/Te needs to be merged with the second valid data.
In this embodiment, the step of expanding the exposure time sequence includes a plurality of sub-effective exposure processes, and each sub-effective exposure process is separately subjected to exposure sampling at different time periods, so as to avoid a stroboscopic phenomenon.
The embodiment of the invention further provides another timing diagram of the pixel circuit of the image sensor during operation, please refer to fig. 5.
Referring to fig. 5, V (RSEL1) is a timing signal of the gate of the selection transistor 270, and when V (RSEL1) is high level, the selection transistor 270 is in an on state, and when V (RSEL1) is low level, the selection transistor 270 is in an off state.
Referring to fig. 5, V (RST1) is a timing signal of the gate of the reset transistor 230, and the reset transistor 230 is in an on state when V (RST1) is high, and the reset transistor 230 is in an off state when V (RST1) is low.
Referring to fig. 5, V (TG1) is a timing signal of the gate of the transfer transistor 210, and when V (TG1) is high, the transfer transistor 210 is in an on state, and when V (TG1) is low, the transfer transistor 210 is in an off state.
Referring to fig. 5, V (SS11) is a timing signal of the gate of the first additional transistor 220, and the first additional transistor 220 is in a turn-on state when V (SS11) is high level and the first additional transistor 220 is in a turn-off state when V (SS11) is low level.
Referring to fig. 5, V (SS22) is a timing signal of the gate of the second additional transistor 250, and the second additional transistor 250 is in a turn-on state when V (SS22) is high level and the second additional transistor 250 is in a turn-off state when V (SS22) is low level.
The timing diagram in fig. 5 differs from the timing diagram in fig. 4 in that: after the extended exposure time sequence step and the extended readout time sequence step are carried out, a main exposure time sequence step and a main readout time sequence step are carried out; the main exposure timing step and the extended readout timing step are consecutive.
The timing of the main exposure timing step in fig. 5 coincides with the timing of the main exposure timing step in fig. 4, the timing of the main readout timing step in fig. 5 coincides with the timing of the main readout timing step in fig. 4, the timing of the extended exposure timing step in fig. 5 coincides with the timing of the extended exposure timing step in fig. 4, and the timing of the extended readout timing step in fig. 5 coincides with the timing of the extended readout timing step in fig. 4, and will not be described in detail.
In this embodiment, referring to fig. 5, the method further includes: before the extended exposure time sequence step, an extended clearing step is carried out; in the extended clearing step, the reset transistor 230, the first additional transistor 220, and the transfer transistor 210 are in a conducting state, the second additional transistor 250 is in an off state, and the selection transistor 270 is in an off state.
In the timing diagram in fig. 5, after the extended exposure timing step and the extended readout timing step are performed, the main exposure timing step and the main readout timing step are performed, and the main exposure timing step and the extended readout timing step are consecutive, so that the actual exposure time corresponding to the data acquired by the first signal data is increased at the same frame rate, and the loss of detail in a dark place in the image is reduced.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. An image sensor pixel circuit for performing a main exposure timing step and an extended exposure timing step, comprising:
a photodiode;
the source electrode of the transmission transistor is connected with the photodiode, and the drain electrode of the transmission transistor is connected with the first floating diffusion point;
a first additional transistor, wherein the source of the first additional transistor is connected with a first floating diffusion point, and the drain of the first additional transistor is connected with a second floating diffusion point;
the drain electrode of the reset transistor is connected with a power line, and the source electrode of the reset transistor is connected with a second floating diffusion point;
the first end of the capacitor is connected with the second floating diffusion point, and the second end of the capacitor is grounded;
the drain electrode of the second additional transistor is connected with a power line, the source electrode of the second additional transistor is connected with the first floating diffusion point, and the second additional transistor and the first additional transistor are suitable for executing a plurality of alternate releasing steps in the extended exposure time sequence step so that the charges stored in the first floating diffusion point are transmitted to the power line;
a column readout line adapted to read out potential information of the first floating diffusion.
2. The image sensor pixel circuit of claim 1, wherein the second additional transistor is adapted to be in an on state during the releasing step and the first additional transistor is adapted to be in an off state during the releasing step.
3. The image sensor pixel circuit of claim 1, further comprising: the grid electrode of the source following transistor is connected with the first floating diffusion point, and the drain electrode of the source following transistor is connected with a power line; a select transistor having a drain connected to the source of the source follower transistor and a source connected to the column readout line.
4. The image sensor pixel circuit of claim 1, wherein the capacitor has first and second opposing terminals, the first terminal connected to the second floating diffusion and the second terminal connected to ground.
5. The image sensor pixel circuit of claim 1, wherein the photodiode has a forward connection terminal connected to the source of the pass transistor and a reverse connection terminal connected to ground.
6. A method of operating an image sensor pixel circuit, comprising:
providing an image sensor pixel circuit as claimed in any one of claims 1 to 5;
performing a main exposure timing sequence step, wherein in the main exposure timing sequence step, the reset transistor, the transmission transistor and the second additional transistor are all in an off state, and the first additional transistor is in an on state;
performing a main readout timing step that is continuous with the main exposure timing step after the main exposure timing step is performed, the second additional transistor being in an off state in the main readout timing step, the main readout timing step including: when the first additional transistor is in an off state, the transmission transistor is turned on, so that the charge in the photodiode carries out first charging on the first floating diffusion point; after the first charging is carried out, under the condition that the first additional transistor is in a disconnected state, the column read-out line carries out first signal data acquisition on the potential information of the first floating diffusion point; after first signal data are collected, the transmission transistor is conducted under the condition that the first additional transistor is in a conducting state, and charges in the photodiode carry out second charging on the first floating diffusion point and the second floating diffusion point; after the second charging, under the condition that the first additional transistor is in a conducting state, the column read-out line carries out second signal data acquisition on the potential information of the first floating diffusion point;
performing an extended exposure timing step in which both the reset transistor and the transfer transistor are in an off state, the extended exposure timing step comprising: the second additional transistor and the first additional transistor perform a plurality of alternate release steps to enable the charges stored in the first floating diffusion point to be transmitted to a power line;
performing an extended readout sequence step subsequent to the extended exposure sequence step, in which the first additional transistor is in an on state and the transfer transistor and the second additional transistor are in an off state, the extended readout sequence step comprising: and the column readout line is used for carrying out third signal data acquisition on the potential information of the first floating diffusion point.
7. The method of claim 6, wherein in each of the releasing steps, the second additional transistor is in an on state and the first additional transistor is in an off state.
8. The method of claim 6, wherein in the extended exposure timing step, the second additional transistor is in an off state when the first additional transistor is in an on state.
9. The method of claim 6, wherein the reset transistor is in an off state from a start time of the main readout timing step to an end time of the second signal data acquisition.
10. The method of claim 6, wherein said main readout timing step further comprises: before first charging, under the condition that the first additional transistor, the reset transistor and the transmission transistor are in an off state, the column read-out line carries out first reference data acquisition on potential information of a first floating diffusion point; and acquiring first effective signal data according to the difference between the data acquired by the first reference data and the data acquired by the first signal data.
11. The method of claim 6, wherein said main readout timing step further comprises: after the second signal data is acquired, performing main reset operation, wherein in the main reset operation, the reset transistor and the first additional transistor are in a conducting state, and the transmission transistor is in a disconnecting state; after the main reset operation is carried out, when the reset transistor and the transmission transistor are in a disconnected state and the first additional transistor is in a conducting state, the column read-out line carries out second reference data acquisition on the potential information of the first floating diffusion point; and acquiring second effective signal data according to the difference between the data acquired by the second reference data and the data acquired by the second signal data.
12. The method of claim 6, wherein said step of extending a readout timing further comprises: after the third signal data is acquired, performing extended reset operation, wherein in the extended reset operation, the reset transistor is in a conducting state; after the expansion reset operation is carried out, the column readout line carries out third reference data acquisition on the potential information of the first floating diffusion point when the reset transistor is in a disconnected state; and acquiring third effective signal data according to the difference between the data acquired by the third reference data and the data acquired by the third signal data.
13. The method of claim 6, wherein the extended exposure timing step and the extended readout timing step are performed after the main exposure timing step and the main readout timing step are performed.
14. The method of claim 13, further comprising: performing an extended clear step after performing the main readout timing step and before performing the extended exposure timing step; in the extended clearing step, the reset transistor, the first additional transistor, and the transfer transistor are in an on state, the second additional transistor is in an off state, and the selection transistor is in an off state.
15. The method of claim 13, further comprising: before the main exposure sequence step, a main emptying step is carried out; in the main clearing step, the reset transistor, the first additional transistor and the transfer transistor are in a conducting state, the second additional transistor is in an off state, and the selection transistor is in an off state.
16. The method of claim 6, wherein the main exposure timing step and the main readout timing step are performed after the extended exposure timing step and the extended readout timing step are performed; the main exposure timing step and the extended readout timing step are consecutive.
17. The method of claim 16, further comprising: before the extended exposure time sequence step, an extended clearing step is carried out; in the extended clearing step, the reset transistor, the first additional transistor, and the transfer transistor are in an on state, the second additional transistor is in an off state, and the selection transistor is in an off state.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11457163B1 (en) * | 2021-07-16 | 2022-09-27 | Pixart Imaging Inc. | Image sensor device capable of improving signal discrimination in dark condition and avoiding signal saturation in bright condition |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110418088B (en) * | 2019-08-14 | 2021-11-16 | Oppo广东移动通信有限公司 | Pixel structure, image sensor and terminal |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104427266A (en) * | 2013-09-03 | 2015-03-18 | 英属开曼群岛商恒景科技股份有限公司 | Pixel sensing unit |
| CN105681690A (en) * | 2016-03-10 | 2016-06-15 | 长春长光辰芯光电技术有限公司 | Global shutter control method for double-transfer-gate high dynamic range image sensor pixel |
| CN106664379A (en) * | 2014-07-08 | 2017-05-10 | 软动力学传感器公司 | A high dynamic range pixel and a method for operating it |
| CN108259790A (en) * | 2018-04-02 | 2018-07-06 | 昆山锐芯微电子有限公司 | Image sensor pixel circuit and its method of work |
| CN108419032A (en) * | 2018-03-01 | 2018-08-17 | 上海晔芯电子科技有限公司 | Support the HDR image sensor pixel structure and imaging system of a variety of exposure modes |
| US10103193B1 (en) * | 2017-08-03 | 2018-10-16 | Omnivision Technologies, Inc. | Apparatus and method for low dark current floating diffusion |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3042912A1 (en) * | 2015-10-26 | 2017-04-28 | Stmicroelectronics (Grenoble 2) Sas | IMAGE SENSOR WITH A HIGH DYNAMIC RANGE |
-
2018
- 2018-10-31 CN CN201811286238.XA patent/CN109194890B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104427266A (en) * | 2013-09-03 | 2015-03-18 | 英属开曼群岛商恒景科技股份有限公司 | Pixel sensing unit |
| CN106664379A (en) * | 2014-07-08 | 2017-05-10 | 软动力学传感器公司 | A high dynamic range pixel and a method for operating it |
| CN105681690A (en) * | 2016-03-10 | 2016-06-15 | 长春长光辰芯光电技术有限公司 | Global shutter control method for double-transfer-gate high dynamic range image sensor pixel |
| US10103193B1 (en) * | 2017-08-03 | 2018-10-16 | Omnivision Technologies, Inc. | Apparatus and method for low dark current floating diffusion |
| CN108419032A (en) * | 2018-03-01 | 2018-08-17 | 上海晔芯电子科技有限公司 | Support the HDR image sensor pixel structure and imaging system of a variety of exposure modes |
| CN108259790A (en) * | 2018-04-02 | 2018-07-06 | 昆山锐芯微电子有限公司 | Image sensor pixel circuit and its method of work |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11457163B1 (en) * | 2021-07-16 | 2022-09-27 | Pixart Imaging Inc. | Image sensor device capable of improving signal discrimination in dark condition and avoiding signal saturation in bright condition |
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