CN109192235A - The reference current control circuit of memory - Google Patents
The reference current control circuit of memory Download PDFInfo
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- CN109192235A CN109192235A CN201811211698.6A CN201811211698A CN109192235A CN 109192235 A CN109192235 A CN 109192235A CN 201811211698 A CN201811211698 A CN 201811211698A CN 109192235 A CN109192235 A CN 109192235A
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- Prior art keywords
- control
- voltage
- grid voltage
- grid
- memory
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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Abstract
A kind of reference current control circuit of memory, comprising: main array, including at least one storage unit are applied with the first control-grid voltage on the control gate of at least one storage unit；Referential array, including at least one reference memory unit are applied with the second control-grid voltage on the control gate of at least one reference memory unit；Further include: control-grid voltage generative circuit is suitable for adjusting second control-grid voltage and is lower than the first control-grid voltage, and adjusts the read current window of the memory.The control-grid voltage generative circuit is by exporting different control-grid voltages to the storage unit and the reference memory unit, the reference current of at least one reference memory unit output can be reduced, to realize biggish read current window, the reading accuracy of the memory is improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, more particularly to a kind of reference current control circuit of memory.
Background technique
Memory is not only the important component in integrated circuit, even more in application system of the building based on microprocessor
Indispensable a part.In recent years, various memories are embedded in microprocessor internal to improve the collection of microprocessor by people
Cheng Du and working efficiency, and memory array and its performance of peripheral circuit largely determine the work of whole system
Efficiency.
In memory, multiple storage units are arranged in array structure according to linescan method to form memory array.
When the bit data stored in reading storage unit, reading electric current where first obtaining the storage unit on bit line and right
The reference current answered, and then the reading electric current is compared with the reference current, institute is finally determined according to comparison result
Stating the data stored in storage unit is " 0 " or " 1 ".
But in some cases, the reading electric current of storage unit and reference current gap are too small, the reading to memory
Precision affects.
Summary of the invention
The embodiment of the present invention provides a kind of reference current control circuit of memory, comprising: main array, including at least one
Storage unit is applied with the first control-grid voltage on the control gate of at least one storage unit；Referential array, including at least
One reference memory unit is applied with the second control-grid voltage on the control gate of at least one reference memory unit；Also wrap
Include: control-grid voltage generative circuit is suitable for adjusting second control-grid voltage and is lower than the first control-grid voltage, and described in adjusting
The read current window of memory.
Optionally, the control-grid voltage generative circuit include: the first control-grid voltage generate branch, be suitable for it is described extremely
A few storage unit provides first control-grid voltage；And second control-grid voltage generate branch, be suitable for it is described extremely
A few reference memory unit provides second control-grid voltage.
Optionally, it includes: the first charge pump that first control-grid voltage, which generates branch, and input terminal receives power supply electricity
Pressure；And first voltage multiplie, suitable for generating first control-grid voltage according to the output voltage of first charge pump.
Optionally, it includes: the second charge pump that second control-grid voltage, which generates branch, and input terminal receives power supply electricity
Pressure；And second voltage multiplie, suitable for generating medium voltage according to the output voltage of second charge pump；And circuit is adjusted,
Suitable for generating second control-grid voltage according to the medium voltage.
Optionally, the driving capability of first voltage multiplie is greater than second voltage multiplie.
Optionally, the adjusting circuit includes: Low threshold pipe, and drain electrode the second control-grid voltage of output, source electrode receives institute
The first control-grid voltage is stated, grid receives the medium voltage；And bias current sources, it is suitable for providing to the Low threshold pipe inclined
Set electric current.
Optionally, the threshold range of the Low threshold pipe is -1V to 1V, and threshold value is reduced with the raising of operating temperature.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantage that
The embodiment of the present invention increases control-grid voltage generative circuit in existing memory, is suitable for adjusting described second
Control-grid voltage is lower than the first control-grid voltage, and adjusts the read current window of the memory.The control-grid voltage generates
Circuit by exporting different control-grid voltages to the storage unit and the reference memory unit, can reduce it is described at least
The reference current of one reference memory unit output, and realize biggish read current window, to reduce because of the reading electricity
The read error that the difference of stream and reference current is too small and generates, further improves the reading accuracy of the memory.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of memory array in the prior art；
Fig. 2 is a kind of schematic diagram for reading electric current, reference current and varying with temperature in the prior art；
Fig. 3 is a kind of structural schematic diagram of the reference current control circuit of memory provided in an embodiment of the present invention；And
Fig. 4 is a kind of schematic diagram for reading electric current, reference current and varying with temperature provided in an embodiment of the present invention.
Specific embodiment
It is a kind of structural schematic diagram of memory array in the prior art with reference to Fig. 1, Fig. 1.
The memory array includes main array 11 and referential array 12, and the main array 11 is common to storing data, institute
Referential array 12 is stated for providing reference current.
The main array 11 includes multiple storage units being arranged in array；It is in array that the referential array 12, which includes multiple,
The reference memory unit of arrangement.One storage unit includes two storage positions, stores the data of 1 bit respectively.With depositing for a line
Storage unit shares same wordline and control grid line, the storage unit of same row share same bit line.As shown in Figure 1, the main battle array
The storage unit common word line WL0 of the first row in column 11, storage position share control grid line CG00, control grid line CG1, master respectively
Each array storage unit respectively corresponds bit line BL0-BLN in array 11；The reference memory unit of the first row in the referential array 12
Common word line RWL0, storage position share control grid line CG0, control grid line CG1 respectively, respectively arrange in referential array 12 with reference to storage
Unit respectively corresponds bit line BL0-BLN.
Currently, usually first choosing one in referential array 12 when obtaining the reference current for executing read operation
Or multiple reference memory units, using the average value of the bit line current of one or more of reference memory units as with reference to electricity
Stream.
When data in reading the memory in a certain storage unit, the memory obtains the reading of the storage unit
Obtaining current, that is, the bit line current of place bit line and corresponding reference current, and the reading electric current and the reference is electric
Stream is compared, so that it is determined that the bit data that the storage unit is stored.If the reading electric current is greater than the reference current,
The bit data then stored in the storage unit is 1；If the reading electric current is less than the reference current, in the storage unit
The bit data of storage is 0.
It is the schematic diagram that reading electric current, reference current vary with temperature in the prior art with reference to Fig. 2, Fig. 2.Horizontal axis indicates work
Make temperature, the longitudinal axis indicates to read electric current and reference current Ir1Current value.
In the prior art, the reading electric current includes normal bits (Normal Bit) electric current IC1With tail bit (Tail
Bit) electric current IT1, in general, the reading electric current of most of storage unit is the normal bits electric current I in main arrayC1, and
The reading electric current for being partially in the storage unit of marginal position is tail bit current IT.With reference to Fig. 2, the normal bits electric current IC1
In lower first temperature T11Under conditions of, the relatively described tail bit current I of current valueT1It is higher；In higher second temperature T12
Under conditions of, current value is relative to the tail bit current IT1It is lower.
When it is 1 that storage unit, which reads data, the reading electric current and the reference current Ir1Difference be read current window
Mouthful, specifically, the read current window is the normal bits electric current IC1With the tail bit current IT1Middle current value is lower
One and the reference current Ir1Difference, the variation with temperature trend of the reference current and the normal bits current capacity
Seemingly.
Therefore, (such as the first temperature T under cryogenic11), corresponding first read current window Iw11It is smaller, that is to say, that
The tail bit current IT1With the reference current Ir1Difference it is smaller, so in the reading electric current and the reference
Electric current Ir1When may generate mistake, to influence the reading accuracy of the memory.(such as second temperature under the high temperature conditions
T12), corresponding second read current window Iw12It is relatively large.
It is described with reference to electricity the embodiment of the invention provides a kind of structural schematic diagram of the reference current control circuit of memory
Flow control circuit is different by exporting respectively at least one described storage unit and at least one described reference memory unit
Control-grid voltage reduces the reference current of at least one reference memory unit output, realizes biggish read current window
Mouthful.
It is a kind of reference current control circuit of memory provided in an embodiment of the present invention with reference to Fig. 3, Fig. 3.The reference
Current control circuit may include: main array 21, including at least one storage unit, the control of at least one storage unit
The first control-grid voltage V is applied on gridCG1；Referential array 22, including at least one reference memory unit, it is described at least one
The second control-grid voltage V is applied on the control gate of reference memory unitCG2；Control-grid voltage generative circuit 23 is suitable for adjusting institute
State the second control-grid voltage VCG2Lower than the first control-grid voltage VCG1, and adjust the read current window of the memory.It is related main
More descriptions of array 21 and referential array 22 can refer to above for the associated description of main array 11 and referential array 12,
This is repeated no more.
In specific implementation, when the memory is read, at least one described storage unit is according to
First control-grid voltage VCG1Read current is generated, at least one described reference memory unit is according to second control-grid voltage
VCG2Generate reference current.Specifically, the control-grid voltage generative circuit 23 is by exporting lower second control-grid voltage
VCG2, the reference current that at least one described reference memory unit generates is reduced, to increase read current window.
In some embodiments, the control-grid voltage generative circuit 23 includes: that the first control-grid voltage generates branch
231, it is suitable for providing the first control-grid voltage V at least one described storage unitCG1；And second control-grid voltage it is raw
At branch 232, it is suitable for providing the second control-grid voltage V at least one described reference memory unitCG2。
In some embodiments, it includes: the first charge pump 2311 that first control-grid voltage, which generates branch 231, defeated
Enter end and receives supply voltage Vdd；And first voltage multiplie 2312, suitable for the output voltage V according to first charge pump 2311w1
Generate the first control-grid voltage VCG1。
In some embodiments, it includes: the second charge pump 2321 that second control-grid voltage, which generates branch 232, defeated
Enter end and receives supply voltage Vdd；And second voltage multiplie 2322, suitable for the output voltage V according to second charge pump 2321w2
Generate medium voltage Vm。
In specific implementation, the value model of first charge pump 2311 and the output voltage of second charge pump 2321
Enclosing is 2V to 6V.
In some embodiments, the driving capability of first voltage multiplie 2312 is greater than second voltage multiplie 2322, because
This, the first control-grid voltage V that first voltage multiplie 2312 exportsCG1Greater than second voltage multiplie 2322 output
Medium voltage Vm。
Second control-grid voltage generates branch 232 further include: adjusts circuit 2323, is suitable for according to the medium voltage
VmGenerate the second control-grid voltage VCG2。
In some embodiments, the adjusting circuit 2323 includes: Low threshold pipe M0, drain electrode output the second control gate electricity
Press VCG2, source electrode reception the first control-grid voltage VCG2, the grid reception medium voltage Vm；And bias current sources Ib,
Suitable for providing bias current to the Low threshold pipe M0.
The control gate coupling of at least one reference memory unit described in the drain electrode of the Low threshold pipe M0 and referential array 22
It connects, the output end of source electrode and first voltage multiplie 2312 couples, and the output end of grid and second voltage multiplie 2322 couples.
The bias current sources IbOne end and the Low threshold pipe M0 drain electrode couple, the other end ground connection.
In some embodiments, the threshold range of the Low threshold pipe M0 be -1V to 1V, threshold value with operating temperature liter
It is high and reduce.
Fig. 4 is a kind of schematic diagram for reading electric current, reference current and varying with temperature provided in an embodiment of the present invention, horizontal axis table
Show operating temperature, the longitudinal axis indicates to read electric current and reference current Ir1Current value.
In conjunction with reference Fig. 3 and Fig. 4, in the present embodiment, the reading electric current that the main array 21 generates includes normal bits
Electric current IC2With tail bit current IT2.The normal bits electric current IC2With the tail bit current IT2Current value variation tendency with
The normal bits electric current IC1With the tail bit current IT1Variation tendency it is identical.
In the present embodiment, the driving capability of second voltage multiplie 2322 is lower than first voltage multiplie 2312, therefore,
The medium voltage VmLower than the first control-grid voltage VCG1.Also, due to including the Low threshold in the adjusting circuit 2323
Pipe M0, therefore, the second control-grid voltage V of outputCG2Voltage value be VCG2=Vm-Vth, wherein VthFor the low threshold
It is worth the threshold voltage of pipe M0.Although in some cases, the threshold voltage of the Low threshold pipe M0 may be negative value (threshold range
For -1V to 1V), but due to the influence of bias current and body bias effect, the equivalent threshold voltage of the Low threshold pipe M0 is positive
Value.Therefore, the second control-grid voltage VCG2Lower than medium voltage Vm。
To sum up, second control-grid voltage generates the second control-grid voltage V that branch 232 providesCG2Lower than described
First control-grid voltage VCG1, therefore the current value of the reference current Ir2 is reduced, to increase read current window.
Further, since the threshold value of the Low threshold pipe M0 is reduced with the raising of operating temperature, according to above-mentioned formula VCG2
=Vm-Vth, in the lower situation of operating temperature, the second control-grid voltage VCG2With the first control-grid voltage VCG1's
Difference is larger, therefore, the reference current Ir2Current value decline when operating temperature is lower it is more, to realize biggish reading
Current window.
In the prior art, under cryogenic, the read current window is smaller, and under the high temperature conditions, the reading electricity
It is relatively large to flow window.That is, in the prior art, the memory more easily occurs to read wrong under cryogenic
Accidentally.Therefore, the embodiment of the present invention is significantly reduced described with reference to electricity under cryogenic by the way that the Low threshold pipe M0 is arranged
Flow Ir2Current value improve the reading accuracy of the memory to effectively increase read current window.
In some embodiments, when the memory is respectively at the first temperature T21With second temperature T22Under conditions of, it is right
The the first read current window I answeredw21With the second read current window Iw22Size it is identical, to make the memory in low temperature condition
It is lower to realize biggish read current window.
In some embodiments, the first temperature T21Value range can be -60 DEG C to -20 DEG C, in some implementations
In example, the first temperature T21It can be -40 DEG C.In some embodiments, the second temperature T22Value range can be
105 DEG C to 145 DEG C, in some embodiments, the second temperature T22It can be 125 DEG C.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (7)
1. a kind of reference current control circuit of memory, comprising:
Main array, including at least one storage unit are applied with the first control on the control gate of at least one storage unit
Gate voltage；
Referential array, including at least one reference memory unit apply on the control gate of at least one reference memory unit
There is the second control-grid voltage；
It is characterized by further comprising:
Control-grid voltage generative circuit is suitable for adjusting second control-grid voltage and is lower than the first control-grid voltage, and adjusts institute
State the read current window of memory.
2. reference current control circuit according to claim 1, which is characterized in that the control-grid voltage generative circuit packet
It includes:
First control-grid voltage generates branch, is suitable for providing first control-grid voltage at least one described storage unit；
And
Second control-grid voltage generates branch, is suitable for providing the second control gate electricity at least one described reference memory unit
Pressure.
3. reference current control circuit according to claim 2, which is characterized in that first control-grid voltage generates branch
Road includes:
First charge pump, input terminal receive supply voltage；And
First voltage multiplie, suitable for generating first control-grid voltage according to the output voltage of first charge pump.
4. reference current control circuit according to claim 3, which is characterized in that second control-grid voltage generates branch
Road includes:
Second charge pump, input terminal receive supply voltage；And
Second voltage multiplie, suitable for generating medium voltage according to the output voltage of second charge pump；And
Circuit is adjusted, is suitable for generating second control-grid voltage according to the medium voltage.
5. reference current control circuit according to claim 4, which is characterized in that the driving capability of first voltage multiplie
Greater than second voltage multiplie.
6. reference current control circuit according to claim 4, which is characterized in that the adjusting circuit includes:
Low threshold pipe, drain the second control-grid voltage of output, source electrode reception first control-grid voltage, described in grid reception
Medium voltage；And
Bias current sources are suitable for providing bias current to the Low threshold pipe.
7. reference current control circuit according to claim 6, which is characterized in that the threshold range of the Low threshold pipe
For -1V to 1V, threshold value is reduced with the raising of operating temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811211698.6A CN109192235A (en) | 2018-10-17 | 2018-10-17 | The reference current control circuit of memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811211698.6A CN109192235A (en) | 2018-10-17 | 2018-10-17 | The reference current control circuit of memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116954524A (en) * | 2023-09-20 | 2023-10-27 | 深圳市爱普特微电子有限公司 | Anti-interference FLASH data reading method and device |
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Application publication date: 20190111 |