CN109192168B

CN109192168B - Pixel charging method and electronic equipment

Info

Publication number: CN109192168B
Application number: CN201811208525.9A
Authority: CN
Inventors: 文亮; 李冠恒
Original assignee: Vivo Mobile Communication Co Ltd
Current assignee: Vivo Mobile Communication Co Ltd
Priority date: 2018-10-17
Filing date: 2018-10-17
Publication date: 2021-08-20
Anticipated expiration: 2038-10-17
Also published as: CN109192168A

Abstract

The invention provides a pixel charging method and electronic equipment, wherein the method comprises the following steps: determining the polarity of a voltage signal provided by a multi-path control circuit to a target data line in M data lines; if the polarity is the first polarity, controlling the duration of the voltage signal provided to the target data line to be equal to the first charging duration; if the polarity is the second polarity, controlling the duration of the voltage signal provided to the target data line to be equal to the second charging duration; the first charging duration is longer than a first minimum charging duration required when the sub-pixels are charged through the voltage signals with the first polarity; the second charging duration is longer than a second minimum charging duration required when the sub-pixels are charged through the voltage signals of the second polarity and is shorter than the preset charging duration; the predetermined charging duration is greater than the second minimum charging duration and less than the first minimum charging duration. The invention can ensure sufficient charging time of the sub-pixel.

Description

Pixel charging method and electronic equipment

Technical Field

The embodiment of the invention relates to the technical field of communication, in particular to a pixel charging method and electronic equipment.

Background

When the display module performs display, a driving IC (Integrated Circuit) in the display module writes a voltage signal into each sub-pixel to charge the sub-pixel, thereby controlling the sub-pixel to perform display.

However, in the prior art, there is a problem that the sub-pixel charging time is insufficient.

Disclosure of Invention

The embodiment of the invention provides a pixel charging method and electronic equipment, and aims to solve the problem of insufficient charging time of sub-pixels.

In order to solve the problems, the invention is realized as follows:

in a first aspect, an embodiment of the present invention provides a pixel charging method applied to an electronic device, where the electronic device includes a pixel charging module, where the pixel charging module includes at least one multi-channel control circuit, and the multi-channel control circuit is connected to M data lines and is configured to provide corresponding voltage signals to the M data lines in a time-sharing manner; m is integral multiple of Z, and Z is the number of sub-pixels included in one pixel;

the method comprises the following steps:

determining the polarity of a voltage signal provided by the multi-path control circuit to a target data line in the M data lines;

if the polarity is a first polarity, controlling the duration of the voltage signal provided to the target data line to be equal to a first charging duration;

if the polarity is a second polarity, controlling the duration of the voltage signal provided to the target data line to be equal to a second charging duration;

the first charging duration is longer than a first minimum charging duration required when the sub-pixels are charged through the voltage signals of the first polarity; the second charging duration is longer than a second minimum charging duration required when the sub-pixels are charged through the voltage signals of the second polarity and is shorter than a preset charging duration; the predetermined charging duration is greater than the second minimum charging duration and less than the first minimum charging duration.

In a second aspect, an embodiment of the present invention further provides an electronic device, where the electronic device includes a pixel charging module, where the pixel charging module includes at least one multi-channel control circuit, and the multi-channel control circuit is connected to M data lines and is configured to provide corresponding voltage signals to the M data lines in a time-sharing manner; m is integral multiple of Z, and Z is the number of sub-pixels included in one pixel;

further comprising:

the first determining module is used for determining the polarity of a voltage signal provided by the multi-path control circuit to a target data line in the M data lines;

the first control module is used for controlling the duration of the voltage signal provided to the target data line to be equal to a first charging duration if the polarity is a first polarity;

a second control module, configured to control a duration of providing a voltage signal to the target data line to be equal to a second charging duration if the polarity is a second polarity;

In a third aspect, an embodiment of the present invention further provides an electronic device, which includes a processor, a memory, and a computer program stored on the memory and executable on the processor, and when the computer program is executed by the processor, the steps of the pixel charging method described above are implemented.

In a fourth aspect, the embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the pixel charging method as described above.

In the embodiment of the present invention, a first charging duration of the multi-path control circuit providing the voltage signal of the first polarity to the target data line is longer than a first minimum charging duration required when the sub-pixel is charged by the voltage signal of the first polarity; the second charging duration of the voltage signal with the second polarity provided by the multi-path control circuit to the target data line is greater than the second minimum charging duration required when the sub-pixel is charged by the voltage signal with the second polarity, so that the sufficient charging time of the sub-pixel can be ensured.

In addition, the first minimum charging time is longer than the preset charging duration, which indicates that the first charging duration is longer than the preset charging duration, and the second charging duration is shorter than the preset charging duration.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.

FIG. 1a is a schematic diagram of a display module according to an embodiment of the present invention;

FIG. 1b is a second structural diagram of a display module according to an embodiment of the present invention;

fig. 2a is a third structural diagram of a display module according to an embodiment of the present invention;

FIG. 2b is a schematic diagram of a charging process according to an embodiment of the present invention;

FIG. 3a is a fourth structural diagram of a display module according to an embodiment of the present invention;

FIG. 3b is a second schematic diagram of charging according to the embodiment of the present invention;

fig. 4a is a charging structure diagram provided by the embodiment of the present invention;

FIG. 4b is a third exemplary charging diagram provided in accordance with an embodiment of the present invention;

FIG. 4c is a fourth exemplary charging diagram provided in accordance with the present invention;

FIG. 5 is a flowchart of a pixel charging method according to an embodiment of the present invention;

FIG. 6a is a fifth structural diagram of a display module according to an embodiment of the present invention;

FIG. 6b is a fifth exemplary charging diagram according to the present invention;

FIG. 7a is a sixth schematic diagram of a display module according to an embodiment of the present invention;

FIG. 7b is a sixth schematic view of a charging circuit according to an embodiment of the present invention;

FIG. 8 is a seventh structural diagram of a display module according to an embodiment of the present invention;

FIG. 9 is a block diagram of an electronic device according to an embodiment of the present invention;

fig. 10 is a second block diagram of an electronic device according to an embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," and the like in this application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. Further, as used herein, "and/or" means at least one of the connected objects, e.g., a and/or B and/or C, means 7 cases including a alone, B alone, C alone, and both a and B present, B and C present, both a and C present, and A, B and C present.

For convenience of description, some contents related to the embodiments of the present invention are explained below:

at present, a liquid crystal display module mainly includes a liquid crystal cell composed of a Thin Film Transistor (TFT) glass substrate and color filter glass, a driver IC (Integrated Circuit), a Flexible Printed Circuit (FPC), a backlight, and the like.

The TFT Glass substrate includes two basic architectures of COG (Chip On Glass, Glass substrate Chip) and COF (Chip On Film, thin Film substrate Chip), which are specifically described as follows:

COG architecture

Fig. 1a shows a COG-based display module, i.e. the driver IC is bonded (bonded) on the TFT glass substrate.

The liquid crystal display module comprises an FPC, a drive IC and wiring between the FPC and the drive IC. The Data voltage output by the driving IC is connected to the multi-path control circuit through fan-out (Fanout) wiring, and the voltage signal is input to the Data line through the control of the multi-path control circuit. The Driver IC controls the output of the clock signal, thereby controlling the output of a Gate Driver On Array (GOA) circuit and a Gate. For example, a multiplexing control circuit may include six multiplexing control switch transistors controlled by CKH1, CKH2, CKH3, CKH4, CKH5, and CKH6, respectively.

The liquid crystal display module further comprises a pixel area, the pixel circuit principle of the pixel area is shown in fig. 1, and the pixel circuit can comprise a pixel transistor and a storage capacitor. In a specific implementation, the pixel transistor may be a TFT (thin film transistor), and the TFT may be a P-type TFT or an N-type TFT, which may be determined according to actual needs, and is not limited in this embodiment of the present invention.

For example, when the high voltage signal of 10V output from the gate of the first row turns on the pixel transistors (or gate pixel transistors) included in the sub-pixels of the entire row connected to the gate of the row, each of the multiplexing control switch transistors included in the multiplexing control circuit is turned on in a time-sharing manner to transmit the corresponding voltage signal to the corresponding column data line.

For example, the voltage signal output terminal S1 of the driving IC outputs a 5V voltage signal, and the multiplexing control circuit turns on the connection between the voltage signal output terminal S1 of the driving IC and the first column Data line Data1, so that the 5V voltage signal output from the voltage signal output terminal S1 of the driving IC is input to the first column Data line Data 1. Since the pixel transistors of the sub-pixels of the whole row connected with the gate of the first row are in a conducting state, the 5V voltage on the Data line Data1 of the first column is charged into the storage capacitor of the sub-pixels of the first column of the fourth row, so as to charge the sub-pixels of the first column of the fourth row, and control the sub-pixels of the first column of the fourth row to display.

The display module of FHD (Full High Definition) with the length-width ratio of 19:9 and a resolution screen comprises 2280 rows of grid electrodes and 1080 multiplied by 3 rows of data lines.

COF architecture

FIG. 1b shows a COF display module, i.e. the driver IC is bonded to the FPC.

The Fanout wire is connected with the FPC Pin (Pin Pin) and the multi-path control circuit. The control signal of the host is input to the drive IC through the FPC, and the output signal of the drive IC is output to the Fanout wiring through the FPC wiring. And voltage signals are input to the data lines under the control of the multi-path control circuit through Fanout wiring, and then are charged into the storage capacitors of the sub-pixels under the control of the corresponding row gates. The power supply voltage and the control clock signal output by the driving IC are input to a Gate On Array (GOA) circuit to control the Gate On/off of the Gate.

The design of the multi-path control circuit comprises a 1:3 multi-path control circuit and a 1:6 multi-path control circuit, and is specifically explained as follows:

1:3 multi-path control circuit

At present, the common design of the multi-path control circuit of the liquid crystal display module is 1: the design of 3 is that usually, a voltage signal output end (also called as a voltage signal output pin) of the driving IC is connected with 3 multi-way control switch transistors, the 3 multi-way control switch transistors are respectively connected with data lines of RGB three-column sub-pixels, and a voltage signal output by a voltage signal output end of the driving IC is sequentially charged into storage capacitors of the sub-pixels in different columns under the control of the multi-way control circuit. The switching transistor may be a TFT (thin film transistor) or a MOS transistor (metal-oxide-field effect transistor).

Fig. 2a shows a1 to 3 multi-channel control circuit, and fig. 2a only shows 2 voltage signal output terminals of the driving IC: a first voltage signal output end Source1 and a second voltage signal output end Source 2. It should be understood that the present invention is not limited to the number of voltage signal outputs of the driving IC accordingly.

In practical operation, the driver IC in the FHD + resolution display panel may have 1080 voltage signal outputs. Wherein, Source1 is connected to three columns of sub-pixels of RBG through 3 switch transistors respectively, and Source2 is also connected to three columns of sub-pixels of RBG through 3 switch transistors (the other 1078 of FHD + are all connected in this way). Specifically, three columns of RBG sub-pixels are sequentially a red sub-pixel column, a green sub-pixel column and a blue sub-pixel column.

When the gate of the first row is turned on, and simultaneously the red voltage signal control signal CKHR output by the driving IC turns on the multi-way control switch transistor connected to the red sub-pixel, the voltage signal (for example, the +5V voltage in the figure) output by Source1 is charged into the storage capacitor in the first row and the first column of the red sub-pixel; the voltage signal (e.g., -3V in the figure) output by Source2 is charged into the storage capacitor in the red sub-pixel in the fourth column of the first row. Then after CKHR turns off the corresponding multiplexing control switch transistor, the driving IC outputs a green voltage signal control signal CKHG, turns on the multiplexing control switch transistor connected to the green sub-pixel, and charges the voltage signal (e.g., -2V in the figure) output by Source1 to the storage capacitor of the green sub-pixel in the first row and column 2, and charges the voltage signal (e.g., +1V in the figure) output by Source2 to the storage capacitor of the green sub-pixel in the first row and column 5. Then after CKHG turns off the corresponding multiplexing control switch transistor, the driving IC outputs a blue voltage signal control signal CKHB, turns on the multiplexing control transistor connected to the blue sub-pixel, the voltage signal (for example, the +4V voltage in the figure) output by Source1 is charged into the storage capacitor of the blue sub-pixel in the first row and column 3, and the voltage signal (for example, the-5V voltage in the figure) output by Source2 is charged into the storage capacitor of the blue sub-pixel in the first row and column 6.

At this point, the charging of the sub-pixels in the first row is completed, and the gate of the first row is turned off by the GOA circuit under the control of the driving IC. And then, opening the grid of the second row, and sequentially charging the sub-pixels of the second row by controlling the multi-path control circuit. Finally, the charging of the sub-pixels on the whole display Panel (Panel) is completed, that is, the display of one frame of picture is completed.

The red voltage signal control signal CKHR is used for controlling the multi-channel control switch transistor connected with the red sub-pixel to be turned on, so that the voltage signal output by the driving IC can be charged into the red sub-pixel; correspondingly, the green voltage signal control signal CKHG is used for controlling the multi-channel control switch transistor connected with the green sub-pixel to be turned on, so that the voltage signal output by the driving IC can be charged into the green sub-pixel; the blue voltage signal control signal CKHB is used to control the multi-way control switch transistor connected to the blue sub-pixel to be turned on, so that the voltage signal output from the driving IC can be charged into the blue sub-pixel.

In fig. 2a, the adjacent columns are opposite in potential, such as the first column is all positive, the second column is all negative, and the third column is all positive, which is the currently common column inversion driving.

In the existing 1:3 multi-path control circuit design, during the on time of a row of gates, the voltage signals output by the driving IC respectively charge the red sub-pixel, the green sub-pixel and the blue sub-pixel. Therefore, the gate on time of one row is divided into 3, and one for each of the red, green, and blue sub-pixels.

Illustrated is a Panel size 19:9FHD + screen, refresh rate of 60 frames/second. As shown in fig. 2b, the reference pixel is charged in a positive frame, the multiple rows of gates included in the display panel are sequentially turned on, the time allocated to turn on each row of gates in one frame of display time is about 6 μ s (microseconds), meanwhile, the voltage signal output end of the driving IC outputs 5V voltage signals with the pulse width of 2 μ s, considering that the signals cannot be superposed and a time margin is left, the driving IC outputs control signals of 1.6 μ s square wave multi-channel control to turn on the switching transistor, so that the 5V voltage output by the voltage signal output end of the driving IC is charged into the storage capacitor of the sub-pixel through Fanout wiring, the multi-channel control switching transistor, the data line and the pixel transistor, and after a certain time, the voltage at two ends of the storage capacitor of the sub-pixel reaches a certain voltage value, such as 4.98V in fig. 3, and the liquid crystal is driven to rotate and display. For pixel negative frame charging, the difference between the pixel negative frame charging and the pixel positive frame charging is mainly that the voltage signal output terminal of the driving IC outputs a voltage signal with negative polarity, and the charging principle is the same as that of the pixel positive frame charging, and is not described herein again.

Taking a display module including 2280 rows of gates and 1080 × 3 columns of data lines as an example, 1080 voltage signal output terminals are required for designing a 1:3 multi-way control circuit, and 1080 Fanout lines are required for connection. For the COG scheme, the Fanout area takes up a large space due to the number of traces. For the COF scheme, 1080 output lines of the driving IC on the FPC occupy large space, the FPC is wide, the required TFT glass space is also wide, and simultaneously Fanout wiring for connection occupies large space.

With the development of the full-screen, the requirement of the proportion of the pixel area in the whole screen area is higher and higher. Under the condition of a certain screen area, other functional modules are required to occupy smaller and smaller space. Thus, 1 to 6Demux circuit design is a future trend.

1:6D multi-path control circuit

As shown in fig. 3a, a 1:6 multi-way control circuit is shown, that is, usually, one voltage signal output terminal of the driver IC is connected with 6 multi-way control switch transistors, so that compared with a 1:3D multi-way control circuit, both Source output lines and Fanout traces of the driver IC can be reduced by half on the basis of 1:3, and the trace occupation space is greatly reduced.

As shown in FIG. 3b, the same example is illustrated for a Panel size of 19:9FHD + screen, with a refresh rate of 60 frames/second. The time allocated to one row of gates to be turned on is about 6 μm during one frame of display time. The 1:6 multi-path control circuit design reduces the charging time allocated to each sub-pixel to 1 mu s (one Gate opening time is divided into 6 parts), and after considering that the voltage signals and the multi-path control signals cannot be overlapped and do not interfere with each other, and the remained time margin is optimized, the driving IC can output the square wave multi-path control signals with the duration of 0.8 mu s (approaching the limit of the maximum output time).

As shown in fig. 4a, in the case where the pixel transistor is NTFT, positive and negative charge simulation is performed on the charge principle map.

As shown in fig. 4b, the gate turns on the pixel transistor (the simulation signal diagram is omitted), the voltage signal output terminal outputs +6V, the pixel electrode voltage is charged from 0V to 6V, and the positive charging takes at least 0.8 μ s with the rising edge of 5% to 95% of the target + 6V. Considering some losses of the data lines, Fanout traces, etc., and some margin for the charging time, the charging time for positive charges needs to be greater than 0.8 mus.

As shown in FIG. 4c, the pixel is charged-6V starting from 0V, with a falling edge of 5% to 95% of the target-6V voltage, and 0.1 μ s is consumed for negative charging.

It can be seen that when the pixel transistor is NTFT, the voltage controlling the pixel transistor to turn on is positive, and the time taken to charge the pixel capacitor positively is much longer than that for charging it negatively. The positive charging time needs to be more than 0.8 mu s and more than the duration of the voltage signal provided by the driving IC in the 1:6 multi-path control circuit to one data line, so that the problem of insufficient pixel charging time exists for the 1:6 multi-path control circuit, and the display effect of the display module is poor.

In the embodiment of the invention, the charging time of the first polarity voltage with sufficient charging time can be saved by utilizing a method of non-uniform positive and negative charging time, and the charging of the second polarity voltage with insufficient charging time is used, so that the sufficient pixel charging time can be ensured.

The pixel charging method provided by the embodiment of the invention can be applied to electronic equipment comprising a display module. In particular, the electronic Device may be a Mobile phone, a Tablet Personal Computer (Tablet Personal Computer), a Laptop Computer (Laptop Computer), a Personal Digital Assistant (PDA), a Mobile Internet Device (MID), a Wearable Device (Wearable Device), or a vehicle-mounted Device.

The display module of the electronic device may include a display substrate, and a plurality of rows of gate electrodes, a plurality of columns of data lines, a plurality of rows and a plurality of columns of sub-pixels, and a pixel charging module disposed on the display substrate, as shown in fig. 1a, fig. 1b, fig. 2a, and fig. 3 a. It should be understood that each sub-pixel is electrically connected to a row gate and a column data line, respectively, so that when a row gate is turned on and a column data line is written with a voltage signal, the voltage signal can be charged in the sub-pixel connected to the row gate and the column data line.

Further, the pixel charging module may include a driving IC, and at least one multiplexing control circuit electrically connected to the driving IC.

For each multi-path control circuit, a first end of the multi-path control circuit is connected with one voltage signal output end of the drive IC, a second end of the multi-path control circuit is connected with the M data lines, and the multi-path control circuit is used for writing data voltage-limited output by the voltage signal output end connected with the multi-path control circuit in a time-sharing mode into the M data lines connected with the multi-path control circuit, namely providing corresponding voltage signals for the M data lines in a time-sharing mode.

Wherein M is an integer multiple of Z, and Z is the number of sub-pixels included in one pixel. Specifically, M is associated with the number L of pixel columns controlled by 1 voltage signal output terminal, and the number Z of sub-pixels included in one pixel, and the relationship between M and L and Z can be expressed as: m ═ lxz. For example, as shown in fig. 2a, if 1 voltage signal output terminal controls 1 column of pixels and one pixel includes three RGB word pixels, M is 1 × 3 is 3; as shown in fig. 3a, if 1 voltage signal output terminal controls 2 columns of pixels, and one pixel includes three RGB word pixels (i.e., one pixel includes 3 red, green, and blue sub-pixels)), then M is 2 × 3 is 6. In addition, it can be understood that if 1 voltage signal output terminal controls 1 column of pixels, and one pixel includes RGBW four sub-pixels (i.e., one pixel includes 4 sub-pixels of red, green, blue and white sub-pixels), then M is 1 × 4 is 4.

Alternatively, as shown in fig. 2a and 3a, the multiplexing control circuit may include M switching transistors. For each switch transistor, the control end of the switch transistor is connected to the multi-channel control signal output by the drive IC, the first end of the switch transistor is connected with a data line, and the second end of the switch transistor is connected with the voltage signal output end Source. In specific implementation, if the control terminal of the switching transistor receives the CHK, the voltage signal output by the voltage signal output terminal Source can be written into the data line connected to the control terminal Source, and then the voltage signal is charged into the corresponding sub-pixel.

The pixel charging method according to the embodiment of the present invention is explained below.

Referring to fig. 5, fig. 5 is a flowchart of a pixel charging method according to an embodiment of the present invention. As shown in fig. 5, the pixel charging method of the present embodiment includes the following steps:

step 501, determining the polarity of the voltage signal provided by the multi-channel control circuit to the target data line in the M data lines.

It should be noted that, the electronic device determines the polarity of the voltage signal provided by the multiplexing control circuit to the target data line, and aims to control the duration of providing the voltage signal to the target data line according to the polarity of the voltage signal, thereby improving the control flexibility of the duration of providing the voltage signal.

It should be understood that the electronic device may be based on at least one of the following prior to controlling the display of the ith picture frame: the layout of the sub-pixels in the ith frame and the display module, and the pixel torsion direction of each sub-pixel in the ith-1 frame predetermine the magnitude of the voltage signal charged in each sub-pixel, i.e. the target voltage, and the polarity of the voltage signal. Since the voltage signals of the sub-pixels are transmitted through the data lines, the electronic device can determine the polarity of the voltage signal supplied from the multiplexing control circuit to the target data line after determining the polarity of the voltage signal charged in each sub-pixel.

In this step, the target data line may be any one of the M data lines.

Step 502, if the polarity is the first polarity, controlling a duration of the voltage signal provided to the target data line to be equal to a first charging duration.

The first charging duration is longer than a first minimum charging duration required when the sub-pixels are charged through the voltage signals of the first polarity. Therefore, if the polarity is the first polarity, the duration of the voltage signal supplied to the target data line is controlled to be longer than the first minimum charging duration.

The first minimum charging time period may be understood as: and when the sub-pixel is charged by the voltage signal with the first polarity, the minimum charging time required when the storage capacitor in the sub-pixel reaches the saturation voltage is prolonged. In some embodiments, the saturation voltage may be equal to the product of C and the target voltage, and C may be greater than 0.9 and less than 1.

Thus, if the polarity of the voltage signal provided by the multi-path control circuit to the target data line is the first polarity, the duration of the voltage signal provided to the target data line is controlled to be equal to the first charging duration, so that the sufficient charging time of the corresponding sub-pixel can be ensured.

Step 503, if the polarity is the second polarity, controlling a duration of the voltage signal provided to the target data line to be equal to a second charging duration.

When the second charging duration is longer than that of the sub-pixels charged by the voltage signals of the second polarity, the required second minimum charging duration is shorter than the preset charging duration; the predetermined charging duration is greater than the second minimum charging duration and less than the first minimum charging duration. Therefore, if the polarity is the second polarity, the duration of the voltage signal supplied to the target data line is controlled to be greater than the second minimum charging duration.

The second minimum charging period may be understood as: and when the sub-pixel is charged by the voltage signal with the second polarity, the minimum charging time required when the storage capacitor in the sub-pixel reaches the saturation voltage is prolonged.

Therefore, if the polarity of the voltage signal provided by the multi-path control circuit to the target data line is the second polarity, the duration of the voltage signal provided to the target data line is controlled to be equal to the second charging duration, so that the sufficient charging time of the corresponding sub-pixel can be ensured.

It is to be understood that the first and second polarities are opposite. For example, the first polarity may be a positive polarity and, correspondingly, the second polarity is a negative polarity; the first polarity may also be a negative polarity and correspondingly the second polarity is a positive polarity.

In the conventional pixel charging method, electronic equipment determines the opening time T of each row of grid electrodes in advance, and assumes that a voltage signal output end of a driving IC corresponds to M data lines, and then divides the opening time of the grid electrodes into M parts, namely, the duration of supplying voltage signals to each data line in the M data lines is equal to about T/M and is irrelevant to the expression form of the polarity of the voltage signals written into the data lines. Since the existing pixel charging method has the duration of supplying the voltage signal to the data line predetermined according to the Gate on time, in the embodiment of the present invention, the duration of supplying the voltage signal to the data line determined by the existing pixel charging method may be made the predetermined charging duration. In practical applications, the predetermined charging duration may be obtained in advance, and the invention does not limit the specific manner of obtaining.

Further, in the embodiment of the present invention, the predetermined charging duration is greater than the second minimum charging duration and less than the first minimum charging duration. Therefore, the embodiment of the invention ensures that the charging time of the sub-pixel is sufficient, and simultaneously ensures that the first charging duration is longer than the preset charging duration and the second charging duration is shorter than the preset charging duration, thereby realizing non-uniform distribution of charging time with different polarities.

It can be seen that, compared with the prior art, the pixel charging method of this embodiment can shorten the charging time for charging the sub-pixel by the voltage signal of the second polarity, and prolong the charging time for charging the sub-pixel by the voltage signal of the first polarity, thereby ensuring that the charging time of the sub-pixel is sufficient.

The specific representation of the first polarity and the second polarity can be determined according to the specific representation of the pixel transistor included in the sub-pixel in the display module.

Further, if the pixel transistor included in the sub-pixel is an N-type transistor, the first polarity is a positive polarity, and the second polarity is a negative polarity; alternatively, the first and second electrodes may be,

if the pixel transistor included in the sub-pixel is a P-type transistor, the first polarity is a negative polarity, and the second polarity is a positive polarity.

That is, when the pixel transistor is an N-type transistor, such as NTFT (N-type thin film transistor), the time for charging the pixel transistor negatively can be saved, and the pixel transistor can be charged positively; when the thin film transistor is a P-type transistor, such as a PMOS transistor (P-type field effect transistor), the time for charging positive electricity can be saved, and the time for charging negative electricity can be saved.

In the embodiment of the present invention, the first charging duration and the second charging duration may be preset, or may be obtained in advance by the electronic device, which may be determined specifically according to actual needs, and this is not limited in the embodiment of the present invention.

Optionally, before determining the polarity of the voltage signal provided by the multi-channel control circuit to the target data line of the M data lines, the method further includes:

acquiring the first minimum charging time and the second minimum charging time;

determining a first charging duration time when the voltage signal of the first polarity is used for charging the sub-pixels according to the first minimum charging duration time;

and determining a second charging duration of the voltage signal of the second polarity when the sub-pixel is charged according to the second minimum charging duration.

In the present embodiment, it is understood that the first charging duration is longer than the first minimum charging duration, and the second charging duration is longer than the second minimum duration.

In a specific implementation, after obtaining the first minimum charging duration and the second minimum charging duration, the electronic device may determine the first charging duration as a first charging duration by adding a sum of a predetermined value to the first charging duration, and determine the second charging duration as a second charging duration by adding a sum of the predetermined value to the second charging duration.

The predetermined value may be preset, and when the voltage signal of the first polarity for the first charging duration determined in the above manner is supplied to the target data line, the sufficient charging time of the sub-pixel may be ensured, and when the voltage signal of the second polarity for the second charging duration determined in the above manner is supplied to the target data line, the sufficient charging time of the sub-pixel may be ensured.

In this way, sufficient charging time of the sub-pixels can be ensured.

Further, before determining the first charging duration and the second charging duration, the method further includes:

acquiring a charging reserved time length;

the determining a first charging duration when the voltage signal of the first polarity is used to charge the sub-pixel according to the first minimum charging duration includes:

determining a first charging duration time when the voltage signal of the first polarity is used for charging the sub-pixels according to the first minimum charging duration time and the charging reservation time;

determining a second charging duration for charging the sub-pixel with the voltage signal of the second polarity according to the second minimum charging duration includes:

and determining a second charging duration time when the voltage signal of the second polarity is used for charging the sub-pixels according to the second minimum charging duration time and the charging reservation time.

In this embodiment, the first charging duration may be greater than the sum of the first minimum charging duration and the charging reservation duration; the second charging duration may be greater than a sum of the second minimum charging duration and the charging reservation duration.

The charging reservation duration can be a reservation duration of the routing loss, the charging time margin and the like. Thus, when the voltage signal of the first polarity for the first charge duration determined in the above manner is supplied to the target data line, the sufficient charging time of the sub-pixel can be ensured, and when the voltage signal of the second polarity for the second charge duration determined in the above manner is supplied to the target data line, the sufficient charging time of the sub-pixel can be ensured.

It should be noted that, in the embodiment of the present invention, both the first charging duration and the second charging duration are less than the switching time. The switching time may be used to monitor the charging object, and for example, assuming that the current charging object is a first sub-object, when the charging duration of the first sub-pixel reaches the switching time, the charging object is switched to a second sub-pixel, and the second sub-pixel is charged.

In the embodiment of the present invention, since both the first charging duration and the second charging duration are less than the switching time, when the charging duration of the first subpixel reaches the first charging duration or the second charging duration, it is described that the first subpixel has completed charging, and therefore, the charging object may be directly switched to the second subpixel to charge the second subpixel, and the charging object is switched without waiting until the charging duration of the first subpixel reaches the switching time, so that compared with the prior art, the charging time may be further shortened in the present invention.

In the embodiment of the present invention, the electronic device may drive the display of the display module in multiple ways, for example, for the display of the ith frame, the display may be controlled by column inversion, row inversion, pixel inversion or field inversion; for the display of the ith picture frame and the (i + 1) th picture frame, the display can be controlled by frame inversion or the like, but it should be understood that, in the process of controlling the display of the ith picture frame, the electronic device can determine the polarity of the voltage signal provided by the multi-path control circuit to the target data line, and based on the specific expression of the polarity, the duration for providing the voltage signal is determined, so that sufficient charging of the sub-pixels can be ensured.

Various embodiments are described below.

In the first embodiment, the electronic device controls display of the i-th frame by column inversion driving. I.e. the potentials of adjacent columns are of opposite polarity.

In this embodiment, optionally, the method further comprises:

under the condition that a grid electrode included in the display module is opened, the multi-path control circuit sequentially provides voltage signals of a first preset polarity for odd-numbered rows of data lines in the M data lines, and the multi-path control circuit sequentially provides voltage signals of a second preset polarity for even-numbered rows of data lines in the M data lines;

wherein the first predetermined polarity is opposite to the second predetermined polarity. The first preset polarity and the second preset polarity can be predetermined by the electronic device, and if the first preset polarity is a positive polarity, the second preset polarity is a negative polarity; if the first predetermined polarity is negative, the second predetermined polarity is positive.

In this embodiment, the polarities of the voltage signals charged to the sub-pixels in the same column are the same, and the polarities of the voltage signals charged to the sub-pixels in the adjacent columns are opposite.

In the embodiment of the present invention, the nth row Gate is turned on, that is, the nth row Gate outputs the nth row Gate driving signal, so that the thin film transistor in the sub-pixel connected to the nth row Gate is turned on, where n is a positive integer.

In a specific implementation, when the nth row gate included in the display module is turned on, the multi-path control circuit may preferentially and sequentially provide a voltage signal of a first preset polarity to the odd-numbered rows of the M data lines, and sequentially provide a voltage signal of a second preset polarity to the even-numbered rows of the M data lines after the charging of the sub-pixels connecting the odd-numbered rows of the data lines and the nth row gate is completed.

Of course, the multi-path control circuit may preferentially and sequentially provide the voltage signals of the first preset polarity to the even-numbered columns of the M data lines, and sequentially provide the voltage signals of the second preset polarity to the odd-numbered columns of the M data lines after the charging of the sub-pixels connecting the even-numbered columns of the data lines and the nth row of the gate electrodes is completed.

It should be noted that, in the process of controlling the display of the ith picture frame, the electronic device may determine the duration of supplying the voltage signal to the target data line through the polarity of the voltage signal supplied to the target data line by the multi-channel control circuit based on the specific expression of the polarity, so as to ensure that the sub-pixels are sufficiently charged.

For ease of understanding, please refer to fig. 6a and 6b together. In fig. 6a, M equals 6 and the pixel transistor in the sub-pixel is NTFT.

As shown in fig. 6a, the first voltage signal output terminal Source1 of the driving IC provides corresponding voltage signals to the first column Data line Data1, the second column Data line Data2, the third column Data line Data3, the fourth column Data line Data4, the fifth column Data line Data5, and the sixth column Data line Data6 in a time-sharing manner. The voltage signal output by the Source1 is transmitted to the above data lines through the multi-channel control circuit.

The multi-way control circuit comprises a first multi-way control switch transistor T1, a second multi-way control switch transistor T2, a third multi-way control switch transistor T3, a fourth multi-way control switch transistor T4, a fifth multi-way control switch transistor T5 and a sixth multi-way control switch transistor T6; the gate of T1 is connected to the first multi-path control signal CKH1, the gate of T2 is connected to the second multi-path control signal CKH2, the gate of T3 is connected to the first multi-path control signal CKH3, the gate of T4 is connected to the first multi-path control signal CKH4, the gate of T5 is connected to the first multi-path control signal CKH5, and the gate of T6 is connected to the first multi-path control signal CKH 6.

In fig. 6a, the gates included in the display module are sequentially referred to as a first row Gate1 and a second row Gate2 from top to bottom. It should be noted that, in the following description of the embodiments, the data lines, the gates, and the multi-way control switch transistors of the display module are the same as those in fig. 6a, and are not repeated.

For example, the first row gate is turned on for 6 μ s, the first voltage signal output terminal Source1 and the second voltage signal output terminal Source2 included in the driving IC output 5V voltage signals, CKH1 controls to turn on the corresponding multi-way control switch transistor, and the 5V voltage signal output by Source1 and the 5V voltage signal output by Source are written into the corresponding sub-pixel through Fanout (fan-out) trace, multi-way control circuit, data line and pixel transistor.

And 1 voltage signal output end drives 6 columns of sub-pixels, and 3 columns of sub-pixels are charged with positive potential and 3 columns of sub-pixels are charged with negative potential by adopting a column inversion mode. The charging time of the positive charge is longer than that of the negative charge, so that the positive potential of 3 columns can be charged first, and then the negative potential of the rest 3 columns can be charged by controlling the output of the CKH signal. The problem that charging time is wasted due to frequent switching of positive and negative potentials caused by positive and negative outputs of data lines due to sequential charging in a row and a column in the conventional method is solved.

As shown in fig. 6b, when the Gate signal is turned on, the multi-path control circuit sequentially turns on the odd-numbered columns, the voltage signal output terminal of the driving IC sequentially provides corresponding voltage signals to the data lines of the odd-numbered columns through the multi-path control circuit to sequentially charge the sub-pixels of the odd-numbered columns of the corresponding row, and then the voltage signal output terminal of the driving IC sequentially provides corresponding voltage signals to the data lines of the even-numbered columns through the multi-path control circuit to sequentially charge the sub-pixels of the even-numbered columns of the corresponding row.

For example, the Gate1 of the first row is turned on, the Source1 outputs a 5V voltage signal, the CKH1 turns on the T1, and the 5V voltage signal output by the Source1 is written into the red sub-pixel of the first row in the first column; then Source1 outputs 4V voltage signal, CKH3 is turned on, and the 4V voltage signal output by Source1 is written into the blue sub-pixel in the first row and the third column; the green sub-pixel in the fifth column of the first row is then charged in a similar manner. And after the odd-numbered columns are charged, the even-numbered columns are sequentially charged. In the process, during the opening time of the Gate1, the charging time of the negative voltage is compressed, and the positive voltage is charged in a saved way. Of course, in another embodiment, the even columns may be charged first and then the odd columns may be charged.

In fig. 6b, the charging duration for supplying the positive polarity voltage signal to the data line is 1.3us, and the charging duration for supplying the negative polarity voltage signal to the data line is 0.7us, which shows that, compared to the prior art in which the charging duration for supplying the positive polarity voltage signal and the negative polarity voltage signal to the data line is 1us, fig. 6b prolongs the charging duration for the positive polarity voltage signal by saving time from the charging duration for the negative polarity voltage signal, thereby ensuring the charging duration for the positive polarity voltage.

It should be noted that, as can be seen from the foregoing, the minimum charging time of the sub-pixel is 0.8us for positive charging, and the minimum charging time of the sub-pixel is 0.1us for negative charging, and if the reserved charging time is 0.2us, it is only necessary to control the duration of the positive charging to be greater than 1us and the duration of the negative charging to be greater than 0.3us, so as to ensure that the sub-pixel charging time is sufficient. And the duration of the positive polarity charging and the duration of the negative polarity charging are both smaller than the switching time.

Compared with the time saved from the charging duration of the negative polarity voltage signal, the charging duration of the positive polarity voltage signal is completely compensated, only part of the time saved from the charging duration of the negative polarity voltage signal is compensated, the charging duration of the positive polarity voltage signal is compensated, the charging time of the whole picture frame can be shortened while the charging duration of the sub-pixels is ensured to be sufficient, and therefore the refresh rate of the picture frame can be further improved.

In the second embodiment, the electronic device controls the display of the i-th screen frame by the line inversion driving method. I.e. the potentials of adjacent rows are of opposite polarity.

In this embodiment, optionally, the method further comprises:

in the display process of the ith picture frame, under the condition that the odd-numbered row grid electrodes included in the display module are opened, the multi-path control circuit sequentially provides voltage signals with first preset polarity for the M data lines; under the condition that even-numbered row gates included in the display module are opened, the multi-path control circuit sequentially provides voltage signals of a second preset polarity to the M data lines;

wherein the first preset polarity is opposite to the second preset polarity, and i is a positive integer. Specifically, reference may be made to the description in the first embodiment, which is not repeated herein.

In this embodiment, the polarities of the voltage signals charged by the sub-pixels connected to the same row of gates are the same, and the polarities of the voltage signals charged by the sub-pixels connected to the adjacent row of gates are opposite.

It should be noted that, in the process of controlling the display of the ith picture frame, the electronic device may determine, based on the specific expression of the polarity, the duration of supplying the voltage signal to the target data line through the polarity of the voltage signal supplied to the target data line by the multi-channel control circuit, so as to ensure that the sub-pixels are sufficiently charged.

For ease of understanding, please refer to fig. 7a and 7b together. In fig. 7a, M equals 6 and the pixel transistor in the sub-pixel is NTFT.

As shown in fig. 7a, the Gate1 of the first row is turned on, and under the control of the multi-way control signal inputted to the Gate of each multi-way control switch transistor included in the multi-way control circuit, the Source1 and the Source2 sequentially charge the positive voltage to each sub-pixel located in the first row. The second row Gate2 is then turned on and the second row of sub-pixels is sequentially charged negatively. And then the third row grid, the fourth row grid and the like are sequentially opened, and the polarities of the voltage signals switched in by the sub-pixels in the adjacent rows are reversed. Since the sub-pixels in a row are positively charged and the sub-pixels in a row are negatively charged, the time for negatively charging the rows is saved, and the sub-pixels are configured for positively charging the rows.

As shown in fig. 7b, illustrated with a Panel size of 19:9FHD + screen, a refresh rate of 60 frames/second. The time for charging each sub-pixel by the negative polarity voltage signal is reduced from about 1 mus to 0.7 mus, and the corresponding row gate on time is 4.2 mus, which can save 1.8 mus compared with the original row gate on time. The saved 1.8 mus is then allocated to the positive voltage charge so that the positive voltage row Gate on time extends to 7.8 mus, and by extending the time to charge each sub-pixel by the positive polarity voltage signal to 1.3 mus, the CKH signal can have a charge time of 1.1 mus, which is sufficient according to industry experience.

Of course, only a part of the time saved from the charging duration of the negative polarity voltage signal may be compensated for the charging duration of the positive polarity voltage signal, and the charging duration of the entire frame may be shortened while ensuring that the charging duration of the sub-pixels is sufficient, so as to further improve the refresh rate of the frame.

Further, after the display of the ith picture frame is completed, before the display of the (i + 1) th picture frame is started, the method further includes:

and controlling the grid electrode included by the display module to be opened at least once.

When the display of the ith picture frame is controlled by adopting a row inversion driving mode, after the display of the ith picture frame is controlled, all gates are opened once before the display of the (i + 1) th picture frame is started, positive and negative charges in pixel capacitors on the same column are conducted and neutralized due to opposite potentials of adjacent columns, then the charge enters the (i + 1) th picture frame for charging, and the charging speed is accelerated due to the fact that the originally charged pixel charges are neutralized to some extent when the (i + 1) th picture frame is charged with opposite charges.

For example, when the display of the ith picture frame is controlled, the storage capacitor of the jth sub-pixel is charged with a voltage of +5V, and when the display of the ith +1 picture frame is controlled, the storage capacitor of the jth sub-pixel is charged with a voltage of-5V, so that after the display of the ith picture frame is completed and before the display of the ith +1 picture frame is started, the gate included in the display module is controlled to be opened at least once, so that the charges in the storage capacitor of the ith sub-pixel are neutralized to have no charges, and then the charging of negative charges is started.

If all pixel capacitors are neutralized before the (i + 1) th picture frame is charged, the original 5V voltage is greatly reduced, and when the (i + 1) th picture frame is negatively charged, the time for neutralizing the positive electricity can be saved, so that the charging time of the (i + 1) th picture frame can be shortened.

In the third embodiment, the electronic device controls the display of the i-th picture frame and the i + 1-th picture frame by the frame inversion driving. I.e. the potentials of adjacent picture frames are of opposite polarity.

In this embodiment, optionally, the method further comprises:

in the display process of the ith picture frame, under the condition that a grid electrode included by the display module is opened, the multi-path control circuit sequentially provides voltage signals with first preset polarity to the M data lines;

in the display process of the (i + 1) th picture frame, under the condition that a grid electrode included by the display module is opened, the multi-path control circuit sequentially provides voltage signals of a second preset polarity to the M data lines;

wherein the first preset polarity is opposite to the second preset polarity, and i is a positive integer. That is, when the first preset polarity is positive, the second preset polarity is negative; when the first predetermined polarity is a negative polarity, the second predetermined polarity is a positive polarity, which can be referred to the description of the first embodiment and will not be described herein again.

In this embodiment, in the display process of the same frame, the polarities of the voltage signals charged to all the sub-pixels included in the display panel are the same; in the display process of the adjacent picture frame, the polarities of the voltage signals charged to the sub-pixels included in the display panel are opposite.

It should be noted that, in the process of controlling the display of the ith picture frame, the electronic device may determine, based on the specific expression of the polarity, the duration for supplying the voltage signal by determining the polarity of the voltage signal supplied by the multi-path control circuit to the target data line, so as to ensure that the charging of the sub-pixels is sufficient.

The implementation principle of the method is similar to that of the first embodiment and the second embodiment, and specific reference may be made to the description in the first embodiment and the second embodiment, which is not described herein again.

Therefore, the charging time of the (i + 1) th picture frame can be prolonged by shortening the charging time of the (i) th picture frame, or the charging time of the (i + 1) th picture frame can be prolonged by shortening the charging time of the (i + 1) th picture frame, the charging time of the adjacent picture frames can be flexibly adjusted, and the sufficient charging time of the sub-pixels can be ensured.

In addition, the frame inversion driving mode is adopted to control the display of the frame, so that the polarization of liquid crystal can be avoided, and the service life of the liquid crystal display module is prolonged.

In the fourth embodiment, the electronic device controls the display of the i-th screen frame by field inversion driving. I.e. the potentials of adjacent fields are of opposite polarity.

In this embodiment, the display module includes 2K rows of gates, where K is a positive integer;

optionally, the method further includes:

under the condition that a first target row grid electrode is opened, the multi-path control circuit sequentially provides voltage signals of a first preset polarity to the M data lines;

under the condition that a second target row grid electrode is opened, the multi-path control circuit sequentially provides voltage signals of a second preset polarity to the M data lines;

the first target behavior is any grid electrode in grids from a line 1 to a line K in the display module, and the second target behavior is any grid electrode in grids from a line K +1 to a line 2K in the display module;

the first predetermined polarity is opposite to the second predetermined polarity. Specifically, reference may be made to the description in the first embodiment, which is not repeated herein.

In this embodiment, the polarities of the voltage signals charged to the sub-pixels of the upper half frame or the lower half frame in the same frame are the same, and the polarities of the voltage signals charged to the sub-pixels of the upper half frame and the lower half frame in the same frame are opposite. For example, the first row sub-pixels to the K row sub-pixels included in the display panel are charged with positive electricity, and the K +1 row sub-pixels to the 2K row sub-pixels included in the display panel are charged with negative electricity. Assuming that the display panel includes 2L columns of sub-pixels, the first to L-th columns of sub-pixels included in the display panel may be positively charged, and the L + 1-2L-th columns of sub-pixels included in the display panel may be negatively charged, but the invention is not limited thereto.

If the pixel thin film tube in the sub-pixel is NTFT, the negative charging of the lower half part saves some time for positive charging of the upper half screen. In practical applications, the charging time of each pixel can be set to 0.1-1.0 μ s for negative charging, and 0.5-1.5 μ s for positive charging.

Therefore, the charging time of the lower half frame can be prolonged by shortening the charging time of the upper half frame, or the charging time of the upper half frame can be prolonged by shortening the charging time of the lower half frame, so that the sufficient charging time of the sub-pixels can be ensured.

In the fifth embodiment, the electronic device controls display of the i-th picture frame by pixel inversion driving. I.e. the potentials of adjacent pixels are of opposite polarity.

In this embodiment, M is equal to 2Z;

optionally, the method further includes:

under the condition that a grid electrode included by the display module is opened, the multi-path control circuit sequentially provides voltage signals of a first preset polarity for the 1 st to the Z-th data lines in the M data lines, and the multi-path control circuit sequentially provides voltage signals of a second preset polarity for the Z +1 th to the 2Z-th data lines in the M data lines;

the first preset polarity is opposite to the second preset polarity, and specific reference may be made to the description in the first embodiment, which is not repeated herein.

Z is the number of sub-pixels included in one pixel. In addition, although the present embodiment is described by taking an example in which 2 pixels are connected to one voltage signal output terminal, the present invention is not limited to the number of pixels connected to one voltage signal output terminal, and in other embodiments, if the number of pixels in one voltage signal output terminal is greater than 2, all pixels connected to one voltage signal output terminal may be driven by pixel inversion polling driving.

In this embodiment, the polarities of the voltage signals charged to the sub-pixels belonging to the same pixel are the same, and the polarities of the voltage signals charged to the sub-pixels of the same pixel are opposite. As shown in fig. 8, the 6 sub-pixels controlled by one voltage signal output terminal are column-inverted in units of pixels of 3 sub-pixels. The first three columns of sub-pixels are driven with positive voltage, and the last three columns of sub-pixels are driven with negative voltage.

Thus, the charging time of the next pixel can be prolonged by shortening the charging time of the previous pixel, or the charging time of the previous pixel can be prolonged by the charging time of the next pixel, so that the sufficient charging time of the sub-pixels can be ensured.

It should be noted that, for a scene with asymmetric charging time of different polarities, charging by using the pixel charging method of the embodiment of the present invention all belongs to the protection scope of the embodiment of the present invention.

Various optional embodiments described in the embodiments of the present invention may be implemented in combination with each other or separately, and the embodiments of the present invention are not limited thereto.

Referring to fig. 9, fig. 9 is a block diagram of an electronic device according to an embodiment of the present invention. The electronic equipment of the embodiment comprises a pixel charging module, wherein the pixel charging module comprises at least one multi-path control circuit, and the multi-path control circuit is connected with M data lines and used for providing corresponding voltage signals for the M data lines in a time-sharing manner; m is an integral multiple of Z, and Z is the number of sub-pixels included in one pixel. As shown in fig. 9, the electronic device 900 includes:

a first determining module 901, configured to determine a polarity of a voltage signal provided by the multi-channel control circuit to a target data line in the M data lines;

a first control module 902, configured to control a duration of providing a voltage signal to the target data line to be equal to a first charging duration if the polarity is a first polarity;

a second control module 903, configured to control a duration of providing a voltage signal to the target data line to be equal to a second charging duration if the polarity is a second polarity;

Optionally, if the pixel transistor included in the sub-pixel is an N-type transistor, the first polarity is a positive polarity, and the second polarity is a negative polarity; alternatively, the first and second electrodes may be,

Optionally, the electronic device 900 further includes:

a first obtaining module, configured to obtain the first minimum charging duration and the second minimum charging duration before determining a polarity of a voltage signal provided by the multi-channel control circuit to a target data line of the M data lines;

the second determining module is used for determining a first charging duration when the voltage signal of the first polarity is used for charging the sub-pixels according to the first minimum charging duration;

and the third determining module is used for determining a second charging duration when the voltage signal of the second polarity is used for charging the sub-pixel according to the second minimum charging duration.

Optionally, the electronic device 900 further includes:

the second acquisition module is used for acquiring a charging reserved time length before the first charging duration and the second charging duration are determined;

the second determining module is specifically configured to:

the third determining module is specifically configured to:

Optionally, the electronic device 900 further includes:

the display module comprises a first charging module, a second charging module and a multi-path control circuit, wherein the first charging module is used for sequentially providing voltage signals of a first preset polarity to odd-numbered rows of data lines in the M data lines under the condition that a grid electrode included in the display module is opened, and the multi-path control circuit sequentially provides voltage signals of a second preset polarity to even-numbered rows of data lines in the M data lines;

wherein the first predetermined polarity is opposite to the second predetermined polarity.

Optionally, the electronic device 900 further includes:

the second charging module is used for sequentially providing voltage signals of a first preset polarity to the M data lines by the multi-path control circuit under the condition that the odd-numbered row grid electrodes included in the display module are opened in the display process of the ith picture frame; under the condition that even-numbered row gates included in the display module are opened, the multi-path control circuit sequentially provides voltage signals of a second preset polarity to the M data lines;

wherein the first preset polarity is opposite to the second preset polarity, and i is a positive integer.

Optionally, the electronic device 900 further includes:

and the third control module is used for controlling the grid electrode included by the display module to be opened at least once after the display of the ith picture frame is finished and before the display of the (i + 1) th picture frame is started.

Optionally, the electronic device 900 further includes:

a third charging module to:

Optionally, the display module includes 2K rows of gates, where K is a positive integer;

the electronic device 900 further comprises:

a fourth charging module to:

the first predetermined polarity is opposite to the second predetermined polarity.

Optionally, M equals 2Z;

the electronic device 900 further comprises:

the multi-path control circuit is used for sequentially providing voltage signals of a first preset polarity to the 1 st to the Z th data lines in the M data lines under the condition that a grid electrode included in the display module is opened, and sequentially providing voltage signals of a second preset polarity to the Z +1 th to the 2Z data lines in the M data lines;

The electronic device 900 can implement the processes in the method embodiment of the present invention and achieve the same beneficial effects, and is not described herein again to avoid repetition.

Referring to fig. 10, fig. 10 is a second structural diagram of an electronic device according to a second embodiment of the present invention, where the electronic device may be a hardware structural diagram of an electronic device for implementing various embodiments of the present invention. The electronic equipment of the embodiment comprises a pixel charging module, wherein the pixel charging module comprises at least one multi-path control circuit, and the multi-path control circuit is connected with M data lines and used for providing corresponding voltage signals for the M data lines in a time-sharing manner; m is an integral multiple of Z, and Z is the number of sub-pixels included in one pixel. As shown in fig. 10, the electronic device 1000 includes, but is not limited to: a radio frequency unit 1001, a network module 1002, an audio output unit 1003, an input unit 1004, a sensor 1005, a display unit 1006, a user input unit 1007, an interface unit 1008, a memory 1009, a processor 1010, and a power supply 1011. Those skilled in the art will appreciate that the electronic device configuration shown in fig. 10 does not constitute a limitation of the electronic device, and that the electronic device may include more or fewer components than shown, or some components may be combined, or a different arrangement of components. In the embodiment of the present invention, the electronic device includes, but is not limited to, a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a wearable device, a pedometer, and the like.

Wherein, the processor 1010 is configured to:

Optionally, the processor 1010 is further configured to:

acquiring the first minimum charging time and the second minimum charging time;

Optionally, the processor 1010 is further configured to:

acquiring a charging reserved time length;

Optionally, the processor 1010 is further configured to:

a processor 1010, further configured to:

Optionally, M equals 2Z; a processor 1010, further configured to:

It should be noted that, in this embodiment, the electronic device 1000 may implement each process in the method embodiment of the present invention and achieve the same beneficial effects, and for avoiding repetition, details are not described here.

It should be understood that, in the embodiment of the present invention, the radio frequency unit 1001 may be used for receiving and sending signals during a message transmission or a call, and specifically, receives downlink data from a base station and then processes the received downlink data to the processor 1010; in addition, the uplink data is transmitted to the base station. In general, radio frequency unit 1001 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like. Further, the radio frequency unit 1001 may also communicate with a network and other devices through a wireless communication system.

The electronic device provides wireless broadband internet access to the user through the network module 1002, such as assisting the user in sending and receiving e-mails, browsing web pages, and accessing streaming media.

The audio output unit 1003 may convert audio data received by the radio frequency unit 1001 or the network module 1002 or stored in the memory 1009 into an audio signal and output as sound. Also, the audio output unit 1003 may also provide audio output related to a specific function performed by the electronic apparatus 1000 (e.g., a call signal reception sound, a message reception sound, etc.). The audio output unit 1003 includes a speaker, a buzzer, a receiver, and the like.

The input unit 1004 is used to receive an audio or video signal. The input Unit 1004 may include a Graphics Processing Unit (GPU) 10041 and a microphone 10042, the Graphics processor 10041 Processing image data of still pictures or video obtained by an image capturing device (such as a camera) in a video capturing mode or an image capturing mode. The processed image frames may be displayed on the display unit 1006. The image frames processed by the graphic processor 10041 may be stored in the memory 1009 (or other storage medium) or transmitted via the radio frequency unit 1001 or the network module 1002. The microphone 10042 can receive sound and can process such sound into audio data. The processed audio data may be converted into a format output transmittable to a mobile communication base station via the radio frequency unit 1001 in case of a phone call mode.

The electronic device 1000 also includes at least one sensor 1005, such as light sensors, motion sensors, and other sensors. Specifically, light sensor includes ambient light sensor and proximity sensor, and wherein, ambient light sensor can adjust the luminance of display module assembly 10061 according to the light and shade of ambient light, and proximity sensor can close display module assembly 10061 and/or be shaded when electronic equipment 1000 moves to the ear. As one type of motion sensor, an accelerometer sensor can detect the magnitude of acceleration in each direction (generally three axes), detect the magnitude and direction of gravity when stationary, and can be used to identify the posture of an electronic device (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), and vibration identification related functions (such as pedometer, tapping); the sensors 1005 may also include a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, etc., which will not be described in detail herein.

The display unit 1006 is used to display information input by the user or information provided to the user. The Display unit 1006 may include a Display module 10061, and the Display module 10061 may be configured by a Liquid Crystal Display (LCD), an Organic Light-Emitting Diode (OLED), or the like.

The user input unit 1007 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the electronic device. Specifically, the user input unit 1007 includes a touch panel 10071 and other input devices 10072. The touch panel 10071, also referred to as a touch screen, may collect touch operations by a user on or near the touch panel 10071 (e.g., operations by a user on or near the touch panel 10071 using a finger, a stylus, or any other suitable object or attachment). The touch panel 10071 may include two parts, a touch detection device and a touch controller. The touch detection device detects the touch direction of a user, detects a signal brought by touch operation and transmits the signal to the touch controller; the touch controller receives touch information from the touch sensing device, converts the touch information into touch point coordinates, sends the touch point coordinates to the processor 1010, and receives and executes commands sent by the processor 1010. In addition, the touch panel 10071 may be implemented by various types, such as a resistive type, a capacitive type, an infrared ray, and a surface acoustic wave. In addition to the touch panel 10071, the user input unit 1007 can include other input devices 10072. Specifically, the other input devices 10072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a track ball, a mouse, and a joystick, which are not described herein again.

Further, the touch panel 10071 can be overlaid on the display module 10061, and when the touch panel 10071 detects a touch operation thereon or nearby, the touch panel is transmitted to the processor 1010 to determine the type of the touch event, and then the processor 1010 provides a corresponding visual output on the display module 10061 according to the type of the touch event. Although in fig. 10, the touch panel 10071 and the display module 10061 are two independent components to implement the input and output functions of the electronic device, in some embodiments, the touch panel 10071 and the display module 10061 may be integrated to implement the input and output functions of the electronic device, which is not limited herein.

The interface unit 1008 is an interface for connecting an external device to the electronic apparatus 1000. For example, the external device may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device having an identification module, an audio input/output (I/O) port, a video I/O port, an earphone port, and the like. The interface unit 1008 may be used to receive input from external devices (e.g., data information, power, etc.) and transmit the received input to one or more elements within the electronic device 1000 or may be used to transmit data between the electronic device 1000 and the external devices.

The memory 1009 may be used to store software programs as well as various data. The memory 1009 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, and the like), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the cellular phone, and the like. Further, the memory 1009 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.

The processor 1010 is a control center of the electronic device, connects various parts of the entire electronic device using various interfaces and lines, and performs various functions of the electronic device and processes data by operating or executing software programs and/or modules stored in the memory 1009 and calling data stored in the memory 1009, thereby integrally monitoring the electronic device. Processor 1010 may include one or more processing units; preferably, the processor 1010 may integrate an application processor, which mainly handles operating systems, user interfaces, application programs, etc., and a modem processor, which mainly handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into processor 1010.

The electronic device 1000 may further include a power source 1011 (e.g., a battery) for supplying power to various components, and preferably, the power source 1011 may be logically connected to the processor 1010 through a power management system, so as to manage charging, discharging, and power consumption management functions through the power management system.

In addition, the electronic device 1000 includes some functional modules that are not shown, and are not described in detail herein.

Preferably, an embodiment of the present invention further provides an electronic device, which includes a processor 1010, a memory 1009, and a computer program stored in the memory 1009 and capable of running on the processor 1010, where the computer program is executed by the processor 1010 to implement each process of the above-mentioned pixel charging method embodiment, and can achieve the same technical effect, and in order to avoid repetition, details are not described here again.

An embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements each process of the pixel charging method embodiment, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here. The computer-readable storage medium may be a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling an electronic device (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A pixel charging method is applied to electronic equipment and is characterized in that the electronic equipment comprises a pixel charging module, the pixel charging module comprises at least one multi-path control circuit, and the multi-path control circuit is connected with M data lines and used for providing corresponding voltage signals for the M data lines in a time-sharing manner; m is integral multiple of Z, and Z is the number of sub-pixels included in one pixel;

the method comprises the following steps:

the first charging duration is longer than a first minimum charging duration required when the sub-pixels are charged through the voltage signals of the first polarity; the second charging duration is longer than a second minimum charging duration required when the sub-pixels are charged through the voltage signals of the second polarity and is shorter than a preset charging duration; the predetermined charging duration is greater than the second minimum charging duration and less than the first minimum charging duration;

the determining the polarity of the voltage signal provided by the multi-path control circuit to the target data line of the M data lines comprises:

before controlling display of an ith picture frame, determining the polarity of the voltage signal based on any one of the ith picture frame, the layout of sub-pixels in the display module and the pixel torsion direction of each sub-pixel of the ith-1 picture frame, wherein i is a positive integer;

before determining the polarity of the voltage signal provided by the multi-path control circuit to the target data line of the M data lines, the method further includes:

acquiring the first minimum charging time and the second minimum charging time;

2. The method of claim 1, wherein if the sub-pixel comprises an N-type pixel transistor, the first polarity is a positive polarity and the second polarity is a negative polarity; alternatively, the first and second electrodes may be,

3. The method of claim 1, wherein determining the first charge duration and the second charge duration is preceded by:

acquiring a charging reserved time length;

4. The method of any of claims 1 to 3, further comprising:

under the condition that a grid electrode of a grid electrode pixel transistor included in the display module is opened, the multi-path control circuit sequentially provides voltage signals of a first preset polarity for odd-numbered data lines in the M data lines, and the multi-path control circuit sequentially provides voltage signals of a second preset polarity for even-numbered data lines in the M data lines;

5. The method of any of claims 1 to 3, further comprising:

6. The method according to claim 5, further comprising, after completion of the display of the ith picture frame, before starting the display of the (i + 1) th picture frame:

7. The method of any of claims 1 to 3, further comprising:

8. The method according to any one of claims 1 to 3, wherein the display module comprises 2K rows of gates, K being a positive integer;

the method further comprises the following steps:

the first target behavior is any grid electrode in the grids from the 1 st row to the Kth row in the display module, and the second target behavior is any grid electrode in the grids from the K +1 st row to the 2 Kth row in the display module;

9. The method according to any one of claims 1 to 3, wherein M is equal to 2Z;

the method further comprises the following steps:

10. An electronic device is characterized by comprising a pixel charging module, wherein the pixel charging module comprises at least one multi-path control circuit, and the multi-path control circuit is connected with M data lines and is used for providing corresponding voltage signals for the M data lines in a time-sharing manner; m is integral multiple of Z, and Z is the number of sub-pixels included in one pixel;

the electronic device includes:

the first determining module is further configured to determine a polarity of the voltage signal based on any one of an ith picture frame, a layout of sub-pixels in the display module, and a pixel torsion direction of each sub-pixel in an i-1 th picture frame before controlling display of the ith picture frame, where i is a positive integer;

11. The electronic device of claim 10, wherein if the sub-pixel comprises an N-type pixel transistor, the first polarity is a positive polarity and the second polarity is a negative polarity; alternatively, the first and second electrodes may be,

12. The electronic device of claim 10, further comprising:

the second determining module is specifically configured to:

the third determining module is specifically configured to:

13. The electronic device of any of claims 10-12, further comprising:

14. The electronic device of any of claims 10-12, further comprising:

15. The electronic device of claim 14, further comprising:

16. The electronic device of any of claims 10-12, further comprising:

a third charging module to:

17. The electronic device according to any one of claims 10 to 12, wherein the display module comprises 2K rows of gates, K being a positive integer;

the electronic device further includes:

a fourth charging module to:

18. The electronic device of any of claims 10-12, wherein M is equal to 2Z;

the electronic device further includes:

19. An electronic device comprising a processor, a memory, and a computer program stored on the memory and executable on the processor, the computer program, when executed by the processor, implementing the steps of the pixel charging method according to any one of claims 1 to 9.

20. A computer-readable storage medium, characterized in that a computer program is stored thereon, which computer program, when being executed by a processor, carries out the steps of the pixel charging method according to any one of claims 1 to 9.