CN113362762B

CN113362762B - Display panel, control method thereof and display device

Info

Publication number: CN113362762B
Application number: CN202110738713.8A
Authority: CN
Inventors: 袁粲; 李永谦; 袁志东; 张大成; 吴刘; 王帅
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2021-06-30
Filing date: 2021-06-30
Publication date: 2022-12-09
Anticipated expiration: 2041-06-30
Also published as: CN113362762A

Abstract

A display panel, a control method thereof and a display device are provided, wherein the display panel comprises: a substrate, the substrate comprising: a display area and a non-display area, the display panel further comprising: the display device comprises M scanning lines arranged on a substrate and extending along a first direction, N data lines extending along a second direction, and M rows and N columns of sub-pixels located in a display area, wherein the ith row and the jth column of sub-pixels are respectively and electrically connected with the ith scanning line and the jth data line, and each sub-pixel comprises: a pixel circuit, the pixel circuit comprising: a switching transistor; the data signal includes: a first changing edge; when the sub-pixels in the jth row and the jth column of the first row are displayed, the starting time of the first change edge of the data signal provided by the jth data line is equal to the first time, the first time is in the falling edge of the scanning line of the first row, and the level of the scanning signal provided for the scanning line of the first row is equal to the time of the third level, and the third level is the level which enables the switching transistor to be in an off state.

Description

Display panel, control method thereof and display device

Technical Field

The embodiment of the disclosure relates to but is not limited to the technical field of display, and particularly relates to a display panel, a control method thereof and a display device.

Background

Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active Light Emitting display devices, and have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, very high response speed, thinness, flexibility, low cost, and the like. With the continuous development of Display technology, a Flexible Display device (Flexible Display) using an OLED or a QLED as a light emitting device and using a Thin Film Transistor (TFT) for signal control has become a mainstream product in the Display field.

In order to pursue better display effect, a high-resolution OLED display panel is developed, such as an 8K display panel, and after the high-resolution OLED display panel is manufactured, a COF (Chip On Film) is further required to connect the source driver Chip and the data lines in the display panel.

Disclosure of Invention

The following is a summary of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

The present disclosure provides a display panel including: a substrate, the substrate comprising: a display area and a non-display area, the display panel further comprising: the display device comprises M scanning lines arranged on a substrate and extending along a first direction, N data lines extending along a second direction, and M rows and N columns of sub-pixels located in a display area, wherein the ith row and the jth column of sub-pixels are respectively electrically connected with the ith scanning line and the jth data line, and each sub-pixel comprises: a pixel circuit, the pixel circuit comprising: the switch transistor, i is more than or equal to 1 and less than or equal to M, and j is more than or equal to 1 and less than or equal to N;

the scan lines are configured to provide scan signals to the pixel circuits in the sub-pixels, and the data lines are configured to provide data signals to the pixel circuits in the sub-pixels, the data signals including: a first change edge in which the data signal changes from a first level to a second level, the first level being a level required for sub-pixel display, the second level being a threshold level;

when the sub-pixels in the jth row and the jth column of the first row are displayed, the start time of the first change edge of the data signal provided by the jth data line is equal to the first time, the first time is within the falling edge of the scanning line of the first row, and the level of the scanning signal provided for the scanning line of the first row is equal to the time of the third level, and the third level is the level which enables the switching transistor to be in an off state.

In some possible implementations, the method further includes: the first grid driving chip, the second grid driving chip and the source driving chip are positioned in the non-display area; the display area includes: a first side, a second side, and a third side, the first side and the second side being disposed opposite each other, the third side being different from the first side and the second side; the first gate driving chip includes: m cascaded first shift registers, the second grid drive chip includes: m cascaded second shift registers;

the first grid driving chip is positioned on the first side of the display area;

the second grid driving chip is positioned at the second side of the display area;

the source electrode driving chip is positioned on the third side of the display area;

the ith scanning line is electrically connected with the ith first shift register and the ith second shift register respectively.

In some possible implementations, the method further includes: a time sequence control chip and a chip on film;

the source electrode driving chip is positioned on the chip on film;

the time sequence control chip is respectively electrically connected with the first grid driving chip, the second grid driving chip and the source driving chip, and is set to output a first signal to the first grid driving chip and the second grid driving chip and a second signal to the source driving chip;

the first grid driving chip is arranged to generate a scanning signal according to the first signal;

the second grid driving chip is arranged to generate a scanning signal according to the first signal;

the source driving chip is configured to generate a data signal according to the second signal.

In some possible implementations, the first sub-pixel is a sub-pixel located in an M-th row and a first column or a sub-pixel located in an M-th row and an N-th column, the second sub-pixel is a sub-pixel located in an M-th row and a K-th column, the third sub-pixel is a sub-pixel located in a first row and a first column or a sub-pixel located in a first row and an N-th column, and the fourth sub-pixel is a sub-pixel located in a first row and a K-th column;

the first falling edge duration is less than the third falling edge duration;

the third falling edge duration is less than the second falling edge duration;

the third falling edge duration is less than the fourth falling edge duration;

the first falling edge duration is the duration of the falling edge of the scanning signal provided by the scanning line of the Mth row when the first sub-pixel displays; the second falling edge duration is the duration of the falling edge of the scanning signal provided by the scanning line of the Mth row when the second sub-pixel displays; the third falling edge duration is the duration of the falling edge of the scanning signal provided by the first row of scanning lines when the third sub-pixel displays; the duration of the fourth falling edge is the duration of the falling edge of the scanning signal provided by the first row of scanning lines when the fourth sub-pixel displays; when N is an even number, K = N/2, and when N is an odd number, K = (N-1)/2.

In some possible implementations, the data signal further includes: a second change edge in which the data signal changes from the second level to the first level;

when the sub-pixels in the ith row and the jth column are displayed, the start time of the second change edge of the data signal provided by the jth data line is earlier than the start time of the falling edge of the scanning signal of the ith row of scanning lines.

In some possible implementations, when the ith row and jth column sub-pixels are displaying, a time interval between a start time of a second variation edge of the data signal provided by the jth data line and a start time of the first variation edge is equal to a time interval between a start time of a second variation edge of the data signal provided by the jth data line and a start time of the first variation edge when the ith +1 row and jth column sub-pixels are displaying.

In some possible implementations, when the ith row and the jth column of sub-pixels are displayed, the duration of the falling edge of the scanning signal provided by the ith row of scanning lines is longer than the duration of the falling edge of the scanning signal provided by the (i + 1) th row of scanning lines when the (i + 1) th row and the jth column of sub-pixels are displayed.

In some possible implementation manners, when the ith row and the kth column of sub-pixels display, the duration of the falling edge of the scanning signal provided by the ith row of scanning lines is less than that when the ith row and the kth +1 column of sub-pixels display, the duration of the falling edge of the scanning signal provided by the ith row of scanning lines is less than that, and k is greater than or equal to 1 and less than or equal to N/2.

In some possible implementations, the method further includes: the first power line, the second power line, the compensation control line and the compensation signal line, the sub-pixel further comprising: a light emitting element, a pixel circuit configured to drive the light emitting element to emit light, the pixel circuit further comprising: a driving transistor, a compensation transistor and a storage capacitor;

the control electrode of the switching transistor is electrically connected with the scanning line, the first electrode of the switching transistor is electrically connected with the data line, and the second electrode of the switching transistor is electrically connected with the control electrode of the driving transistor;

the first pole of the driving transistor is electrically connected with a first power line, and the second pole of the driving transistor is electrically connected with the first pole of the compensation transistor and the light-emitting element respectively;

the control electrode of the compensation transistor is electrically connected with the compensation control line, and the second electrode of the compensation transistor is electrically connected with the compensation signal line;

the first end of the storage capacitor is electrically connected with the gate electrode of the driving transistor, and the second end of the storage capacitor is electrically connected with the second pole of the driving transistor;

the light emitting element is electrically connected with a second power line;

the switching transistor, the compensation transistor, and the driving transistor are oxide transistors.

In some possible implementations, the method further includes: clock signal lines extending in a second direction and located at first and second sides of the display area;

the clock signal line is electrically connected with the time sequence control chip, the first grid driving chip and the second grid driving chip respectively.

In some possible implementations, the chip on film includes: 2Q chip on films arranged at intervals;

the source electrode driving chip on the ith crystal covering sub-film is electrically connected with the P data wires; when the ith row of sub-pixels is displayed, a difference value tCOF between the duration of the first change edge of the data signal provided by the pth data line connected to the source driver chip on the ith flip-chip sub-film and the duration of the first change edge of the data signal provided by the pth data line connected to the source driver chip on the i-1 flip-chip sub-film and the duration of the first change edge of the data signal provided by the pth data line connected to the source driver chip on the ith flip-chip sub-film satisfies the following formula:

T_IC*Q+T_COF*(Q-1)＝T2-T1

wherein, T1 is a difference value between a start time of a first change edge of the data signal supplied to the third subpixel and a start time of a falling edge of the scan signal supplied to the third subpixel when the third subpixel displays, and T2 is a difference value between a start time of a falling edge of the data signal supplied to the fourth subpixel and a start time of a falling edge of the scan signal supplied to the fourth subpixel when the fourth subpixel displays.

In some possible implementations, T _ COF is equal to or greater than 0 and equal to or less than 0.5 nanoseconds.

In a second aspect, the present disclosure also provides a display device, including: the display panel is provided.

In a third aspect, the present disclosure also provides a control method of a display panel, configured to control the display panel, where the method includes:

providing a control signal to the display panel, so that when the sub-pixels in the jth row and the jth column of the first row are displayed, the starting time of a first change edge of a data signal provided by a jth data line is equal to a first time;

the first time is within a falling edge of the first row scanning line, and the level of a scanning signal provided for the first row scanning line is equal to a third level, wherein the third level is a level which enables the switching transistor to be in an off state;

the data signal includes: and the data signal changes from a first level to a second level within the first change edge, wherein the first level is a level required by the sub-pixel display, and the second level is a threshold level.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the example serve to explain the principles of the disclosure and not to limit the disclosure.

Fig. 1 is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure;

FIG. 2 is a timing diagram illustrating the display of the sub-pixels in the first row and the first column according to an embodiment of the present disclosure;

FIG. 3 is a timing diagram of the fourth sub-pixel during displaying;

FIG. 4 is a timing diagram of the first sub-pixel displaying signal;

FIG. 5 is a timing diagram of the second sub-pixel displaying signal;

FIG. 6 is an equivalent circuit diagram of a pixel circuit;

FIG. 7 is a schematic cross-sectional view of a display panel;

FIG. 8 is a schematic diagram of a T _ IC and a T _ COF provided in an exemplary embodiment;

FIG. 9 is a diagram illustrating exemplary data voltage and display uniformity relationships among four pixels of a display panel according to an exemplary embodiment;

FIG. 10 is a diagram illustrating a relationship between data voltages and display uniformity for four pixels of a display panel according to another exemplary embodiment;

fig. 11 is a diagram illustrating correspondence between data voltages and display uniformity of four pixels of a display panel according to an exemplary embodiment.

Detailed Description

The present disclosure describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of the embodiments described in this disclosure. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure that have been disclosed may also be combined with any conventional features or elements to form a technical solution as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other aspects to form yet another aspect defined by the claims. Thus, it should be understood that any features shown and/or discussed in this disclosure may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Unless otherwise defined, technical or scientific terms used in the disclosure of the present disclosure should have the ordinary meaning as understood by those of ordinary skill in the art to which the disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments may be implemented in a plurality of different forms. Those skilled in the art can readily appreciate the fact that the forms and details may be varied into a variety of forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict. To maintain the following description of the embodiments of the present disclosure clear and concise, a detailed description of some known functions and components have been omitted from the present disclosure. The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design

In the drawings, the size of each component, the thickness of layers, or regions may be exaggerated for clarity. Therefore, one aspect of the present disclosure is not necessarily limited to the dimensions, and the shapes and sizes of the respective components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present specification are provided for avoiding confusion among the constituent elements, and are not limited in number.

In this specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used to explain positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise explicitly specified or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art.

In this specification, a transistor refers to an element including at least three terminals, i.e., a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region where current mainly flows.

In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having some kind of electrical function" is not particularly limited as long as it can transmit and receive an electrical signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.

In the present specification, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

"about" in this disclosure means that the limits are not strictly defined, and that the numerical values are within the tolerances allowed for the process and measurement.

A display panel includes: the device comprises a time sequence control chip, a grid driving chip and a source driving chip. The time sequence control chip generates an initial data signal and a clock signal, the grid driving chip executes logic operation according to the clock signal to generate a scanning signal required by driving the display panel to display, and the source driving chip executes logic operation according to the initial data signal to generate a data signal required by driving the display panel to display. However, due to the increase of the size of the display panel and the factors of the circuit layout, the clock signal received by the gate driver chip and the initial data signal received by the source driver chip may have different signal delays, so that the scan signal and the data signal required by the display panel cannot be matched with each other when the display panel displays, thereby affecting the display quality of the display panel.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the disclosure, and fig. 2 is a timing diagram of signals when sub-pixels in a first row and a first column are displayed according to the embodiment of the disclosure. As shown in fig. 1, a display panel provided by an embodiment of the present disclosure may include: a substrate, the substrate comprising: a display area AA and a non-display area AA', the display panel further including: m scanning lines G1 to GM extending along a first direction, N data lines D1 to DN extending along a second direction and M rows and N columns of sub-pixels located in a display area, wherein the M rows and the j columns of sub-pixels are arranged on the substrate, the ith row and the jth column of sub-pixels are respectively and electrically connected with the ith scanning line and the jth data line, and each sub-pixel comprises: a pixel circuit, the pixel circuit comprising: and in the switching transistor, i is more than or equal to 1 and less than or equal to M, and j is more than or equal to 1 and less than or equal to N.

In one exemplary embodiment, as shown in fig. 2, the scan lines are arranged to supply scan signals G to the pixel circuits in the sub-pixels, and the data lines are arranged to supply data signals D to the pixel circuits in the sub-pixels, the data signals D including: the data signal changes from a first level to a second level within the first changing edge.

In one exemplary embodiment, the first level is a level required for sub-pixel display, and the second level is a threshold level. Fig. 2 illustrates an example in which the threshold level is equal to 0, which is not limited in this disclosure.

In an exemplary embodiment, as shown in fig. 2, when the sub-pixels in the jth row and jth column of the first row are displaying, the start time of the first change edge of the data signal D provided by the jth data line is equal to a first time T, the first time T is within the falling edge of the scan line of the first row, and the level of the scan signal provided for the scan line of the first row is equal to a time of a third level, the third level is a level that makes the switching transistor in an off state.

In one exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass, metal sheet; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

In an exemplary embodiment, the display panel is a high resolution display panel, and the refresh frequency of the display panel is high.

In one exemplary embodiment, the data signal may be a data voltage.

In an exemplary embodiment, the third level may be a negative voltage, and fig. 2 illustrates the third level as-3V.

In an exemplary embodiment, the first changing edge may be a rising edge or may be a falling edge depending on the first level and the second level. Fig. 2 is an example in which the first change edge is a rising edge.

In an exemplary embodiment, the display panel may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P including a sub-pixel emitting light of a first color, a sub-pixel emitting light of a second color, and a sub-pixel emitting light of a third color.

In an exemplary embodiment, the pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, and the disclosure is not limited thereto.

In an exemplary embodiment, the shape of the sub-pixel in the pixel unit may be a rectangular shape, a diamond shape, a pentagon shape, or a hexagon shape. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged in a horizontal parallel, vertical parallel, or delta-shaped manner, and when the pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or Square (Square) manner, which is not limited in this disclosure.

The display panel provided by the embodiment of the disclosure includes: a substrate, the substrate comprising: a display area and a non-display area, the display panel further comprising: the display device comprises M scanning lines arranged on a substrate and extending along a first direction, N data lines extending along a second direction, and M rows and N columns of sub-pixels located in a display area, wherein the ith row and the jth column of sub-pixels are respectively and electrically connected with the ith scanning line and the jth data line, and each sub-pixel comprises: a pixel circuit, the pixel circuit comprising: the switch transistor, i is more than or equal to 1 and less than or equal to M, and j is more than or equal to 1 and less than or equal to N; the scan lines are configured to provide scan signals to the pixel circuits in the sub-pixels, and the data lines are configured to provide data signals to the pixel circuits in the sub-pixels, the data signals including: a first change edge in which the data signal changes from a first level to a second level, the first level being a level required for sub-pixel display, the second level being a threshold level; when the sub-pixels in the jth row and the jth column of the first row are displayed, the starting time of the first change edge of the data signal provided by the jth data line is equal to the first time, the first time is in the falling edge of the scanning line of the first row, and the level of the scanning signal provided for the scanning line of the first row is equal to the time of the third level, and the third level is the level which enables the switching transistor to be in an off state. According to the display panel, the delay time of the scanning signal to the sub-pixel of the first row is the most effective, so that when the sub-pixel of the first row and the j column is arranged to display, the starting time of the first change edge of the data signal provided by the j data line is equal to the first time, the data signal can be changed only after the switching transistor in the sub-pixel is cut off, the scanning signal and the data signal are matched when each sub-pixel displays, the charging rate and the display uniformity of the sub-pixel can be improved, and the display effect of the display panel is improved.

In an exemplary embodiment, as shown in fig. 1, the display panel may further include: the display device comprises a first gate driving chip GOA1, a second gate driving chip GOA2 and a source driving chip which are positioned in a non-display area; the display area includes: the first side, the second side and the third side, the first side and the second side are oppositely arranged, and the third side is different from the first side and the second side.

In one exemplary embodiment, the first gate driving chip GOA1 includes: m cascaded first shift registers. The output end of the ith first shift register is electrically connected with the input end of the (i + 1) th first shift register.

In one exemplary embodiment, each of the first shift registers includes a plurality of transistors, and the transistors may be oxide transistors.

In one exemplary embodiment, the second gate driving chip GOA2 includes: m cascaded second shift registers. And the output end of the ith second shift register is electrically connected with the input end of the (i + 1) th second shift register.

In one exemplary embodiment, each of the second shift registers includes a plurality of transistors, and the transistors may be oxide transistors.

In one exemplary embodiment, the first gate driving chip GOA1 may be located at a first side of the display region; the second gate driving chip GOA2 may be located at a second side of the display area; the source driving chip may be located at a third side of the display region.

In an exemplary embodiment, the display panel may further include: a time sequence control chip and a chip on film. The source driving chip can be located on the chip on film.

In an exemplary embodiment, the timing control chip is electrically connected to the first gate driving chip, the second gate driving chip, and the source driving chip, respectively, and is configured to output a first signal to the first gate driving chip and the second gate driving chip and a second signal to the source driving chip. The first grid driving chip is arranged to generate a scanning signal according to the first signal; the second grid driving chip is arranged to generate a scanning signal according to the first signal; the source driving chip is configured to generate a data signal according to the second signal.

In one exemplary embodiment, the first signal may be a clock signal and a scan start signal suitable for the specifications of the first and second gate driving chips.

In one exemplary embodiment, the second signal may be a gray value and a control signal suitable for the specification of the data signal driver.

In one exemplary embodiment, the source driving chip may generate the data voltages to be supplied to the data lines D1 to DN using the second signal received from the timing control chip. For example, the source driving chip may sample a gray value using a clock signal and apply a data voltage corresponding to the gray value to the data lines D1 to DN in a unit of a sub-pixel row.

In one exemplary embodiment, the first and second gate driving chips may generate the scan signals to be supplied to the scan lines G1 to GM by receiving a first signal or the like from the timing control chip. For example, the first and second gate driving chips may sequentially supply scan signals having on-level pulses to the scan lines G1 to GM. For example, the first and second gate driving chips may be configured in the form of a shift register, and the scan signal may be generated in such a manner that a scan start signal provided in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal.

In an exemplary embodiment, FIG. 3 is a timing diagram of signals displayed by the fourth sub-pixel, and FIG. 4

Fig. 5 is a timing diagram of signals displayed by the first sub-pixel, and fig. 5 is a timing diagram of signals displayed by the second sub-pixel. As shown in fig. 1 to 5, the first sub-pixel P2 is a sub-pixel located in the M-th row and the first column or a sub-pixel located in the M-th row and the N-th column, the second sub-pixel P2 is a sub-pixel located in the M-th row and the K-th column, the third sub-pixel P3 is a sub-pixel located in the first row and the first column or a sub-pixel located in the first row and the N-th column, and the fourth sub-pixel P4 is a sub-pixel located in the first row and the K-th column. The first falling edge duration is the duration of the falling edge of the scanning signal provided by the scanning line of the Mth row when the first sub-pixel displays; the second falling edge duration is the duration of the falling edge of the scanning signal provided by the scanning line of the Mth row when the second sub-pixel displays; the third falling edge duration is the duration of the falling edge of the scanning signal provided by the first row of scanning lines when the third sub-pixel displays; the duration of the fourth falling edge is the duration of the falling edge of the scanning signal provided by the first row of scanning lines when the fourth sub-pixel displays; when N is an even number, K = N/2, and when N is an odd number, K = (N-1)/2. Fig. 2 shows a timing chart of signals when the third sub-pixel displays.

In an exemplary embodiment, the first falling edge duration is less than the third falling edge duration.

In an exemplary embodiment, the third falling edge duration is less than the second falling edge duration.

In an exemplary embodiment, the third falling edge duration is less than the fourth falling edge duration.

In an exemplary embodiment, as shown in fig. 2 to 5, the data signal further includes: and a second change edge in which the data signal changes from the second level to the first level. When the ith row and the jth column of sub-pixels display, the start time of the second change edge of the data signal D provided by the jth data line is earlier than the start time of the falling edge of the scanning signal G of the ith row of scanning lines.

According to the display panel, when the ith row and the jth column of sub-pixels display, the start time of the second change edge of the data signal provided by the jth data line is earlier than the start time of the falling edge of the scanning signal of the ith row of scanning line, so that the writing time of the data signal can be ensured, the charging rate of the sub-pixels is improved, and the display effect of the display panel is improved.

In an exemplary embodiment, when the ith row and jth column sub-pixels are displaying, a time interval between a start time of a second change edge of the data signal provided by the jth data line and a start time of a first change edge is equal to a time interval between a start time of a second change edge of the data signal provided by the jth data line and a start time of a first change edge when the ith row and jth column sub-pixels are displaying, that is, when sub-pixels located in the same column are displaying, phases of the data signals are the same.

In an exemplary embodiment, when the ith row and the jth column of sub-pixels display, the duration of a falling edge of a scanning signal provided by the ith row of scanning lines is longer than that of a falling edge of a scanning signal provided by the (i + 1) th row of scanning lines when the (i + 1) th row and the jth column of sub-pixels display.

In one exemplary embodiment, when the ith row and the kth column of sub-pixels are displayed, the duration of the falling edge of the scanning signal provided by the ith row of scanning lines is less than that when the ith row and the kth +1 column of sub-pixels are displayed, the duration of the falling edge of the scanning signal provided by the ith row of scanning lines is less than that, and k is greater than or equal to 1 and less than or equal to N/2.

As shown in fig. 2 and fig. 4, the duration of the falling edge of the scanning signal provided by the scanning line of the ith row is longer when the subpixel of the ith row and the jth column is displayed than when the subpixel of the (i + 1) th row and the jth column is displayed. Therefore, the level value of the scan signal is less than-3V at the start time of the first changing edge of the data signal when the first subpixel displays. FIG. 4 is an illustration of-4.638V.

As shown in fig. 3 and 5, the level value of the scan signal is less than-3V at the start time of the first transition edge of the data signal when the second subpixel displays. FIG. 5 is an illustration of-4.551V.

As shown in fig. 4 and 5, since the duration of the falling edge of the scan signal supplied from the scan line of the ith row is shorter than the duration of the falling edge of the scan signal supplied from the scan line of the ith row at the time of the display of the sub-pixels of the (i) th row and (k + 1) th column when the sub-pixels of the ith row are displayed, the level value of the scan signal at the start time of the first variation edge of the data signal when the first sub-pixel is displayed is lower than the level value of the scan signal at the start time of the first variation edge of the data signal when the second sub-pixel is displayed.

In one exemplary embodiment, the display panel may further include: a first power line VDD, a second power line VSS, a compensation control line Sn, and a compensation signal line Se.

In an exemplary embodiment, the first power line VDD may continuously supply a high level signal. The second power line VDD may continuously supply a low level signal.

In an exemplary embodiment, the display panel may further include: the sub-pixel further includes: and a light emitting element, the pixel circuit being configured to drive the light emitting element to emit light.

Fig. 6 is an equivalent circuit diagram of a pixel circuit. As shown in fig. 6, the pixel circuit may further include: drive transistor T2. Compensation transistor T3 and storage capacitor C _ST 。

In an exemplary embodiment, the control electrode of the switching transistor T1 is electrically connected to the scan line Gn, the first electrode of the switching transistor T1 is electrically connected to the data line Dn, and the second electrode of the switching transistor T1 is electrically connected to the control electrode of the driving transistor T2. A first electrode of the driving transistor T2 is electrically connected to a first power line VDD, and a second electrode of the driving transistor T2 is electrically connected to a first electrode of the compensating transistor T3 and the light emitting element, respectively. The control electrode of the compensation transistor T3 is electrically connected to the compensation control line Sn, and the second electrode of the compensation transistor is electrically connected to the compensation signal line Se. Storage capacitor C _ST Is electrically connected to the gate electrode of the driving transistor T2, and a storage capacitor C _ST Is electrically connected to the second pole of the driving transistor T2.

In an exemplary embodiment, the switching transistor T1 is configured to receive a data signal transmitted by the data line Dn under the control of the scan line Gn, and enable the gate electrode of the driving transistor T2 to receive the data signal. The first driving transistor T2 is used to generate a corresponding driving current at the second pole under the control of the data signal received by the gate electrode thereof. The compensation transistor T3 is used to extract the threshold voltage Vth and the mobility of the driving transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth. Storage capacitor C _ST For storing the potential of the gate electrode of the driving transistor T2.

In one exemplary embodiment, the light emitting element and the second power line VSS are electrically connected.

In one exemplary embodiment, the light emitting element may be an OLED or a QLED.

In one exemplary embodiment, when the light emitting element is an OLED, the light emitting element may include a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

Fig. 7 is a schematic cross-sectional structure diagram of a display panel, which illustrates the structure of three sub-pixels of the display panel. As shown in fig. 7, the display panel may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from a base 101, and an encapsulation layer 104 disposed on a side of the light emitting structure layer 103 away from the base 101, in a plane perpendicular to the display panel.

In an exemplary embodiment, the display panel may include other film layers, such as spacer pillars, etc., and the disclosure is not limited thereto.

In an exemplary embodiment, the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit, and only one transistor 101 and one storage capacitor 101A are exemplified in fig. 3. The light emitting structure layer 103 may include an anode 301, a pixel defining layer 302, an organic light emitting layer 303, and a cathode 304, the anode 301 is connected to the drain electrode of the driving transistor 210 through a via hole, the organic light emitting layer 303 is connected to the anode 301, the cathode 304 is connected to the organic light emitting layer 303, and the organic light emitting layer 303 emits light of a corresponding color under the driving of the anode 301 and the cathode 304. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 that are stacked, the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, the second encapsulation layer 402 may be made of organic materials, and the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, which may ensure that external moisture cannot enter the light emitting structure layer 103.

In an exemplary embodiment, the organic light Emitting Layer 303 may include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), a light Emitting Layer (EML), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) stacked one on another. In an exemplary embodiment, the hole injection layers of all the sub-pixels may be a common layer connected together, the electron injection layers of all the sub-pixels may be a common layer connected together, the hole transport layers of all the sub-pixels may be a common layer connected together, the electron transport layers of all the sub-pixels may be a common layer connected together, the hole blocking layers of all the sub-pixels may be a common layer connected together, the light emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.

In one exemplary embodiment, the switching transistor, the compensation transistor, and the driving transistor may be oxide transistors. An Oxide (Oxide) is used as an active layer of the Oxide transistor. The oxide thin film transistor has the advantages of low leakage current and the like. High resolution (Pixel Per inc, PPI for short) can be realized, low frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

In an exemplary embodiment, as shown in fig. 1, the display panel may further include: and a clock signal line CLK extending in the second direction and positioned at the first and second sides of the display region. The clock signal line is electrically connected with the time sequence control chip, the first grid driving chip and the second grid driving chip respectively.

In one exemplary embodiment, the flip chip film may include: 2Q spaced flip chip films 10. The source driving chip on the ith flip chip sub-film is electrically connected with the P data lines.

In an exemplary embodiment, fig. 8 is a schematic diagram of a T _ IC and a T _ COF provided by an exemplary embodiment, as shown in fig. 8, when the ith row of sub-pixels is displayed, a difference T _ COF between a duration of a first change edge of a data signal provided by a P-th data line connected to a source driver chip on an ith flip-chip sub-film and a duration of a first change edge of a data signal provided by a first data line connected to the source driver chip on the ith flip-chip sub-film and a duration of a first change edge of a data signal provided by a P-th data line connected to the source driver chip on an i-1 flip-chip sub-film satisfies the following formula:

T_IC*Q+T_COF*(Q-1)＝T2-T1

as shown in fig. 2 to 5, T1 is a difference between a start time of a first transition edge of a data signal supplied to the third subpixel and a start time of a falling edge of a scan signal supplied to the third subpixel when the third subpixel displays, and T2 is a difference between a start time of a falling edge of a data signal supplied to the fourth subpixel and a start time of a falling edge of a scan signal supplied to the fourth subpixel when the fourth subpixel displays.

The introduction of the T _ COF in the present disclosure can be compatible with the display of different loads (film thicknesses) of the display panel.

As shown in fig. 2, after the falling edge start time of the scanning signal in the third sub-pixel display period passes T1, the level of the scanning signal becomes-3V.

As shown in fig. 3, when the falling edge start time of the scanning signal at the time of displaying the fourth subpixel is T2, the level of the scanning signal becomes-3V.

As shown in fig. 4, when the falling edge start time of the scanning signal in the first subpixel display period is T1, the level of the scanning signal is-4.638V.

As shown in fig. 5, when the falling edge start time of the scanning signal in the second subpixel display period is T2, the level of the scanning signal is-4.551V.

In an exemplary embodiment, the T _ COF is greater than or equal to 0 and less than or equal to 0.5 nsec, and a value of the T _ COF depends on a load of the display panel.

In one exemplary embodiment, when the load of the display panel is such that T2-T1 is an integer multiple of T _ IC, T _ COF is equal to 0. When the load of the display panel makes T2-T1 larger than the integral multiple of T _ IC, T _ COF is not equal to 0.

In an exemplary embodiment, the number of flip-chip sub-films Q may be determined according to the load of the display panel and the T _ IC of each flip-chip sub-film.

In an exemplary embodiment, the T _ COF may be determined according to the load of the display panel and the T _ IC of each chip on sub-film.

Table 1 shows the luminance difference ratio of different sub-pixels at the data voltage D (V) at different T _ COF nanoseconds. Wherein, the smaller the brightness difference ratio, the better the display effect. As shown in table 1, the retardation difference of the first sub-pixel is relatively small, the second sub-pixel has relatively small difference when the data voltage is less than 4V, the retardation ratio difference of the third sub-pixel and the fourth sub-pixel is relatively large, and the retardation ratio of the fourth sub-pixel is greater than the retardation ratio of the third sub-pixel under the same data voltage. When the data voltage is greater than 4V, the difference ratio of the second sub-pixel is higher than that of the third sub-pixel and is less than that of the fourth sub-pixel.

TABLE 1

D(V)	P1	P2	P3	P4
						1	0.00％	0.19％	0.92％	1.18％
1.5	0.00％	0.05％	0.28％	0.39％
					2	0.00％	0.26％	0.62％	1.29％
2.5	0.06％	0.00％	0.65％	0.84％
					3	0.07％	0.24％	0.18％	0.78％
3.5	0.04％	0.04％	0.40％	0.54％
					4	0.03％	0.61％	0.47％	0.83％
4.5	0.02％	0.44％	0.39％	0.91％

In an exemplary embodiment, the film thickness of the display panel is different, and the load of the display panel is different. Here, the film thickness of the display panel refers to the thickness of the metal film of the display panel.

Fig. 9 is a corresponding relationship between data voltages and uniformity of four pixels of a display panel according to an exemplary embodiment, fig. 10 is a corresponding relationship between data voltages and uniformity of four pixels of a display panel according to another exemplary embodiment, and fig. 11 is a corresponding relationship between data voltages and uniformity of four pixels of a display panel according to an exemplary embodiment. The film thickness of the display panel provided in fig. 9 is the first film thickness, the film thickness of the display panel provided in fig. 10 is the second film thickness, and the film thickness of the display panel provided in fig. 11 is the third film thickness. The first film thickness is larger than the second film thickness, and the first film thickness is 1.1 times of the second film thickness. The second film is thicker than the third film, and the third film is 90% of the second film. Since the first film thickness is larger than the second film thickness, the resistance of the signal line in the display panel provided in fig. 9 is smaller than the resistance of the signal line in the display panel provided in fig. 10, the load of the display panel provided in fig. 9 is smaller than the load of the display panel provided in fig. 10, the delay of the scan signal and the data signal in the display panel provided in fig. 9 is smaller than the delay of the scan signal and the data signal in the display panel provided in fig. 10, and the uniformity of the four pixel points is higher during display. Since the second film thickness is larger than the third film thickness, the resistance of the signal line in the display panel provided in fig. 10 is smaller than the resistance of the signal line in the display panel provided in fig. 11, the load of the display panel provided in fig. 10 is smaller than the load of the display panel provided in fig. 11, the delay of the scan signal and the data signal in the display panel provided in fig. 10 is smaller than the delay of the scan signal and the data signal in the display panel provided in fig. 11, and the display uniformity of the four pixel points is higher when displaying.

In an exemplary embodiment, as shown in fig. 9, fig. 9 provides a display panel in which the display uniformity of the second sub-pixel is higher than that of the first sub-pixel, and when the voltage values of the data signals of the four sub-pixels are greater than 2V, the display uniformity of the first sub-pixel is higher than that of the third sub-pixel, and the display uniformity of the third sub-pixel is higher than that of the fourth sub-pixel.

In an exemplary embodiment, as shown in fig. 10, fig. 10 provides a display panel in which the display uniformity of the second sub-pixel is higher than that of the first sub-pixel, and when the voltage values of the data signals of the four sub-pixels are greater than 1.5V, the display uniformity of the first sub-pixel is higher than that of the third sub-pixel, and the display uniformity of the third sub-pixel is higher than that of the fourth sub-pixel.

In an exemplary embodiment, as shown in fig. 11, fig. 11 provides the display panel in which the display uniformity of the second sub-pixel is higher than that of the first sub-pixel, the display uniformity of the first sub-pixel is higher than that of the fourth sub-pixel, and the display uniformity of the fourth sub-pixel is higher than that of the third sub-pixel.

The embodiment of the present disclosure also provides a display device, including: a display panel.

In practical applications, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a navigator and the like.

The display panel is the display panel provided in any of the foregoing embodiments, and the implementation principle and the implementation effect are similar and are not described again here.

The embodiment of the present disclosure further provides a control method of a display panel, which is configured to control the display panel, and the control method of the display panel provided by the embodiment of the present disclosure may include:

providing a control signal to the display panel, so that when the sub-pixels in the jth row and the jth column of the first row are displayed, the starting time of a first change edge of a data signal provided by a jth data line is equal to a first time; the first time is within a falling edge of the first row of scanning lines, and the level of the scanning signal provided for the first row of scanning lines is equal to the time of a third level, and the third level is a level which enables the switching transistor to be in an off state. The data signal includes: and the first change edge changes the data signal from a first level to a second level in the first change edge, wherein the first level is a level required by the sub-pixel display, and the second level is a threshold level.

The drawings in this disclosure relate only to the structures to which the embodiments of the disclosure relate and other structures may be referred to in general design.

For clarity, the thickness and dimensions of layers or microstructures are exaggerated in the drawings that are used to describe embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the terms of the appended claims.

Claims

1. A display panel, comprising: a substrate, the substrate comprising: a display area and a non-display area, the display panel further comprising: the display device comprises M scanning lines arranged on a substrate and extending along a first direction, N data lines extending along a second direction, and M rows and N columns of sub-pixels located in a display area, wherein the ith row and the jth column of sub-pixels are respectively electrically connected with the ith scanning line and the jth data line, and each sub-pixel comprises: a pixel circuit, the pixel circuit comprising: a switching transistor, i is more than or equal to 1 and less than or equal to M, and j is more than or equal to 1 and less than or equal to N;

when the sub-pixels in the jth row and the jth column display, the starting time of a first change edge of a data signal provided by a jth data line is equal to a first time, the first time is within a falling edge of a scanning line of the first row, and the level of a scanning signal provided for the scanning line of the first row is equal to the time of a third level, and the third level is a level which enables a switching transistor to be in an off state;

the first sub-pixel is a sub-pixel positioned in an M-th row and a first column or a sub-pixel positioned in an M-th row and an N-th column, the second sub-pixel is a sub-pixel positioned in an M-th row and a K-th column, the third sub-pixel is a sub-pixel positioned in a first row and a first column or a sub-pixel positioned in an N-th column of the first row, and the fourth sub-pixel is a sub-pixel positioned in a K-th column of the first row;

the first falling edge duration is less than the third falling edge duration;

the third falling edge duration is less than the second falling edge duration;

the third falling edge duration is less than the fourth falling edge duration;

2. The display panel according to claim 1, further comprising: the first grid driving chip, the second grid driving chip and the source driving chip are positioned in the non-display area; the display area includes: a first side, a second side, and a third side, the first side and the second side being disposed opposite each other, the third side being different from the first side and the second side; the first gate driving chip includes: m cascaded first shift registers, the second grid drive chip includes: m cascaded second shift registers;

3. The display panel according to claim 2, characterized by further comprising: a time sequence control chip and a chip on film;

the source electrode driving chip is positioned on the chip on film;

4. The display panel of claim 1, wherein the data signal further comprises: a second change edge in which the data signal changes from the second level to the first level;

when the sub-pixels in the ith row and the jth column are displayed, the start time of a second change edge of the data signal provided by the jth data line is earlier than the start time of a falling edge of the scanning signal of the scanning line in the ith row.

5. The display panel according to claim 4, wherein when the ith row and the jth column of sub-pixels are displaying, a time interval between a start time of a second changing edge of the data signal provided by the jth data line and a start time of the first changing edge is equal to a time interval between a start time of a second changing edge of the data signal provided by the jth data line and a start time of the first changing edge when the ith +1 row and the jth column of sub-pixels are displaying.

6. The display panel according to claim 5, wherein when the ith row and the jth column of sub-pixels display, the duration of the falling edge of the scanning signal provided by the ith row of scanning lines is longer than that when the (i + 1) th row and the jth column of sub-pixels display, the duration of the falling edge of the scanning signal provided by the (i + 1) th row of scanning lines is longer.

7. The display panel of claim 6, wherein when the ith row and the kth column of sub-pixels display, the duration of the falling edge of the scanning signal provided by the ith row of scanning lines is less than that when the ith row and the kth +1 column of sub-pixels display, the duration of the falling edge of the scanning signal provided by the ith row of scanning lines is 1 ≦ k ≦ N/2.

8. The display panel according to any one of claims 1 to 7, further comprising: the first power line, the second power line, the compensation control line and the compensation signal line, the sub-pixel further comprising: a light emitting element, a pixel circuit configured to drive the light emitting element to emit light, the pixel circuit further comprising: a driving transistor, a compensation transistor and a storage capacitor;

the light emitting element is electrically connected with a second power line;

9. The display panel according to claim 3, further comprising: clock signal lines extending in a second direction and located at first and second sides of the display area;

the clock signal line is respectively and electrically connected with the time sequence control chip, the first grid driving chip and the second grid driving chip.

10. The display panel according to claim 9, wherein the chip on film comprises: 2Q chip on films arranged at intervals;

the source electrode driving chip on the ith crystal covering sub-film is electrically connected with the P data wires; when the ith row of sub-pixels is displayed, a difference value T _ COF between the duration of the first change edge of the data signal provided by the P-th data line connected with the source driver chip on the ith flip-chip sub-film and the duration of the first change edge of the data signal provided by the first data line connected with the source driver chip on the ith flip-chip sub-film and the duration of the first change edge of the data signal provided by the P-th data line connected with the source driver chip on the i-1 th flip-chip sub-film and the duration of the first change edge of the data signal provided by the first data line connected with the source driver chip on the ith flip-chip sub-film satisfies the following formula:

T_IC*Q+T_COF*(Q-1)＝T2-T1

11. The display panel according to claim 10, wherein T _ COF is 0 or more and 0.5 ns or less.

12. A display device, comprising: a display panel as claimed in any one of claims 1 to 11.

13. A method of controlling a display panel, arranged to control a display panel as claimed in any one of claims 1 to 11, the method comprising: