CN110690265B - Display substrate, manufacturing method thereof and display device - Google Patents
Display substrate, manufacturing method thereof and display device Download PDFInfo
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- CN110690265B CN110690265B CN201911038883.4A CN201911038883A CN110690265B CN 110690265 B CN110690265 B CN 110690265B CN 201911038883 A CN201911038883 A CN 201911038883A CN 110690265 B CN110690265 B CN 110690265B
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- H—ELECTRICITY
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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Abstract
A display substrate, a manufacturing method thereof and a display device are provided, wherein the display substrate comprises: the liquid crystal display panel comprises a substrate, a plurality of sub-pixels, a plurality of columns of power lines and a data line, wherein the sub-pixels, the plurality of columns of power lines and the data line are arranged on the substrate, and each sub-pixel comprises: a drive circuit; the drive circuit includes: a transistor and a capacitor; the capacitor includes: the first polar plate and the second polar plate are oppositely arranged; the active layer of the transistor is positioned on one side of the second plate of the capacitor close to the substrate, and the power line is positioned on one side of the second plate of the capacitor far away from the substrate; for each sub-pixel, the power line is connected with the second plate of the capacitor and the active layer of the transistor respectively, the second plate of the capacitor of each sub-pixel is connected with the second plate of the capacitor of one adjacent sub-pixel in the same row, and the active layer of the transistor of each sub-pixel is connected with the active layer of the transistor of the other adjacent sub-pixel in the same row. The technical scheme provided by the application can reduce the load of the data line, and then reduce the power consumption of the display substrate and shorten the write-in time of the data signal.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
Background
An Organic Light-Emitting diode (OLED) Display substrate is a Display substrate different from a conventional Liquid Crystal Display (LCD), and has the advantages of active Light emission, good temperature characteristics, low power consumption, fast response, flexibility, ultra-lightness and thinness, low cost, and the like. And thus has become one of the important developments of the new generation of display devices and receives increasing attention.
In order to realize high-frequency driving of the OLED display substrate, a double-data-line OLED display substrate is proposed in the related art, that is, sub-pixels in the same column are connected to two data lines. However, in the OLED display substrate in the related art, the distances between the power connection lines respectively connected to the power lines and the sub-pixels in the same row and the data lines are short, so that the load of the data lines is large, and further, the power consumption of the OLED display substrate is large and the writing time of data signals provided by the data lines is long.
Disclosure of Invention
The application provides a display substrate, a manufacturing method thereof and a display device, which reduce the load of a data line, further reduce the power consumption of the display substrate and shorten the writing time of a data signal.
In a first aspect, the present application provides a display substrate comprising: the liquid crystal display panel comprises a substrate, a plurality of sub-pixels arranged on the substrate, a plurality of columns of power lines and a data line arranged on the same layer as the power lines, wherein each sub-pixel comprises: a drive circuit; the drive circuit includes: a transistor and a capacitor; the capacitor includes: the first polar plate and the second polar plate are oppositely arranged; the active layer of the transistor is positioned on one side of the second plate of the capacitor close to the substrate, and the power line is positioned on one side of the second plate of the capacitor far away from the substrate;
for each sub-pixel, the power line is respectively connected with the second polar plate of the capacitor and the active layer of the transistor, the second polar plate of the capacitor of each sub-pixel is connected with the second polar plate of the capacitor of one adjacent sub-pixel in the same row, and the active layer of the transistor of each sub-pixel is connected with the active layer of the transistor of the other adjacent sub-pixel in the same row.
Alternatively, the active layers of the transistors in adjacent sub-pixels located in the same column are connected to each other.
Optionally, the pixel structures of the adjacent sub-pixels in the same row are symmetrical to each other, and the pixel structure of the sub-pixel in the ith row and the jth column is the same as the pixel structure of the sub-pixel in the (i + 1) th row and the jth +1 column.
Optionally, each pixel comprises: four sub-pixels, the pixel comprising: a first pixel and a second pixel;
in the first pixel, a second polar plate of a capacitor in the ith sub-pixel is connected with a second polar plate of a capacitor in the (i + 1) th sub-pixel, and an active layer of a transistor in the second sub-pixel is connected with an active layer of a transistor in the third sub-pixel;
in the second pixel, the second plate of the capacitor in the second sub-pixel is connected with the second plate of the capacitor in the third sub-pixel, the active layer of the transistor in the ith sub-pixel is connected with the active layer of the transistor in the (i + 1) th sub-pixel, and i is an odd number smaller than 4.
Optionally, the display substrate further comprises: a first insulating layer, a second insulating layer, a third insulating layer, a gate line, a reset signal line, a light emission control signal line, and an initial signal line, which are disposed on a substrate;
the grid line, the reset signal line, the light-emitting control signal line, the first polar plate of the capacitor and the gate electrode of the transistor are arranged on the same layer, the second polar plate of the capacitor and the initial signal line are arranged on the same layer, and the data line, the power line and the source and drain electrodes of the transistor are arranged on the same layer;
the first insulating layer is disposed between an active layer of a transistor and a gate electrode of the transistor, the second insulating layer is disposed between the gate electrode of the transistor and a second plate of the capacitor, and the third insulating layer is disposed between the second plate of the capacitor and the data line.
Optionally, a first via hole is disposed on the third insulating layer;
in each sub-pixel, the orthographic projection of the second plate of the capacitor on the substrate covers the orthographic projection of the first via hole on the substrate, so that the power line is connected with the second plate of the capacitor through the first via hole.
Optionally, the first insulating layer, the second insulating layer and the third insulating layer are provided with second vias;
in each sub-pixel, an overlapping region exists between the orthographic projection of the second via hole on the substrate and the orthographic projection of the active layer on the substrate, and the power line is connected with the active layer of the transistor through the second via hole.
Optionally, the number of the first vias is at least one.
Optionally, the ith column of sub-pixels is connected with the ith column of data lines and the ith column of power lines respectively, i is greater than or equal to 1 and less than or equal to N, and N is the total column number of the sub-pixels;
each column of data lines includes: the first sub data line and the second sub data line in the ith row of data lines are respectively positioned on two sides of the ith row of sub pixels, the ith row of power lines are positioned between the first sub data line and the second sub data line in the ith row of data lines, the first sub data line and the second sub data line in adjacent data lines are arranged in opposite modes, and the adjacent power lines are symmetrical to each other.
Optionally, adjacent sub-pixels in the same column connect different sub-data lines.
In a second aspect, the present application further provides a display device including the above display substrate.
In a third aspect, the present application further provides a method for manufacturing a display substrate, for manufacturing the display substrate, where the method includes:
providing a substrate;
forming a plurality of sub-pixels, a plurality of rows of power lines and data lines arranged on the same layer as the power lines on the substrate; each of the sub-pixels includes: a drive circuit; the drive circuit includes: a transistor and a capacitor; the capacitor includes: the first polar plate and the second polar plate are oppositely arranged; the capacitor includes: the first polar plate and the second polar plate are oppositely arranged; the active layer of the transistor is positioned on one side of the second plate of the capacitor close to the substrate, and the power line is positioned on one side of the second plate of the capacitor far away from the substrate;
for each sub-pixel, the power line is respectively connected with the second plate of the capacitor and the active layer of the transistor, the second plate of the capacitor of each sub-pixel is connected with the second plate of the capacitor of one adjacent sub-pixel in the same row, and the active layer of the transistor of each sub-pixel is connected with the active layer of the transistor of the other adjacent sub-pixel in the same row.
Optionally, the forming a plurality of sub-pixels, a plurality of columns of power lines, and a data line disposed on the same layer as the power lines on the substrate includes:
forming an active layer on a substrate;
forming a first insulating layer on one side of the active layer far away from the substrate;
forming a grid line, a light-emitting control signal line, a reset signal line, a first polar plate of a capacitor and a gate electrode of a transistor on one side of the first insulating layer, which is far away from the substrate;
forming a second insulating layer on one side of the grid line far away from the substrate;
forming an initial signal line and a second plate of the capacitor on one side of the second insulating layer, which is far away from the substrate;
forming a third insulating layer on one side of the initial signal line far away from the substrate;
and forming a data line, a power line and a source-drain electrode of the transistor on one side of the third insulating layer, which is far away from the substrate.
The embodiment of the application provides a display substrate, a manufacturing method thereof and a display device, wherein the display substrate comprises: the liquid crystal display panel comprises a substrate, a plurality of sub-pixels arranged on the substrate, a plurality of columns of power lines and data lines arranged on the same layer with the power lines, wherein each sub-pixel comprises: a drive circuit; the drive circuit includes: a transistor and a capacitor; the capacitor includes: the first polar plate and the second polar plate are oppositely arranged; the active layer of the transistor is positioned on one side of the second plate of the capacitor close to the substrate, and the power line is positioned on one side of the second plate of the capacitor far away from the substrate; for each sub-pixel, the power line is respectively connected with the second polar plate of the capacitor and the active layer of the transistor, the second polar plate of the capacitor of each sub-pixel is connected with the second polar plate of the capacitor of one adjacent sub-pixel in the same row, and the active layer of the transistor of each sub-pixel is connected with the active layer of the transistor of the other adjacent sub-pixel in the same row. The embodiment of the application multiplexes the power signal for the power connecting line transmission power line through the second polar plate of the capacitor and the active layer of the transistor, and the active layer of the transistor is far away from the data line, so that the technical scheme provided by the embodiment of the application increases the distance between part of the power connecting line and the data line, reduces the load of the data line, and further reduces the power consumption of the display substrate and shortens the writing time of the data signal.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the application may be realized and attained by the instrumentalities and combinations particularly pointed out in the written description and claims hereof, as well as the appended drawings.
Drawings
The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.
Fig. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;
FIG. 2 is a top view of a plurality of sub-pixels according to an embodiment of the present disclosure;
FIG. 3 is a side view of a plurality of sub-pixels provided by an embodiment of the present application;
fig. 4 is an equivalent circuit diagram of a driving circuit provided in an embodiment of the present application;
FIG. 5 is a partial top view of a subpixel in a display substrate according to an embodiment of the present application;
FIG. 6 is a top view of another portion of a subpixel in a display substrate according to an embodiment of the present disclosure;
FIG. 7 is a top view of another portion of a subpixel in a display substrate according to an embodiment of the present application;
fig. 8 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the present disclosure;
FIG. 9 is a schematic diagram illustrating an active layer of a display substrate according to an embodiment of the present disclosure;
fig. 10 is a schematic view illustrating a first insulating layer and a first metal layer of a display substrate according to an embodiment of the present disclosure;
fig. 11 is a schematic view illustrating a second insulating layer and a second metal layer of a display substrate according to an embodiment of the disclosure;
fig. 12 is a schematic view illustrating a third insulating layer according to an embodiment of the present disclosure.
Detailed Description
The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.
Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
Unless defined otherwise, technical or scientific terms used in the disclosure of the embodiments of the present invention should have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. The use of "first," "second," and the like in the embodiments of the present invention does not denote any order, quantity, or importance, but rather the terms "first," "second," and the like are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The related art OLED display substrate includes a plurality of sub-pixels, power lines, and data lines. Each sub-pixel includes: the capacitor comprises a first polar plate and a second polar plate which are oppositely arranged, wherein the second polar plate of the capacitor is connected with a power line, the second polar plates of the capacitors of adjacent sub-pixels are mutually connected, and the power line and the data line are arranged on the same layer.
In the OLED display substrate in the related art, the second plates of the capacitors of all the sub-pixels in the same row are multiplexed as the power connection line, so that the power signals provided by the power lines in each sub-pixel are the same, and the display failure of the OLED display substrate is avoided. Specifically, the extending direction of the power connecting line is perpendicular to the extending direction of the data line, but because the overlapping area between the power connecting line and the data line is large, and the distance between the power connecting line and the data line is short, the load of the data line is large, and further the power consumption of the OLED display substrate is large and the writing time of the data signal provided by the data line is long.
In order to solve the above technical problem, embodiments of the present application provide a display substrate, a manufacturing method thereof, and a display device, which are specifically described as follows:
some embodiments of the present application provide a display substrate, fig. 1 is a schematic structural diagram of the display substrate provided in the embodiments of the present application, fig. 2 is a top view of a plurality of sub-pixels provided in the embodiments of the present application, and fig. 3 is a side view of the plurality of sub-pixels provided in the embodiments of the present application, as shown in fig. 1 to 3, the display substrate provided in the embodiments of the present application includes: the liquid crystal display device includes a substrate 10, and a plurality of sub-pixels P, a plurality of columns of power lines VDD and data lines D disposed on the same layer as the power lines VDD on the substrate 10, wherein each sub-pixel P includes: a drive circuit; the drive circuit includes: a transistor and a capacitor, the capacitor comprising: the first plate C1 and the second plate C2 are oppositely arranged, the active layer 20 of the transistor is positioned on the side, close to the substrate 10, of the second plate C2 of the capacitor, and the power line VDD is positioned on the side, far away from the substrate 10, of the second plate C2 of the capacitor.
Specifically, for each sub-pixel, the power line VDD is connected to the second plate C2 of the capacitor and the active layer 20 of the transistor, respectively, the second plate C2 of the capacitor of each sub-pixel is connected to the second plate C2 of the capacitor of one adjacent sub-pixel located in the same row, and the active layer 20 of the transistor of each sub-pixel is connected to the active layer 20 of the transistor of another adjacent sub-pixel located in the same row. Fig. 2 illustrates an example of 8 sub-pixels.
Specifically, as shown in fig. 1, the display substrate in this embodiment includes M rows and N columns of sub-pixels, N columns of data lines D1 to DN, N columns of power lines VDD1 to VDDN, M rows of gate lines G1 to GM, M-1 rows of light emission control signal lines EM1 to EMM-1, M rows of Reset signal lines Reset, and M rows of initial signal lines Vinit, and further includes: a data driver for supplying data signals to the data lines, a scan driver for supplying scan signals to the gate lines, a light emission driver for supplying light emission control signals to the light emission control signal lines, and a timing controller for supplying driving signals to the data driver, the scan driver, and the light emission driver.
Optionally, as can be seen from fig. 1 and fig. 2, the ith column of sub-pixels is connected to the ith column of data lines and the ith column of power lines, and 1 ≦ i ≦ N.
Each column of data lines includes: the first sub data line DOi and the second sub data line DEi in the ith column of data line Di are respectively located at two sides of the ith column of sub-pixels, the ith column of power supply line VDDi is located between the first sub data line DOi and the second sub data line DEi in the ith column of data line Di, and fig. 2 illustrates two rows of sub-pixels before four columns.
Specifically, as shown in fig. 1 and 2, adjacent sub-pixels in the same column are connected to different sub-data lines, that is, if the sub-pixel in the ith row and the jth column is connected to the first sub-data line DOj in the jth column data line, the sub-pixel in the (i + 1) th row and the jth column is connected to the second sub-data line DEj in the jth column data line, and if the sub-pixel in the ith row and the jth column is connected to the second sub-data line DEj in the jth column data line, the sub-pixel in the (i + 1) th row and the jth column is connected to the first sub-data line DOj in the jth column data line.
In this embodiment, the first sub data line and the second sub data line in adjacent data lines are arranged in opposite ways, that is, when the first sub data line DOi of the ith column of data line Di is located at the first side of the ith column of sub-pixels and the second sub data line DEi of the ith column of data line Di is located at the second side of the ith column of sub-pixels, the second sub data line DEi +1 of the (i + 1) th column of data line Di +1 is located at the first side of the (i + 1) th column of sub-pixels, and the first sub data line DOi +1 of the (i + 1) th column of data line Di +1 is located at the second side of the (i + 1) th column of sub-pixels; or when the first sub data line DOi of the ith column data line Di is located at the second side of the ith column of sub-pixels and the second sub data line DEi of the ith column data line Di is located at the first side of the ith column of sub-pixels, the second sub data line DEi +1 of the (i + 1) th column data line Di +1 is located at the second side of the (i + 1) th column of sub-pixels, and the first sub data line DOi +1 of the (i + 1) th column data line Di +1 is located at the first side of the (i + 1) th column of sub-pixels.
Fig. 4 is an equivalent circuit diagram of a driving circuit provided in an embodiment of the present application, and as shown in fig. 4, fig. 4 is a diagram illustrating a driving circuit included in an ith column of sub-pixels and an (i + 1) th column of sub-pixels, the driving circuit provided in the embodiment of the present application has a 7T1C structure, the driving circuit includes a first transistor T1 to a seventh transistor T7 and a capacitor C, where the capacitor C includes a first plate C1 and a second plate C2.
Specifically, the gate electrode of the first transistor T1 is connected to the Reset signal line Reset, the source electrode of the first transistor T1 is connected to the initial signal line Vinit, the drain electrode of the first transistor T1 is connected to the first plate C1 of the capacitor C, the gate electrode of the second transistor T2 is connected to the gate line G, the source electrode of the second transistor T2 is connected to the first plate C1 of the capacitor C, the drain electrode of the second transistor T2 is connected to the drain electrode of the sixth transistor T6, the gate electrode of the third transistor T3 is connected to the first plate C1 of the capacitor C, the source electrode of the third transistor T3 is connected to the drain electrode of the fourth transistor T4, the drain electrode of the third transistor T3 is connected to the drain electrode of the sixth transistor T6, the gate electrode of the fourth transistor T4 is connected to the gate line G, the source electrode of the fourth transistor T4 is connected to the data line D, and the gate electrode of the fifth transistor T5 is connected to the emission control signal line EM, a source electrode of the fifth transistor T5 is connected to a power supply line VDD, a drain electrode of the fifth transistor T5 is connected to a source electrode of the third transistor T3, a gate electrode of the sixth transistor T6 is connected to the emission control signal line EM, a drain electrode of the sixth transistor T6 is connected to an anode of the light emitting device, a gate electrode of the seventh transistor T7 is connected to a Reset signal line Reset, a source electrode of the seventh transistor T7 is connected to the initial signal line Vinit, a drain electrode of the seventh transistor T7 is connected to an anode of the light emitting device, the second plate C2 of the capacitor is connected to the power supply line VDD, and a cathode of the light emitting device OLED is connected to the low-level power supply terminal VSS.
The third transistor T3 is a driving transistor, and other transistors except the third transistor T3 are switching transistors, and the first transistor T1 to the seventh transistor T7 provided in this embodiment may all be P-type transistors or N-type transistors, which is not limited in this embodiment of the present invention.
Specifically, the general operation process of the driving circuit includes: the light emitting device comprises a driving circuit, a reset signal line, a gate line, a light emitting control signal line and a light emitting device, wherein the driving circuit comprises a driving circuit, the light emitting control signal line comprises a data line and a data line, the data line comprises a data line, the data line and the light emitting control signal line comprises a data line.
Specifically, as shown in fig. 2 and fig. 3, the display substrate provided in the embodiment of the present application further includes: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a gate line G, a Reset signal line Reset, a light emission control signal line EM, and an initial signal line Vinit sequentially disposed on the substrate 10.
The gate line G, the Reset signal line Reset, the emission control signal line EM, the first electrode plate C1 of the capacitor, and the gate electrode of the transistor are disposed in the same layer, the second electrode plate C2 of the capacitor and the initial signal line Vinit are disposed in the same layer, and the data line D, the power supply VDD line, and the source/drain electrode of the transistor are disposed in the same layer.
Wherein the first insulating layer 11 is disposed between the active layer 20 of the transistor and the gate electrode of the transistor, the second insulating layer 12 is disposed between the gate electrode of the transistor and the second plate C2 of the capacitor, and the third insulating layer 13 is disposed between the second plate C2 of the capacitor and the data line.
Alternatively, the base 10 may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass, metal sheet; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.
Optionally, the gate electrode of the transistor, the source/drain electrode of the transistor, the data line D, and the power line VDD are all made of metal, for example, metal materials such as silver, aluminum, or copper may be used, which is not limited in this embodiment of the present invention.
Optionally, the active layer 20 is made of polysilicon, which is not limited in this embodiment.
According to the embodiment of the application, the power signals provided by the power lines of all the sub-pixels in the same row are ensured to be the same through the second plates of the capacitors connected with each other and the active layers of the transistors connected with each other, so that poor display of the display substrate is avoided, and the display effect of the display substrate is ensured.
The display substrate provided by the embodiment of the application comprises: the liquid crystal display panel comprises a substrate, a plurality of sub-pixels arranged on the substrate, a plurality of columns of power lines and data lines arranged on the same layer with the power lines, wherein each sub-pixel comprises: a drive circuit; the drive circuit includes: a transistor and a capacitor; the capacitor includes: the first polar plate and the second polar plate are oppositely arranged; the active layer of the transistor is positioned on one side of the second plate of the capacitor close to the substrate, and the power line is positioned on one side of the second plate of the capacitor far away from the substrate; for each sub-pixel, the power line is respectively connected with the second polar plate of the capacitor and the active layer of the transistor, the second polar plate of the capacitor of each sub-pixel is connected with the second polar plate of the capacitor of one adjacent sub-pixel in the same row, and the active layer of the transistor of each sub-pixel is connected with the active layer of the transistor of the other adjacent sub-pixel in the same row. The embodiment of the application multiplexes the power signal for the power connecting line transmission power line through the second polar plate of the capacitor and the active layer of the transistor, and the distance between the active layer of the transistor and the data line is longer than the distance between the second polar plate of the capacitor and the data line, so that the technical scheme provided by the application increases the distance between part of the power connecting line and the data line, reduces the load of the data line, further reduces the power consumption of the display substrate and shortens the writing time of the data signal.
Alternatively, in the present embodiment, as shown in fig. 2, the active layers 20 of adjacent sub-pixels located in the same column are connected to each other.
Alternatively, as shown in fig. 2, the pixel structure of the sub-pixel located in the ith row and the jth column is the same as the pixel structure of the sub-pixel located in the (i + 1) th row and the (j + 1) th column.
As shown in fig. 2, adjacent power lines are symmetrical to each other, and specifically, the i-th column power line VDDi and the i + 1-th column power line VDDi + 1 are arranged symmetrically along the extending direction of the data line. In the embodiment of the present application, the power line VDD is a zigzag.
Specifically, as shown in fig. 2, in the display substrate provided in the embodiment of the present application, each pixel includes: four sub-pixels, the pixel includes: a first pixel and a second pixel.
In the first pixel, the second plate of the capacitor in the ith sub-pixel is connected with the second plate of the capacitor in the (i + 1) th sub-pixel, the active layer of the transistor in the ith sub-pixel is disconnected from the active layer of the transistor in the (i + 1) th sub-pixel, the active layer of the transistor in the second sub-pixel is connected with the active layer of the transistor in the third sub-pixel, and the second plate of the capacitor in the second sub-pixel is disconnected from the second plate of the capacitor in the third sub-pixel.
In the second pixel, the second plate of the capacitor in the second sub-pixel is connected with the second plate of the capacitor in the third sub-pixel, the active layer of the transistor in the second sub-pixel is disconnected from the active layer of the transistor in the third sub-pixel, the active layer of the transistor in the ith sub-pixel is connected with the active layer of the transistor in the (i + 1) th sub-pixel, and the second plate of the capacitor in the ith sub-pixel is disconnected from the second plate of the capacitor in the (i + 1) th sub-pixel.
Wherein i is an odd number less than 4.
It should be noted that fig. 2 illustrates 2 pixels arranged along a column direction as an example, where an upper pixel is a first pixel, and a lower pixel is a second pixel, which is not limited in this application, and the pixel structures of adjacent sub-pixels are symmetrical in this application, so in the display substrate provided in this application, the first pixel is arranged between the adjacent second pixels, and the second pixel is arranged between the adjacent first pixels.
Fig. 5 is a partial top view of a subpixel in a display substrate provided in an embodiment of the present application, fig. 6 is another partial top view of the subpixel in the display substrate provided in the embodiment of the present application, fig. 7 is another partial top view of the subpixel in the display substrate provided in the embodiment of the present application, and it should be noted that the display substrate provided in fig. 5 does not include a power line, a data line, and a source/drain electrode of a transistor, the display substrate provided in fig. 6 only includes a film layer where a second electrode of a capacitor is located and a film layer where the data line is located, and the display substrate provided in fig. 7 only includes a film layer where an active layer of a transistor and a data line are located, as shown in fig. 5, in the display substrate provided in the embodiment of the present application, a first via hole V1 is provided in a third insulating layer.
Specifically, referring to fig. 5 and 6, in each sub-pixel, the orthographic projection of the second plate C2 of the capacitor on the substrate covers the orthographic projection of the first via V1 on the substrate, and the power line is connected with the second plate C2 of the capacitor through the first via V1.
Optionally, the number of the first vias V1 is at least one. In particular, the greater the number of first vias V1, the better the conductivity between the power line and the second plate of the capacitor.
Optionally, as shown in fig. 5, in the display substrate provided in the embodiment of the present application, the first insulating layer, the second insulating layer, and the third insulating layer are provided with a second via hole V2 therein.
Specifically, in each sub-pixel, in conjunction with fig. 5 and 7, there is an overlapping region between the orthographic projection of the second via V2 on the substrate and the orthographic projection of the active layer 20 on the substrate, and the power supply line is connected to the active layer 20 of the transistor through the second via V2.
Optionally, the number of the second vias V2 is at least one, and the larger the number of vias, the better the conductivity of the components connected by the vias.
Fig. 5 to 7 illustrate two first vias V1 and one second via V2, which is not limited in this embodiment of the present application.
Based on the same inventive concept, an embodiment of the present application further provides a manufacturing method of a display substrate, which is used for manufacturing the display substrate provided in the foregoing embodiment, and fig. 8 is a flowchart of the manufacturing method of the display substrate provided in the embodiment of the present application, and as shown in fig. 8, the manufacturing method of the display substrate provided in the embodiment of the present application specifically includes the following steps:
Each sub-pixel includes: a drive circuit; the drive circuit includes: a transistor and a capacitor; the capacitor includes: the first polar plate and the second polar plate are oppositely arranged; the capacitor includes: the first polar plate and the second polar plate are oppositely arranged; the active layer of the transistor is positioned on one side of the second plate of the capacitor close to the substrate, and the power line is positioned on one side of the second plate of the capacitor far away from the substrate;
for each sub-pixel, the power line is respectively connected with the second polar plate of the capacitor and the active layer of the transistor, the second polar plate of the capacitor of each sub-pixel is connected with the second polar plate of the capacitor of one adjacent sub-pixel in the same row, and the active layer of the transistor of each sub-pixel is connected with the active layer of the transistor of the other adjacent sub-pixel in the same row.
The manufacturing method of the display substrate provided by the embodiment of the application is used for manufacturing the display substrate provided by the embodiment, and the implementation principle and the implementation effect are similar, and are not repeated here.
Take the case of forming two pixels disposed along the extending direction of the data line, wherein each pixel includes four sub-pixels, for convenience of description, the film layer where the first electrode plate of the capacitor is located is referred to as a first metal layer, the film layer where the second electrode plate of the capacitor is located is referred to as a second metal layer, the film layer where the power line is located is referred to as a third metal layer, fig. 9 is a schematic view illustrating an active layer of a display substrate according to an embodiment of the present disclosure, fig. 10 is a schematic view illustrating a first insulating layer and a first metal layer of a display substrate according to an embodiment of the present disclosure, FIG. 11 is a schematic diagram illustrating a second insulating layer and a second metal layer of a display substrate according to an embodiment of the present disclosure, fig. 12 is a schematic view illustrating a manufacturing method of a third insulating layer according to an embodiment of the present application, and with reference to fig. 9 to fig. 12, the following further describes the manufacturing method of a display substrate according to the embodiment of the present application, and specifically describes the following:
step 101 is to provide a substrate 10, and form an active layer 20 on the substrate, as shown in fig. 9.
Step 102 is to form a first insulating layer on the active layer 20, and form a first metal layer 30 on the first insulating layer, as shown in fig. 10.
Wherein the first metal layer includes: a gate line G, a Reset signal line Reset, a light emission control signal line EM, and a first plate C1 of a capacitor.
Step 103, forming a second insulating layer on the first metal layer, and forming a second metal layer on the second insulating layer, as shown in fig. 11.
Wherein the second metal layer includes: an initial signal line Vinit and a second plate C2 of the capacitor.
Step 104, forming a third insulating layer on the second metal layer, as shown in fig. 12.
Specifically, the third insulating layer is provided with a first via hole exposing the second plate of the capacitor, and the first insulating layer, the second insulating layer and the third insulating layer further comprise a second via hole exposing the active layer.
Step 105, a third metal layer is formed on the third insulating layer, as shown in fig. 2.
The third metal layer comprises a data line D, a power line VDD and a source drain electrode of the transistor.
Based on the same inventive concept, the embodiment of the present application further provides a display device, wherein the display device includes: a display substrate.
Optionally, the display substrate is an OLED display substrate.
Specifically, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator, etc., but the embodiment of the present invention is not limited thereto.
The display substrate is provided in the foregoing embodiments, and the implementation principle and the implementation effect thereof are similar, and are not described herein again.
In the drawings used to describe embodiments of the invention, the thickness and dimensions of layers or microstructures are exaggerated for clarity. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (13)
1. A display substrate, comprising: the liquid crystal display panel comprises a substrate, a plurality of sub-pixels arranged on the substrate, a plurality of columns of power lines and data lines arranged on the same layer with the power lines, wherein each sub-pixel comprises: a drive circuit; the drive circuit includes: a transistor and a capacitor; the capacitor includes: the first polar plate and the second polar plate are oppositely arranged; the active layer of the transistor is positioned on one side of the second plate of the capacitor close to the substrate, and the power line is positioned on one side of the second plate of the capacitor far away from the substrate;
for each sub-pixel, the power line is respectively connected with the second polar plate of the capacitor and the active layer of the transistor, the second polar plate of the capacitor of each sub-pixel is connected with the second polar plate of the capacitor of one adjacent sub-pixel in the same row, and the active layer of the transistor of each sub-pixel is connected with the active layer of the transistor of the other adjacent sub-pixel in the same row.
2. The display substrate of claim 1, wherein the active layers of the transistors in adjacent sub-pixels in the same column are connected to each other.
3. The display substrate of claim 1, wherein the pixel structures of the adjacent sub-pixels in the same row are symmetrical to each other, and the pixel structure of the sub-pixel in the ith row and the jth column is the same as the pixel structure of the sub-pixel in the (i + 1) th row and the (j + 1) th column.
4. The display substrate of claim 1, wherein each pixel comprises: four sub-pixels, the pixel comprising: a first pixel and a second pixel;
in the first pixel, a second polar plate of a capacitor in the ith sub-pixel is connected with a second polar plate of a capacitor in the (i + 1) th sub-pixel, and an active layer of a transistor in the second sub-pixel is connected with an active layer of a transistor in the third sub-pixel;
in the second pixel, the second plate of the capacitor in the second sub-pixel is connected with the second plate of the capacitor in the third sub-pixel, the active layer of the transistor in the ith sub-pixel is connected with the active layer of the transistor in the (i + 1) th sub-pixel, and i is an odd number smaller than 4.
5. The display substrate of claim 1, further comprising: a first insulating layer, a second insulating layer, a third insulating layer, a gate line, a reset signal line, a light emission control signal line, and an initial signal line, which are disposed on a substrate;
the grid line, the reset signal line, the light-emitting control signal line, the first polar plate of the capacitor and the gate electrode of the transistor are arranged on the same layer, the second polar plate of the capacitor and the initial signal line are arranged on the same layer, and the data line, the power line and the source and drain electrodes of the transistor are arranged on the same layer;
the first insulating layer is disposed between the active layer of the transistor and the gate electrode of the transistor, the second insulating layer is disposed between the gate electrode of the transistor and the second plate of the capacitor, and the third insulating layer is disposed between the second plate of the capacitor and the data line.
6. The display substrate according to claim 5, wherein the third insulating layer is provided with a first via hole;
in each sub-pixel, the orthographic projection of the second plate of the capacitor on the substrate covers the orthographic projection of the first via hole on the substrate, so that the power line is connected with the second plate of the capacitor through the first via hole.
7. The display substrate according to claim 5, wherein the first insulating layer, the second insulating layer, and the third insulating layer are provided with a second via hole;
in each sub-pixel, an overlapping region exists between the orthographic projection of the second via hole on the substrate and the orthographic projection of the active layer on the substrate, and the power line is connected with the active layer of the transistor through the second via hole.
8. The display substrate of claim 6, wherein the number of the first vias is at least one.
9. The display substrate according to claim 1, wherein the ith column of sub-pixels is connected with the ith column of data lines and the ith column of power lines respectively, i is more than or equal to 1 and less than or equal to N, and N is the total column number of the sub-pixels;
each column of data lines includes: the first sub data line and the second sub data line in the ith column of data lines are respectively positioned at two sides of the ith column of sub pixels, the ith column of power lines are positioned between the first sub data line and the second sub data line in the ith column of data lines, the arrangement modes of the first sub data line and the second sub data line in adjacent data lines are opposite, and the adjacent power lines are symmetrical.
10. The display substrate of claim 9, wherein adjacent sub-pixels in the same column are connected to different sub-data lines.
11. A display device comprising the display substrate according to any one of claims 1 to 10.
12. A method for manufacturing a display substrate, the method being used for manufacturing the display substrate according to any one of claims 1 to 10, the method comprising:
providing a substrate;
forming a plurality of sub-pixels, a plurality of rows of power lines and data lines arranged on the same layer as the power lines on the substrate; each of the sub-pixels includes: a drive circuit; the drive circuit includes: a transistor and a capacitor; the capacitor includes: the first polar plate and the second polar plate are oppositely arranged; the active layer of the transistor is positioned on one side of the second plate of the capacitor close to the substrate, and the power line is positioned on one side of the second plate of the capacitor far away from the substrate;
for each sub-pixel, the power line is respectively connected with the second plate of the capacitor and the active layer of the transistor, the second plate of the capacitor of each sub-pixel is connected with the second plate of the capacitor of one adjacent sub-pixel in the same row, and the active layer of the transistor of each sub-pixel is connected with the active layer of the transistor of the other adjacent sub-pixel in the same row.
13. The method of claim 12, wherein forming a plurality of sub-pixels, a plurality of columns of power lines, and data lines on the same layer as the power lines on the substrate comprises:
forming an active layer on a substrate;
forming a first insulating layer on one side of the active layer, which is far away from the substrate;
forming a grid line, a light-emitting control signal line, a reset signal line, a first polar plate of a capacitor and a grid electrode of a transistor on one side of the first insulating layer, which is far away from the substrate;
forming a second insulating layer on one side of the grid line far away from the substrate;
forming an initial signal line and a second plate of the capacitor on one side of the second insulating layer, which is far away from the substrate;
forming a third insulating layer on one side of the initial signal line far away from the substrate;
and forming a data line, a power line and a source drain electrode of the transistor on one side of the third insulating layer, which is far away from the substrate.
Priority Applications (14)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111290594.0A CN114023801A (en) | 2019-10-29 | 2019-10-29 | Display substrate, manufacturing method thereof and display device |
| CN201911038883.4A CN110690265B (en) | 2019-10-29 | 2019-10-29 | Display substrate, manufacturing method thereof and display device |
| CN202080002859.XA CN115605999A (en) | 2019-10-29 | 2020-10-29 | Display substrate, manufacturing method thereof and display device |
| AU2020376100A AU2020376100B2 (en) | 2019-10-29 | 2020-10-29 | Display substrate and method for manufacturing same, and display apparatus |
| RU2021119000A RU2770179C1 (en) | 2019-10-29 | 2020-10-29 | Display substrate, its manufacturing method and display device |
| MX2021008023A MX2021008023A (en) | 2019-10-29 | 2020-10-29 | Display substrate and method for manufacturing same, and display apparatus. |
| KR1020207036474A KR102476703B1 (en) | 2019-10-29 | 2020-10-29 | Display substrate and its manufacturing method, display device |
| EP20824415.2A EP4053903A4 (en) | 2019-10-29 | 2020-10-29 | Display substrate and method for manufacturing same, and display apparatus |
| US17/256,006 US12041826B2 (en) | 2019-10-29 | 2020-10-29 | Display substrate and manufacturing method thereof, and display apparatus |
| JP2020571364A JP2022554043A (en) | 2019-10-29 | 2020-10-29 | DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE |
| CN202111530233.9A CN114050179A (en) | 2019-10-29 | 2020-10-29 | Display substrate and display device |
| BR112021012544-2A BR112021012544A2 (en) | 2019-10-29 | 2020-10-29 | DISPLAY SUBSTRATE AND MANUFACTURING METHOD, AND DISPLAY DEVICES |
| PCT/CN2020/124967 WO2021083298A1 (en) | 2019-10-29 | 2020-10-29 | Display substrate and method for manufacturing same, and display apparatus |
| US17/489,771 US20220328600A1 (en) | 2019-10-29 | 2021-09-29 | Display Substrate and Manufacturing Method Thereof, and Display Apparatus |
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| CN201911038883.4A CN110690265B (en) | 2019-10-29 | 2019-10-29 | Display substrate, manufacturing method thereof and display device |
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| CN202111290594.0A Division CN114023801A (en) | 2019-10-29 | 2019-10-29 | Display substrate, manufacturing method thereof and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115605999A (en) * | 2019-10-29 | 2023-01-13 | 京东方科技集团股份有限公司（Cn） | Display substrate, manufacturing method thereof and display device |
| CN113096596A (en) * | 2020-01-08 | 2021-07-09 | 京东方科技集团股份有限公司 | Display substrate, driving method thereof and display device |
| CN114080688A (en) * | 2020-03-25 | 2022-02-22 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| JP7525525B2 (en) * | 2020-05-06 | 2024-07-30 | 京東方科技集團股▲ふん▼有限公司 | Display substrate, driving method thereof, and display device |
| CN111474790A (en) * | 2020-05-14 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
| CN113823657A (en) * | 2020-06-18 | 2021-12-21 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN111834292B (en) * | 2020-07-28 | 2023-10-10 | 合肥京东方卓印科技有限公司 | Display substrate, manufacturing method thereof, display panel and display device |
| US20220320225A1 (en) * | 2020-08-31 | 2022-10-06 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate and method for manufacturing the same, and display device |
| US12101972B2 (en) | 2020-12-15 | 2024-09-24 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate and display device |
| KR20220092134A (en) * | 2020-12-24 | 2022-07-01 | 엘지디스플레이 주식회사 | Display device |
| WO2022133971A1 (en) * | 2020-12-25 | 2022-06-30 | Boe Technology Group Co., Ltd. | Array substrate and display apparatus |
| WO2022165831A1 (en) * | 2021-02-08 | 2022-08-11 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN116097924A (en) * | 2021-03-11 | 2023-05-09 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device thereof |
| CN113075826B (en) * | 2021-03-16 | 2022-07-29 | Tcl华星光电技术有限公司 | Display panel and display device |
| CN113450715B (en) * | 2021-06-25 | 2022-10-28 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display device |
| KR20230013949A (en) * | 2021-07-20 | 2023-01-27 | 엘지디스플레이 주식회사 | Display panel, display device including same, and driving method thereof |
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