CN109190419B - Key encryption circuit and method - Google Patents
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- CN109190419B CN109190419B CN201811021766.2A CN201811021766A CN109190419B CN 109190419 B CN109190419 B CN 109190419B CN 201811021766 A CN201811021766 A CN 201811021766A CN 109190419 B CN109190419 B CN 109190419B
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- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/82—Protecting input, output or interconnection devices
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Abstract
The invention discloses a key encryption circuit and a key encryption method, wherein the key encryption circuit comprises an MCU module, a key module and an inverting module, and the MCU module outputs a random signal to the inverting module; judging the data content of the random signal and the data content of the feedback signal, and measuring the pulse width of the random signal and the pulse width of the feedback signal; when the data content of the feedback signal is judged to be the inverted data of the data content of the random signal, and the pulse width of the random signal is consistent with the pulse width of the feedback signal; the pressing of the key module takes effect; the negation module performs data negation on data content of the random signal to generate a feedback signal; when the key module is pressed, the key module is conducted, and a feedback signal is transmitted to the MCU module. The invention can greatly improve the reliability and stability of key action identification by a double encryption mode of the content of the feedback signal and the pulse width of the signal.
Description
Technical Field
The invention relates to the technical field of key circuits, in particular to a key encryption circuit and a key encryption method.
Background
In the prior art, a key circuit is widely applied to the field of circuit design. The common key circuit simply detects the high-low level change generated by the opening or closing of the key through the GPIO of the MCU. In some occasions with higher safety requirements, such as an exit switch of an access controller, a back plate key of an intelligent lock and the like, illegal persons can easily illegally open facilities such as the access control and the like through simple simulation of high and low levels of the key. Furthermore, a device called tesla coil is available in the market, which can illegally interfere with the key of the back plate of the intelligent lock to complete the door opening.
Based on the common key circuit, the anti-interference performance and the safety are poor, and the application of the key circuit with high safety requirements cannot be met. Even if some simple measures (such as shielding) are added, the application requirements of the key circuit in high-safety occasions cannot be met.
Disclosure of Invention
This patent has proposed a button encryption circuit and method in order to solve the poor problem of ordinary button circuit interference immunity security to greatly improve button circuit interference immunity and security level.
In order to achieve the purpose, the invention provides a key encryption circuit which comprises an MCU module, a key module and an inverting module, wherein the input end of the MCU module is connected with one end of the key module, the output end of the MCU module is connected with the inverting module, and the other end of the key module is also connected with the inverting module;
the MCU module is used for periodically and regularly outputting a random signal to the negation module; the device is also used for judging the data content of the random signal and the data content of the feedback signal and measuring the pulse width of the random signal and the pulse width of the feedback signal; when the data content of the feedback signal is judged to be the inverted data of the data content of the random signal, and the pulse width of the random signal is consistent with the pulse width of the feedback signal; the pressing of the key module takes effect;
the negation module is used for performing data negation on data content of the random signal to generate a feedback signal;
the key module is used for conducting when pressed and transmitting a feedback signal to the MCU module.
The invention has the beneficial effects that: through the double encryption mode of the content of the feedback signal and the pulse width of the signal, the reliability and the stability of the key action identification can be greatly improved.
Further, the data content of the random signal is a data header, a middle data and a data tail in sequence, and the data content of the feedback signal is the inverted data content of the data header, the middle data and the data tail in sequence; wherein the intermediate number is a systematic pseudorandom code generation;
the pulse width of the random signal is generated by a systematic pseudo random code.
Further, the MCU module comprises an MCU, a first filtering unit and a reset power-on unit, wherein the first filtering unit is respectively connected with the MCU and is also connected with a power supply VCC; the first filtering unit is used for filtering the MCU access power supply signal;
the reset power-on unit is connected with the MCU and also connected with a power supply VCC; and the reset power-on unit is used for controlling the MCU to reset power-on operation.
The beneficial effects of the further scheme are as follows: the first filtering unit can ensure that a power supply signal input by the MCU is clean and stable; the reset power-on unit can ensure that the MCU is reliably reset and powered on to work.
Further, the first filtering unit comprises a capacitor C1, a capacitor C3, a capacitor C4, a capacitor C8 and a capacitor C9, and the VCORE pin of the MCU is grounded through the capacitor C1;
one end of the capacitor C3 is connected with a VDDA pin of the MCU, and the other end of the capacitor C3 is grounded; the VDDA pin of the MCU is also connected with a power supply VCC; the capacitor C4 is connected in parallel with the capacitor C3;
one end of the capacitor C8 is connected with a VDD pin of the MCU, and the other end of the capacitor C8 is grounded; the VDD pin of the MCU is also connected with a power supply VCC; the capacitor C9 is connected in parallel with the capacitor C8.
The beneficial effects of the further scheme are as follows: the capacitor C1, the capacitor C3, the capacitor C4, the capacitor C8 and the capacitor C9 are coordinated to operate, so that power signals input by the MCU can be filtered, and the cleanness and stability of the power signals input by the MCU are guaranteed.
Further, the reset power-on unit comprises a capacitor C2, a resistor R4 and a diode D1, one end of the capacitor C2 is grounded, the other end of the capacitor C2 is connected with a RESETB pin of the MCU, the cathode of the diode D1 is connected to a power supply VCC, and the anode of the diode D1 is connected with the RESETB pin of the MCU; the resistor R4 is connected in parallel with the diode D1.
The beneficial effects of the further scheme are as follows: the capacitor C2, the resistor R4 and the diode D1 work in a coordinated mode, and therefore reliable resetting and power-on work of the MCU are guaranteed.
Further, the negation module comprises a triode Q1, a resistor R5 and a resistor R6, the base electrode of the triode Q1 is connected with the PA09 pin of the MCU through the resistor R5, the collector electrode of the triode Q1 is connected with the key module, and the emitter electrode of the triode Q1 is grounded; one end of the resistor R6 is connected with the emitter of the triode Q1, and the other end is connected with the base of the triode Q1.
The beneficial effects of the further scheme are as follows: the MCU controls the on or off state of the triode or the MOS tube Q1 through a PA09 pin, so that the on or off relation between one end of the key K1, one end of the key K2 and one end of the key K3 of the key unit and a ground signal is controlled, and the stability and the safety are improved.
Furthermore, the key module comprises a key unit, a second filtering unit and a pull-up unit, the key unit is respectively connected with the MCU and the negation module, and the second filtering unit and the pull-up unit are both connected with the key unit;
the key unit is used for pressing, generating a feedback signal and transmitting the feedback signal to the MCU; the second filtering unit is used for filtering the feedback signal; the pull-up unit is used for pulling up the current of the circuit between the key unit and the MCU and is matched with the negation module to conduct signal data negation.
The beneficial effects of the further scheme are as follows: the key unit can enable the corresponding signal line to be in a conducting or disconnecting state in a physical pressing mode; the second filtering unit filters the feedback signal, so that part of clutter signal interference can be filtered; the pull-up unit ensures that the GPIO input port of the MCU is in an effective and reliable level state, and ensures the accuracy of the feedback signal.
Further, the key unit comprises a key K1, a key K2 and a key K3, wherein one end of the key K1 is connected with a pin PA14 of the MCU, and the other end of the key K1 is connected with a collector of the triode Q1; one end of the key K2 is connected with a PA13 pin of the MCU, and the other end of the key K2 is connected with a collector of the triode Q1; one end of the key K3 is connected with a PA12 pin of the MCU, and the other end of the key K3 is connected with a collector of the triode Q1.
The beneficial effects of the further scheme are as follows: the key K1, the key K2 and the key K3 are pressed in a physical pressing mode, and corresponding signal lines can be in a conducting or disconnecting state through the coordinated operation of the MCU module and the negation module.
Further, the second filtering unit comprises capacitors C5-C7, one end of the capacitor C7 is connected with a PA14 pin of the MCU, and the other end of the capacitor C7 is grounded; one end of the capacitor C6 is connected with a PA13 pin of the MCU, and the other end of the capacitor C6 is grounded; one end of the capacitor C5 is connected with a PA12 pin of the MCU, and the other end of the capacitor C5 is grounded;
the pull-up unit comprises a resistor R1-a resistor R3, one end of the resistor R1 is connected to a power supply VCC, and the other end of the resistor R1 is connected with a PA14 pin of the MCU; one end of the resistor R2 is connected to a power supply VCC, and the other end of the resistor R2 is connected with a PA13 pin of the MCU; one end of the resistor R3 is connected to a power supply VCC, and the other end of the resistor R3 is connected to a PA12 pin of the MCU.
The beneficial effects of the further scheme are as follows: the capacitors C5 to C7 filter the feedback signals, so that part of clutter signal interference can be filtered; the resistor R1 to the resistor R3 ensure that the MCU input GPIO port is in an effective and reliable level state, and ensure the accuracy of the feedback signal.
In order to achieve the above object, the present invention further provides a key encryption method, including the following steps:
the method comprises the following steps that 1, an MCU module periodically outputs random signals to an negation module at regular time, and the negation module performs data negation on data contents of the random signals to generate feedback signals;
The invention has the beneficial effects that: through the double encryption mode of the content of the feedback signal and the pulse width of the signal, the reliability and the stability of the key action identification can be greatly improved.
Drawings
FIG. 1 is a block diagram of a key encryption circuit according to the present invention;
FIG. 2 is a schematic circuit diagram of a key encryption circuit according to the present invention.
The main element symbols are as follows:
1.MCU module, 2, button module, 3, the module of negating.
Detailed Description
In order to more clearly describe the present invention, the present invention will be further described with reference to the accompanying drawings.
Example 1:
referring to fig. 1-2, the key encryption circuit provided by the invention includes an MCU module 1, a key module 2 and an inverting module 3, wherein an input end of the MCU module 1 is connected to one end of the key module 2, an output end of the MCU module 1 is connected to the inverting module 3, and the other end of the key module 2 is further connected to the inverting module 3;
the MCU module 1 is used for periodically and regularly outputting a random signal to the negation module 3; the device is also used for judging the data content of the random signal and the data content of the feedback signal and measuring the pulse width of the random signal and the pulse width of the feedback signal; when the data content of the feedback signal is judged to be the inverted data of the data content of the random signal, and the pulse width of the random signal is consistent with the pulse width of the feedback signal; the pressing of the key module 2 takes effect;
the negation module 3 is used for performing data negation on data content of the random signal to generate a feedback signal;
the key module 2 is used for conducting when pressed, and transmitting a feedback signal to the MCU module 1.
The MCU module 1 is customized into a Watchdog (WDT) timing wake-up mode, and is in a low-power-consumption sleep state at ordinary times, so that the system can keep extremely low power consumption, several uAs or even lower; meanwhile, the MCU module 1 is awakened to be in a normal working state periodically and regularly through a Watchdog (WDT), for example, once in 50ms, and the MCU module 1 operates; and after the operation is finished, the system enters the low-power-consumption dormant state again, and the operation is repeated, so that the system can accurately operate, and meanwhile, the extremely low power consumption level is kept.
When the MCU module 1 is in the wake-up mode, the MCU module 1 outputs a random signal to the negation module 3; the negation module 3 performs data negation on the data content of the random signal to generate a feedback signal; meanwhile, when the key module is pressed, the feedback signal is transmitted to the MCU module 1, the MCU module 1 judges the data content of the random signal and the data content of the feedback signal, the data content of the random signal is a data head, a middle number and a data tail in sequence, and if the random signal is AA, XX, XX,55 (hexadecimal), the data content of the feedback signal received by the MCU module 1 is 55, XX, XX, AA; wherein the intermediate number is a systematic pseudorandom code generation; when the MCU module 1 judges that the data content of the feedback signal is the negation data of the data content of the random signal, the negation data is used as one of the conditions for controlling the pressing of the key module 2 to take effect;
the data type and format specification takes "AA, XX, 55" as an example, the "AA" is a data head, the "55" is a data tail, and the data head and the data tail can be changed according to actual needs and are not necessarily fixed; the 'XX, XX' is intermediate data, which can be two bits, or one or several bits, and is determined according to actual needs, and the intermediate data can be generated by program pseudo random code, and each time the data are different, so as to prevent the illegal analog key with the data format from being forged after the data are illegally intercepted;
meanwhile, the MCU module 1 also detects the pulse width of the random signal, the signal waveform represents low level by binary ' 0 ', 1 ' represents high level, the pulse width of the random signal can be generated by a system pseudo-random code, the pulse width of each time is different, the pulse width of the random signal detected by the MCU module 1 is consistent with the pulse width of the feedback signal, and the data content of the feedback signal is judged to be the inverted data of the data content of the random signal; the MCU module 1 controls the press of the key module 2 to take effect; the problem of key false identification caused by illegal forged data can be effectively prevented by measuring the pulse width of the feedback signal;
according to the technical scheme, the reliability and the stability of key action identification can be greatly improved through a double encryption mode of the content of the feedback signal and the pulse width of the signal. The condition of illegal simulation of high and low level states of the keys or the condition of achieving key misoperation through an external disturber (such as a Tesla coil) cannot occur.
In the above embodiment, the MCU module 1 includes an MCU, a first filtering unit and a reset power-on unit, where the first filtering unit is connected to the MCU and also connected to a power VCC; the first filtering unit is used for filtering the MCU access power supply signal;
the reset power-on unit is connected with the MCU and also connected with a power supply VCC; and the reset power-on unit is used for controlling the MCU to reset power-on operation.
The MCU is used for generating a random signal, judging whether the content of the random signal corresponds to the content of the feedback signal or not and detecting the pulse width of the feedback signal; when the content of the random signal and the content of the feedback signal are in inverse correspondence, and the pulse widths of the detected random signal and the detected feedback signal are consistent, a conducting signal is generated and transmitted to the inverse module 3;
the first filtering unit can ensure that a power supply signal input by the MCU is clean and stable; the reset power-on unit can ensure that the MCU is reliably reset and powered on to work.
In the above embodiment, the first filtering unit includes a capacitor C1, a capacitor C3, a capacitor C4, a capacitor C8 and a capacitor C9, and the VCORE pin of the MCU is grounded via the capacitor C1;
one end of the capacitor C3 is connected with a VDDA pin of the MCU, and the other end of the capacitor C3 is grounded; the VDDA pin of the MCU is also connected with a power supply VCC; the capacitor C4 is connected in parallel with the capacitor C3;
one end of the capacitor C8 is connected with a VDD pin of the MCU, and the other end of the capacitor C8 is grounded; the VDD pin of the MCU is also connected with a power supply VCC; the capacitor C9 is connected in parallel with the capacitor C8.
The capacitor C1, the capacitor C3, the capacitor C4, the capacitor C8 and the capacitor C9 are coordinated to operate, so that power signals input by the MCU can be filtered, and the cleanness and stability of the power signals input by the MCU are guaranteed.
In the above embodiment, the reset power-on unit includes a capacitor C2, a resistor R4, and a diode D1, one end of the capacitor C2 is grounded, the other end of the capacitor C2 is connected to the RESETB pin of the MCU, a negative electrode of the diode D1 is connected to a power supply VCC, and an anode of the diode D1 is connected to the RESETB pin of the MCU; the resistor R4 is connected in parallel with the diode D1.
The capacitor C2, the resistor R4 and the diode D1 work in a coordinated mode, and therefore reliable resetting and power-on work of the MCU are guaranteed.
The negation module 3 comprises a triode Q1, a resistor R5 and a resistor R6, the base electrode of the triode Q1 is connected with the PA09 pin of the MCU through a resistor R5, the collector electrode of the triode Q1 is connected with the key module 2, and the emitter electrode of the triode Q1 is grounded; one end of the resistor R6 is connected with the emitter of the triode Q1, and the other end is connected with the base of the triode Q1.
The MCU controls the on or off state of the triode or the MOS tube Q1 through a pin PA09, so that the on or off relation among signals of one end of a key K1, one end of a key K2 and one end of a key K3 of the key unit and the ground is controlled.
In the above embodiment, the key module 2 includes a key unit, a second filtering unit and a pull-up unit, the key unit is respectively connected to the MCU and the negation module 3, and both the second filtering unit and the pull-up unit are connected to the key unit;
the key unit is used for pressing, generating a feedback signal and transmitting the feedback signal to the MCU; the second filtering unit is used for filtering the feedback signal; the pull-up unit is used for pulling up the current of the circuit between the key unit and the MCU and is matched with the negation module 3 to conduct signal data negation.
The key unit can enable the corresponding signal line to be in a conducting or disconnecting state in a physical pressing mode; the second filtering unit filters the feedback signal, so that part of clutter signal interference can be filtered; the pull-up unit ensures that the GPIO input port of the MCU is in an effective and reliable level state, and ensures the accuracy of the feedback signal.
In the above embodiment, the key unit includes a key K1, a key K2, and a key K3, one end of the key K1 is connected to a pin PA14 of the MCU, and the other end is connected to a collector of the transistor Q1; one end of the key K2 is connected with a PA13 pin of the MCU, and the other end of the key K2 is connected with a collector of the triode Q1; one end of the key K3 is connected with a PA12 pin of the MCU, and the other end of the key K3 is connected with a collector of the triode Q1.
The key K1, the key K2 and the key K3 are pressed in a physical pressing mode, and corresponding signal lines can be in a conducting or disconnecting state through the coordinated operation of the MCU module 1 and the negation module 3.
In the above embodiment, the second filtering unit includes capacitors C5 to C7, one end of the capacitor C7 is connected to the PA14 pin of the MCU, and the other end is grounded; one end of the capacitor C6 is connected with a PA13 pin of the MCU, and the other end of the capacitor C6 is grounded; one end of the capacitor C5 is connected with a PA12 pin of the MCU, and the other end of the capacitor C5 is grounded;
the pull-up unit comprises a resistor R1-a resistor R3, one end of the resistor R1 is connected to a power supply VCC, and the other end of the resistor R1 is connected with a PA14 pin of the MCU; one end of the resistor R2 is connected to a power supply VCC, and the other end of the resistor R2 is connected with a PA13 pin of the MCU; one end of the resistor R3 is connected to a power supply VCC, and the other end of the resistor R3 is connected to a PA12 pin of the MCU.
The capacitors C5 to C7 filter the feedback signals, so that part of clutter signal interference can be filtered; the resistor R1 to the resistor R3 ensure that the MCU input GPIO port is in an effective and reliable level state, and ensure the accuracy of the feedback signal.
Example 2:
referring to fig. 1-2, the key encryption method of the present invention includes the following steps:
The MCU module 1 is customized into a Watchdog (WDT) timing wake-up mode, and is in a low-power-consumption sleep state at ordinary times, so that the system can keep extremely low power consumption, several uAs or even lower; meanwhile, the MCU module 1 is awakened to be in a normal working state periodically and regularly through a Watchdog (WDT), for example, once in 50ms, and the MCU module 1 operates; and after the operation is finished, the system enters the low-power-consumption dormant state again, and the operation is repeated, so that the system can accurately operate, and meanwhile, the extremely low power consumption level is kept.
When the MCU module 1 is in the wake-up mode, the MCU module 1 outputs a random signal to the negation module 3; the negation module 3 performs data negation on the data content of the random signal to generate a feedback signal; meanwhile, when the key module is pressed, the feedback signal is transmitted to the MCU module 1, the MCU module 1 judges the data content of the random signal and the data content of the feedback signal, the data content of the random signal is a data head, a middle number and a data tail in sequence, and if the random signal is AA, XX, XX,55 (hexadecimal), the data content of the feedback signal received by the MCU module 1 is 55, XX, XX, AA; wherein the intermediate number is a systematic pseudorandom code generation; when the MCU module 1 judges that the data content of the feedback signal is the negation data of the data content of the random signal, the negation data is used as one of the conditions for controlling the pressing of the key module 2 to take effect;
the data type and format specification takes "AA, XX, 55" as an example, the "AA" is a data head, the "55" is a data tail, and the data head and the data tail can be changed according to actual needs and are not necessarily fixed; the 'XX, XX' is intermediate data, which can be two bits, or one or several bits, and is determined according to actual needs, and the intermediate data can be generated by program pseudo random code, and each time the data are different, so as to prevent the illegal analog key with the data format from being forged after the data are illegally intercepted;
meanwhile, the MCU module 1 also detects the pulse width of the random signal, the signal waveform represents low level by binary ' 0 ', 1 ' represents high level, the pulse width of the random signal can be generated by a system pseudo-random code, the pulse width of each time is different, the pulse width of the random signal detected by the MCU module 1 is consistent with the pulse width of the feedback signal, and the data content of the feedback signal is judged to be the inverted data of the data content of the random signal; the MCU module 1 controls the press of the key module 2 to take effect; the problem of key false identification caused by illegal forged data can be effectively prevented by measuring the pulse width of the feedback signal;
according to the technical scheme, the reliability and the stability of key action identification can be greatly improved through a double encryption mode of the content of the feedback signal and the pulse width of the signal. The condition of illegal simulation of high and low level states of the keys or the condition of achieving key misoperation through an external disturber (such as a Tesla coil) cannot occur.
In the above embodiment, the MCU module 1 includes an MCU, a first filtering unit and a reset power-on unit, where the first filtering unit is connected to the MCU and also connected to a power VCC; the first filtering unit is used for filtering the MCU access power supply signal;
the reset power-on unit is connected with the MCU and also connected with a power supply VCC; and the reset power-on unit is used for controlling the MCU to reset power-on operation.
The MCU is used for generating a random signal, judging whether the content of the random signal and the content of the feedback signal are in inverse correspondence or not, and detecting the pulse width of the feedback signal; when the content of the random signal corresponds to the content of the feedback signal and the pulse width of the detected feedback signal is a corresponding value, a conducting signal is generated and transmitted to the negation module 3;
the first filtering unit can ensure that a power supply signal input by the MCU is clean and stable; the reset power-on unit can ensure that the MCU is reliably reset and powered on to work.
In the above embodiment, the first filtering unit includes a capacitor C1, a capacitor C3, a capacitor C4, a capacitor C8 and a capacitor C9, and the VCORE pin of the MCU is grounded via the capacitor C1;
one end of the capacitor C3 is connected with a VDDA pin of the MCU, and the other end of the capacitor C3 is grounded; the VDDA pin of the MCU is also connected with a power supply VCC; the capacitor C4 is connected in parallel with the capacitor C3;
one end of the capacitor C8 is connected with a VDD pin of the MCU, and the other end of the capacitor C8 is grounded; the VDD pin of the MCU is also connected with a power supply VCC; the capacitor C9 is connected in parallel with the capacitor C8.
The capacitor C1, the capacitor C3, the capacitor C4, the capacitor C8 and the capacitor C9 are coordinated to operate, so that power signals input by the MCU can be filtered, and the cleanness and stability of the power signals input by the MCU are guaranteed.
In the above embodiment, the reset power-on unit includes a capacitor C2, a resistor R4, and a diode D1, one end of the capacitor C2 is grounded, the other end of the capacitor C2 is connected to the RESETB pin of the MCU, a negative electrode of the diode D1 is connected to a power supply VCC, and an anode of the diode D1 is connected to the RESETB pin of the MCU; the resistor R4 is connected in parallel with the diode D1.
The capacitor C2, the resistor R4 and the diode D1 work in a coordinated mode, and therefore reliable resetting and power-on work of the MCU are guaranteed.
The negation module 3 comprises a triode Q1, a resistor R5 and a resistor R6, the base electrode of the triode Q1 is connected with the PA09 pin of the MCU through a resistor R5, the collector electrode of the triode Q1 is connected with the key module 2, and the emitter electrode of the triode Q1 is grounded; one end of the resistor R6 is connected with the emitter of the triode Q1, and the other end is connected with the base of the triode Q1.
The MCU controls the on or off state of the triode or the MOS tube Q1 through a pin PA09, so that the on or off relation among signals of one end of a key K1, one end of a key K2 and one end of a key K3 of the key unit and the ground is controlled.
In the above embodiment, the key module 2 includes a key unit, a second filtering unit and a pull-up unit, the key unit is respectively connected to the MCU and the negation module 3, and both the second filtering unit and the pull-up unit are connected to the key unit;
the key unit is used for pressing, generating a feedback signal and transmitting the feedback signal to the MCU; the second filtering unit is used for filtering the feedback signal; and the pull-up unit is used for adjusting the level state of the input end of the MCU.
The key unit can enable the corresponding signal line to be in a conducting or disconnecting state in a physical pressing mode; the second filtering unit filters the feedback signal, so that part of clutter signal interference can be filtered; the pull-up unit ensures that the GPIO input port of the MCU is in an effective and reliable level state, and ensures the accuracy of the feedback signal.
In the above embodiment, the key unit includes a key K1, a key K2, and a key K3, one end of the key K1 is connected to a pin PA14 of the MCU, and the other end is connected to a collector of the transistor Q1; one end of the key K2 is connected with a PA13 pin of the MCU, and the other end of the key K2 is connected with a collector of the triode Q1; one end of the key K3 is connected with a PA12 pin of the MCU, and the other end of the key K3 is connected with a collector of the triode Q1.
The key K1, the key K2 and the key K3 are pressed in a physical pressing mode, and corresponding signal lines can be in a conducting or disconnecting state through the coordinated operation of the MCU module 1 and the negation module 3.
In the above embodiment, the second filtering unit includes capacitors C5 to C7, one end of the capacitor C7 is connected to the PA14 pin of the MCU, and the other end is grounded; one end of the capacitor C6 is connected with a PA13 pin of the MCU, and the other end of the capacitor C6 is grounded; one end of the capacitor C5 is connected with a PA12 pin of the MCU, and the other end of the capacitor C5 is grounded;
the pull-up unit comprises a resistor R1-a resistor R3, one end of the resistor R1 is connected to a power supply VCC, and the other end of the resistor R1 is connected with a PA14 pin of the MCU; one end of the resistor R2 is connected to a power supply VCC, and the other end of the resistor R2 is connected with a PA13 pin of the MCU; one end of the resistor R3 is connected to a power supply VCC, and the other end of the resistor R3 is connected to a PA12 pin of the MCU.
The capacitors C5 to C7 filter the feedback signals, so that part of clutter signal interference can be filtered; the resistor R1 to the resistor R3 ensure that the MCU input GPIO port is in an effective and reliable level state, and ensure the accuracy of the feedback signal.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. The key encryption circuit comprises an MCU module (1), a key module (2) and an inverting module (3), wherein the input end of the MCU module (1) is connected with one end of the key module (2), the output end of the MCU module (1) is connected with the inverting module (3), and the other end of the key module (2) is also connected with the inverting module (3);
the MCU module (1) is used for periodically and regularly outputting a random signal to the negation module (3); the device is also used for judging the data content of the random signal and the data content of the feedback signal and measuring the pulse width of the random signal and the pulse width of the feedback signal; when the data content of the feedback signal is judged to be the inverted data of the data content of the random signal, and the pulse width of the random signal is consistent with the pulse width of the feedback signal; the pressing of the key module (2) is effective;
the negation module (3) is used for performing data negation on the data content of the random signal to generate a feedback signal;
the key module (2) is used for conducting when pressed and transmitting a feedback signal to the MCU module (1).
2. The key encryption circuit according to claim 1, wherein the data content of the random signal is sequentially a data header, a middle data and a data trailer, and the data content of the feedback signal is sequentially the inverted data content of the data header, the middle data and the data trailer; wherein the intermediate number is a systematic pseudorandom code generation;
the pulse width of the random signal is generated by a systematic pseudo random code.
3. The key encryption circuit according to claim 2, wherein the MCU module (1) comprises an MCU, a first filtering unit and a reset power-on unit, the first filtering unit is respectively connected with the MCU and is also connected with a power supply VCC; the first filtering unit is used for filtering the MCU access power supply signal;
the reset power-on unit is connected with the MCU and also connected with a power supply VCC; and the reset power-on unit is used for controlling the MCU to reset power-on operation.
4. The key encryption circuit of claim 3, wherein the first filtering unit comprises a capacitor C1, a capacitor C3, a capacitor C4, a capacitor C8 and a capacitor C9, and the VCORE pin of the MCU is grounded through the capacitor C1;
one end of the capacitor C3 is connected with a VDDA pin of the MCU, and the other end of the capacitor C3 is grounded; the VDDA pin of the MCU is also connected with a power supply VCC; the capacitor C4 is connected in parallel with the capacitor C3;
one end of the capacitor C8 is connected with a VDD pin of the MCU, and the other end of the capacitor C8 is grounded; the VDD pin of the MCU is also connected with a power supply VCC; the capacitor C9 is connected in parallel with the capacitor C8.
5. The key encryption circuit according to claim 4, wherein the reset power-on unit comprises a capacitor C2, a resistor R4 and a diode D1, one end of the capacitor C2 is grounded, the other end of the capacitor C2 is connected with the RESETB pin of the MCU, the cathode of the diode D1 is connected with a power supply VCC, and the anode of the diode D1 is connected with the RESETB pin of the MCU; the resistor R4 is connected in parallel with the diode D1.
6. A key encryption circuit according to any one of claims 3 to 5, characterized in that said inverting module (3) comprises a transistor Q1, a resistor R5 and a resistor R6, the base of said transistor Q1 is connected to the PA09 pin of the MCU via a resistor R5, the collector of said transistor Q1 is connected to said key module (2), and the emitter of said transistor Q1 is connected to ground; one end of the resistor R6 is connected with the emitter of the triode Q1, and the other end is connected with the base of the triode Q1.
7. The key encryption circuit according to claim 6, wherein the key module (2) comprises a key unit, a second filtering unit and a pull-up unit, the key unit is respectively connected with the MCU and the negation module (3), and the second filtering unit and the pull-up unit are both connected with the key unit;
the key unit is used for pressing, generating a feedback signal and transmitting the feedback signal to the MCU; the second filtering unit is used for filtering the feedback signal; the pull-up unit is used for pulling up the current of the circuit between the key unit and the MCU and is matched with the negation module (3) to conduct signal data negation.
8. The key encryption circuit according to claim 7, wherein the key unit comprises a key K1, a key K2 and a key K3, one end of the key K1 is connected with a PA14 pin of the MCU, and the other end is connected with a collector of the triode Q1; one end of the key K2 is connected with a PA13 pin of the MCU, and the other end of the key K2 is connected with a collector of the triode Q1; one end of the key K3 is connected with a PA12 pin of the MCU, and the other end of the key K3 is connected with a collector of the triode Q1.
9. The key encryption circuit according to claim 8, wherein the second filtering unit comprises a capacitor C5-C7, one end of the capacitor C7 is connected with a PA14 pin of the MCU, and the other end is grounded; one end of the capacitor C6 is connected with a PA13 pin of the MCU, and the other end of the capacitor C6 is grounded; one end of the capacitor C5 is connected with a PA12 pin of the MCU, and the other end of the capacitor C5 is grounded;
the pull-up unit comprises a resistor R1-a resistor R3, one end of the resistor R1 is connected to a power supply VCC, and the other end of the resistor R1 is connected with a PA14 pin of the MCU; one end of the resistor R2 is connected to a power supply VCC, and the other end of the resistor R2 is connected with a PA13 pin of the MCU; one end of the resistor R3 is connected to a power supply VCC, and the other end of the resistor R3 is connected to a PA12 pin of the MCU.
10. The key encryption method is characterized by comprising the following steps:
the method comprises the following steps that 1, an MCU module (1) periodically outputs random signals to an negation module (3) at regular time, and the negation module (3) performs data negation on data contents of the random signals to generate feedback signals;
step 2, conducting when the key module (2) is pressed, and transmitting a feedback signal to the MCU module (1);
step 3, the MCU module (1) judges the data content of the random signal and the data content of the feedback signal and simultaneously measures the pulse width of the random signal and the pulse width of the feedback signal; when the data content of the feedback signal is judged to be the inverted data of the data content of the random signal, and the pulse width of the random signal is consistent with the pulse width of the feedback signal; the pressing of the key module (2) takes effect.
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| US6252288B1 (en) * | 1999-01-19 | 2001-06-26 | Rockwell Science Center, Llc | High power trench-based rectifier with improved reverse breakdown characteristic |
| CN102857232B (en) * | 2012-09-17 | 2016-03-09 | 青岛海信宽带多媒体技术有限公司 | A kind of key press detecting circuit and detection method |
| CN105302319B (en) * | 2014-07-22 | 2018-08-07 | 中国长城科技集团股份有限公司 | A kind of press key locking control circuit and portable mobile terminal |
| CN104867214B (en) * | 2015-05-22 | 2017-11-14 | 青岛歌尔声学科技有限公司 | Door opening method and system based on sound wave identification |
| CN107515662B (en) * | 2016-06-15 | 2020-05-15 | 深圳市博巨兴微电子科技有限公司 | Low-power-consumption management method in MCU chip for keying application |
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