Specific embodiment
Below in conjunction with attached drawing, the invention will be further described.
Fig. 1 is the AC voltage regulator composition block diagram for realizing AC voltage-stabilizing control method, samples comparing unit to AC power source
Voltage carries out voltage sample, output triggering gating controlling value P2;Delay protection unit input triggering gating controlling value P2, output are prolonged
The triggering to lag gates controlling value P3 and not trigger region control signal P4;Triggering choosing after triggering gating control cells input delay
Logical controlling value P3, exports Trig control signal P5;Trigger unit issues trigger signal P6 according to the Trig control signal P5 of input
To compensation main circuit, the on-off of bidirectional thyristor in thyristor bridge is controlled;Triggering choosing after error detection judgement unit input delay
Logical controlling value P3, output triggering gating controlling value differentiate signal P7;Protect driving unit input not trigger region control signal P4 and
Triggering gating controlling value differentiates signal P7, differentiates whether signal P7 effectively stops/starting to crystalline substance according to triggering gating controlling value
The open-circuit-protection of brake tube bridge, while differentiating whether effectively and not trigger region controls signal P4 to signal P7 according to triggering gating controlling value
Whether the power supply effectively to control trigger unit.
Fig. 2 is compensation main circuit embodiment 1, and compensator transformer TB1, TB2 form compensator transformer group, 6 two-way crystalline substances
Brake tube SR1-SR6 collectively constitutes thyristor bridge, and fuse FU1 and relay normally open switch KA-1, KA-2, KA-3, relay are normal
Make and break closes KA-5, KA-6 and forms relay protection circuit.
In Fig. 2, the bucking coil of compensator transformer TB1, TB2 are connected in phase line, and phase line input terminal is LA1, output
End is LA2.Voltage on TB1, TB2 magnet exciting coil is controlled by thyristor bridge.1 thyristor full-bridge circuit includes upper and lower 2 crystalline substances
Brake tube bridge arm.In Fig. 2, the thyristor full-bridge circuit of SR1 and SR2 composition is connected to after one end of TB1, TB2 magnet exciting coil is in parallel,
The other end of TB1, TB2 magnet exciting coil is respectively connected to the thyristor full-bridge circuit of SR3 and SR4, SR5 and SR6 composition.If TB1,
The offset voltage of TB2 is not identical, does not consider the compensation way that offset voltage is cancelled out each other, then compensator transformer group at most shares just
To TB1, forward direction TB2, forward direction TB1+TB2, reversed TB1, reversed TB2, reversed TB1+TB2 totally 6 kinds of voltage compensation states, additional one
The AC supply voltage of 0 voltage compensation state when kind input voltage is within normal range (NR), phase line input terminal LA1 input can
At most being divided into 7 voltage ranges compensates control.In Fig. 2, N is zero curve, and G11, G12 to G61, G62 are respectively two-way crystalline substance
The trigger signal input terminal of brake tube SR1 to SR6.
Fig. 3 is compensation main circuit embodiment 2, and compensator transformer TB1, TB2, TB3 form compensator transformer group, and 8 double
Thyristor bridge, fuse FU1 and relay normally open switch KA-1, KA-2, KA-3, KA-4 are collectively constituted to thyristor SR1-SR8,
Relay normally closed switch KA-4, KA-5, KA-6 form relay protection circuit.
In Fig. 3, the bucking coil of compensator transformer TB1, TB2, TB3 are connected in phase line, and phase line input terminal is LA1,
Output end is LA2.Voltage on TB1, TB2, TB3 magnet exciting coil is controlled by thyristor bridge, and the one of TB1, TB2, TB3 magnet exciting coil
The thyristor full-bridge circuit of SR1 and SR2 composition is connected to after end is in parallel, the other end of TB1, TB2, TB3 magnet exciting coil connects respectively
It is connected to the thyristor full-bridge circuit of SR3 and SR4, SR5 and SR6, SR7 and SR8 composition.If the offset voltage of TB1, TB2, TB3 are equal
It is not identical, do not consider the compensation way that offset voltage is cancelled out each other, then compensator transformer group is at most shared 7 kinds positive, and reversed 7
Kind, totally 14 kinds of voltage compensation states, 0 voltage compensation state when a kind of additional input voltage is within normal range (NR), phase line is defeated
The AC supply voltage for entering to hold LA1 to input can be at most divided into 15 voltage ranges and compensate control.In Fig. 3, N zero
Line, G11, G12 to G81, G82 are respectively the trigger signal input terminal of bidirectional thyristor SR1 to SR8.
Each bidirectional thyristor in Fig. 2, Fig. 3 can be substituted with the unidirectional thyristor of 2 reverse parallel connections.Fig. 2, Fig. 3
In, relay normally open switch and relay normally closed switch composition relay protection switch.
The voltage of AC supply voltage waving interval range is divided into M voltage class section, samples comparing unit to friendship
Stream supply voltage carries out voltage sample and obtains AC supply voltage sampled value, by M comparator to AC supply voltage sampled value
It is compared, the triggering that output M-bit binary number is constituted gates controlling value;When AC supply voltage is in M voltage class area
Between in one when, in M triggerings gating controlling values corresponding one effectively, other positions are invalid.M triggerings gate controlling value
Significance bit is high level, i.e. binary one;Invalid bit is low level, i.e. Binary Zero;Either, M triggerings gate controlling value
Significance bit is low level, i.e. Binary Zero;Invalid bit is high level, i.e. binary one.
Fig. 4 is sampling comparing unit embodiment 1, compensates control for compensation main circuit embodiment 1.AC power source
In voltage sampling circuit, the AC supply voltage inputted from phase line LA1 and zero curve N is after transformer TV decompression, by diode
The rectifier bridge rectification of DV1-DV4 composition, then divided through capacitor CV1 filtering and resistance RV1, RV2, obtain the AC power source with input
The AC supply voltage sampled value U1 of voltage effective value direct proportionality.
Between the multi-region of Fig. 4 in voltage comparator circuit, resistance RF1-RF8 forms bleeder circuit, divides to power supply+VCC1
Afterwards, 7 threshold voltage UF1-UF7 are obtained.7 comparator FA1-FA7 realize AC supply voltage sampled value U1 and 7 threshold value electricity
The comparison of UF1-UF7 is pressed, the triggering gating controlling value P2 of output is made of the output Y11-Y17 of 7 comparator FA1-FA7, will
The voltage of AC supply voltage waving interval range is divided into 7 voltage class section 1-7.Amplifier FA0 forms follower, alternating current
Source voltage sample value U1 is sent simultaneously after follower FA0 driving to the inverting input terminal of comparator FA1-FA7;AC power source
Voltage sample value U1 can also drive without follower FA0 and directly send simultaneously to the inverting input terminal of comparator FA1-FA7;7
Threshold voltage UF1-UF7 is sent respectively to the non-inverting input terminal of comparator FA1-FA7.In Fig. 4, other accurate electricity can also be used
Power supply+VCC1 is replaced in source, and bleeder circuit divides precision voltage source, threshold voltage can be made more accurate.Amplifier FA0 and ratio
The rail-to-rail amplifier of low-power consumption single supply power supply is preferably used compared with device FA1-FA7, for example, selection OPA317, AD8517,
Single-pass track of the quiescent operations source current such as MCP6291, TLV2450, TLV2451, TLV2460, TLV2461 less than 1mA arrives
Rail amplifier.
In Fig. 4, nor gate FH2-FH7 forms the controllable power supply of comparator FA2-FA7, i.e. comparator FA2-FA7's
The power supply control by output Y11-Y16 respectively;Resistance RB2-RB7 is respectively the pull down resistor for exporting Y12-Y17, works as phase
The power supply for answering comparator is to draw level for low level when output is high-impedance state close to 0V.The power supply of comparator FA1
Power supply is connected to power supply+VCC1, is in normal operating conditions, and output Y11 controls the power supply of comparator FA2-FA7 simultaneously.Example
Such as, when the AC supply voltage of input is low, when a minimum voltage class section 1 in 7 voltage class sections, Y11 is defeated
High level out, all output is low level to nor gate FH2-FH7, and the single supply power supply of comparator FA2-FA7 is all to be connect
Nearly 0V, output are close to 0V either high-impedance state, and resistance RB2-RB7 respectively draws output Y12-Y17 for low level.Work as input
AC supply voltage not at a minimum voltage class section 1 in 7 voltage class sections, Y11 export low level or non-
Door FH2 exports high level and provides power supply to comparator FA2, at this point, if the AC supply voltage of input is in voltage etc.
When grade section 2, Y12 exports high level, and all output is low level to nor gate FH3-FH7, and the single supply of comparator FA3-FA7 supplies
Power supply is all close to 0V, and output is close to 0V either high-impedance state, and resistance RB3-RB7 respectively draws output Y13-Y17
For low level.When the AC supply voltage of input is higher than voltage class section 2, Y11, Y12 export low level, nor gate
FH2, FH3 export high level, provide power supply to comparator FA2, FA3 respectively, at this point, if the AC power source electricity of input
When pressure is in voltage class section 3, Y13 exports high level, and all output is low level, comparator FA4- to nor gate FH4-FH7
The single supply power supply of FA7 is all close to 0V, and output is close to 0V either high-impedance state, and resistance RB4-RB7 respectively will
Exporting Y14-Y17 and drawing is low level.The rest may be inferred, and when the AC supply voltage of input is in voltage class section 4, Y14 is defeated
High level out, other outputs are low level;When the AC supply voltage of input is in voltage class section 5, the high electricity of Y15 output
Flat, other outputs are low level;When the AC supply voltage of input is in voltage class section 6, Y16 exports high level,
It is low level that he, which exports,;When the AC supply voltage of input is in voltage class section 7, Y17 exports high level, other outputs
For low level.When nor gate FH2-FH7 selects 74HC series of high speed CMOS gate circuit, for example, 8 input nor gate of selection
74HC4078, three tunnels 3 input nor gate 74HC27, four tunnels 2 input nor gate 74HC02 etc. or 74HC series of high speed CMOS
Or door add NOT gate realize nor gate function when, since the high level driving current of 74HC series of high speed CMOS can reach 4mA, foot
Enough single channel rail-to-rail amplifier of the driving quiescent operation source current less than 1mA.The power supply of nor gate FH1-FH6 is power supply
+VCC1。
If the AC supply voltage fluctuation range of input is 220V ± 10%, it is desirable that stablized the model in 220V ± 2%
Enclose interior output.Comparing unit embodiment 1 is sampled using Fig. 4, input can be divided into section in 242V to the voltage between 198V
Voltage swing is 7 voltage class sections of 6.4V, and the voltage in 3 voltage class sections therein is higher than desired output voltage
Range needs to carry out drop compensation;The voltage in 3 voltage class sections is risen lower than desired output voltage range
Pressure compensation;1 voltage class section carries out 0 voltage compensation, i.e. uncompensation within desired output voltage range.6.4V
Voltage range is not more than 220V ± 1.5%, meets requirement of the output control within 220V ± 2%;7 voltage class of 6.4V
The corresponding AC supply voltage waving interval in section is 242.4V to 197.6V, covers the range actually fluctuated.It is mended using Fig. 2
It repays formula main circuit embodiment 1 to compensate, and TB1 offset voltage is low, TB2 offset voltage is high;The offset voltage of TB2 is TB1 benefit
2 times for repaying voltage, then when voltage is alternating current 220V on magnet exciting coil at this time, TB1 offset voltage is 6.4V, and TB2 offset voltage is
12.8V.Ratio phase between the selection and AC supply voltage sampled value U1 and AC supply voltage of threshold voltage UF1-UF7
It closes;If the ratio between AC supply voltage sampled value U1 and AC supply voltage is 0.01, i.e. AC supply voltage sampled value
U1 is the 1% of AC supply voltage virtual value, and input is in 242V to the corresponding voltage sample value range of voltage between 198V
2.42V to 1.98V;When AC supply voltage is divided into 7 voltage class sections that section voltage swing is 6.4V, 7 threshold values
Voltage UF7-UF1 is respectively 2.424V, 2.36V, 2.296V, 2.232V, 2.168V, 2.104V, 2.04V, respectively with will
The voltage sample value that 242.4V divides into 7 voltage class section upper limit values to 197.6V range of voltages is corresponding;According to 7 threshold values
The size of voltage UF1-UF7 and+VCC1 can calculate the size of resistance RF1-RF8.
Since the compensation way of compensation main circuit embodiment 1 has Schmidt's characteristic, comparator FA1 to comparator automatically
FA7 does not form Schmidt's comparator.The triggering gating controlling value high level of Fig. 4 output is effective;In the defeated of comparator FA1-FA7
Outlet increases level-one phase inverter, then it is effective that the triggering gating controlling value exported becomes low level.
In the sampling comparing unit embodiment 1 of Fig. 4, when the AC supply voltage of input is lower than minimum voltage levels section model
When enclosing, output signal corresponding with minimum voltage levels section is effective in the triggering gating controlling value of output, i.e. output has for Y11
Effect;Main circuit is in minimum voltage levels section according to the AC supply voltage of input and carries out corresponding voltage step-down benefit at this time
It repays.When the AC supply voltage of input is higher than maximum voltage grade interval range, own in the triggering gating controlling value of output
Signal is invalid, and main circuit is without voltage compensation at this time.If removing the comparison in the sampling comparing unit embodiment 1 of Fig. 4
6 threshold voltage UF6-UF1 of device FA7, comparator FA6-FA1 are constant, for the AC power source with 7 voltage class sections of separation
The intermediate dividing voltage value of 7 of the corresponding voltage sample value of voltage value;Directly by the output signal of nor gate FH7, i.e. highest
Interval judgement value Y17-1 is as the Y17 in triggering gating controlling value, then when the AC supply voltage of input is at or above most
It is that Y17 output is effective, and main circuit is in maximum voltage according to the AC supply voltage of input when big voltage class interval range
Grade interval carries out corresponding voltage step-down compensation.
The embodiment 1 of Fig. 4 can also be carried out for compensation main circuit embodiment 2, at this time, it may be necessary to by AC supply voltage
The voltage of waving interval range is divided into more voltage class sections.For example, by the electricity of AC supply voltage waving interval range
When pressure is divided into 15 voltage class sections, the circuit of Fig. 4 should extend to 15 comparators, with 15 threshold value electricity of different sizes
Pressure is compared;14 comparators are either used, are compared with 14 threshold voltages of different sizes;The triggering of output is selected
Logical controlling value P2 will be by 15, for example, Y11-Y115 is formed.
Fig. 5 is sampling comparing unit embodiment 2, for compensating control for compensation main circuit embodiment 2.Fig. 5
In, FD1 is that real available value detects device LTC1966, LTC1966 and transformer TV1, capacitor CV2, capacitor CV3 composition alternating current
Source voltage sampling circuit measures the AC supply voltage inputted from phase line LA1 and zero curve N, obtains AC supply voltage
Sampled value U2.UIN1, UIN2 of LTC1966 is alternating voltage difference input terminal, and USS is the negative supply input terminal that can be grounded,
UDD is positive power input, and GND is ground terminal, and EN is that low level effectively enables control signal, and UOUT is voltage output end,
COM is output voltage return terminal.
In Fig. 5, voltage comparator circuit between FD2, resistance RD1, resistance RD2, phase inverter FB1-FB10 composition multi-region;FD2
Compare display driver LM3914 for 10 grades, the internal voltage divider circuit that inside is together in series containing 10 1k Ω precision resistances is formed
10 comparative threshold voltages and the positive input terminal for being respectively connected to internal 10 comparators, by AC supply voltage waving interval model
The voltage enclosed is divided into 10 voltage class section 1-10.6 feet are that internal voltage divider circuit is high-end, are connected in 7 feet through resistance RD1
Ministerial standard power supply exports VREF;4 feet are internal voltage divider circuit low side, are connected to the ground through resistance RD2;8 feet are internal standard power supply
Low side is connected to the ground;2 feet are negative power end, are connected to the ground;3 feet are positive power source terminal, are connected to power supply+VCC1;5 feet are signal
Input terminal is connected to AC supply voltage sampled value U2, is connected internally to the negative input end of 10 comparators;10-18 foot, 1 foot
The signal L10 to L1 of output is with the output of 10 comparators as a result, wherein L10 comparative threshold voltage highest, successively reduces, L1
Comparative threshold voltage is minimum;The equal low level of L1 to L10 is effective;The scheme control end of 9 feet is hanging, realizes that L1's to L10 is dotted defeated
Out, i.e., single low level output is effective.In Fig. 5, internal voltage divider circuit is high-end can also to be connected to other power supplys through resistance RD1,
For example, power supply+VCC1.
In Fig. 5,10 phase inverter FB1-FB10 for carrying out reverse phase respectively to output signal L1-L10, obtain 10 two into
Y11-Y110 processed is formed, high level effectively triggers gating controlling value P2.AC supply voltage is in 10 voltage class areas
Between one in 1-10 when, corresponding one is high level in Y11-Y110, other positions are low level.For example, when the friendship of input
When stream supply voltage is in voltage class section 10, Y110 exports high level, other outputs are low level;When the alternating current of input
When source voltage is in voltage class section 9, Y19 exports high level, other outputs are low level;When the AC supply voltage of input
When in voltage class section 5, Y15 exports high level, other outputs are low level;When the AC supply voltage of input is in electricity
When pressing grade interval 1, Y11 exports high level, other outputs are low level.The phase inverter FB1-FB10 cancelled in Fig. 5 directly makes
When output signal L1-L10 being used to gate controlling value Y11-Y110 as triggering, triggering gating controlling value low level is effective.Phase inverter
FB1-FB10 is all made of power supply+VCC1 power supply.
10 comparators inside LM3914 are used in Fig. 5, by the AC supply voltage waving interval range of input
Voltage relatively divides into 10 voltage class sections.If the AC supply voltage fluctuation range of input is 220V+10% to 220V-
20%, it is desirable that stablized and exported in the range of 220V ± 2%.Using the sampling comparing unit embodiment 2 of Fig. 5, will input
It is divided into 10 voltage class sections that section voltage swing is 7V, 3 voltage therein etc. in 242V to the voltage between 176V
The voltage in grade section is higher than desired output voltage range, needs to carry out drop compensation;The voltage in 6 voltage class sections is lower than
It is required that output voltage range, need to carry out boosting compensation;1 voltage class section within desired output voltage range,
Carry out 0 voltage compensation, i.e. uncompensation.The voltage range of 7V is 220V ± 1.6%, meets output control within 220V ± 2%
Requirement, the corresponding AC supply voltage waving interval in 10 voltage class sections of 7V is 244.5V to 174.5V, is covered
The range actually fluctuated.It is compensated using the compensation main circuit embodiment 2 of Fig. 3, and TB1 offset voltage is minimum, TB3 compensation electricity
Press highest;The offset voltage of TB2 is 2 times of TB1 offset voltage, and the offset voltage of TB3 is 2 times of TB2 offset voltage, then at this time
When voltage is alternating current 220V on magnet exciting coil, TB1 offset voltage is 7V, and TB2 offset voltage is 14V, and TB3 offset voltage is 28V.
Ratio between the selection and AC supply voltage sampled value U2 and AC supply voltage of threshold voltage is related;If AC power source is electric
Pressing the ratio between sampled value U2 and AC supply voltage is 0.005, i.e. AC supply voltage sampled value U2 is AC power source electricity
Be pressed with the 0.5% of valid value, then when AC supply voltage being divided into 10 voltage class sections that section voltage swing is 7V, input
It is 1.21V to 0.88V in 242V to the corresponding voltage sample value range of voltage between 176V;10 threshold voltages are respectively
1.1875V、1.1525V、1.1175V、1.0825V、1.0475V、1.0125V、0.9775V、0.9425V、0.9075V、
0.8725V, the voltage with the lower limit value that 244.5V to 174.5V range of voltages is divided into 10 voltage class sections is adopted respectively
Sample value is corresponding;The high-end voltage of internal voltage divider circuit is connected to highest comparator positive input terminal, therefore 6 foot voltages are 1.1875V.According to
The size of 10 threshold voltages and internal standard power supply output VREF (1.2V or 1.25V), and internal 10 accurate electricity
The size of resistance can calculate the size of resistance RD1, RD2.If it is required that improving the precision either input voltage of voltage compensation
Fluctuation range it is bigger, it is desirable that voltage class is divided into more voltage class sections by the sampling comparing unit embodiment 2 of Fig. 5
When, for example, it is desired to can be used 2 when the voltage of AC supply voltage waving interval range is divided into 15 voltage class sections
LM3914 is realized, the internal voltage divider circuit in 2 LM3914 is connected, and forms 20 comparative threshold voltages, is constituted 20 grades and is compared
Device circuit;15 grades therein are selected to compare output, the triggering gating controlling value P2 of output will be by 15, for example, Y11-Y115 group
At.
In the sampling comparing unit embodiment 2 of Fig. 5, when the AC supply voltage of input exceeds maximum voltage grade interval model
When enclosing, the triggering gating controlling value of output is that output signal corresponding with maximum voltage grade interval is effective, i.e. output is Y110
Effectively, main circuit is in maximum voltage grade interval according to AC supply voltage and carries out corresponding voltage step-down compensation.Work as input
AC supply voltage be lower than minimum voltage levels interval range when, output triggering gating controlling value in all equal nothings of signal
Effect, main circuit is without voltage compensation at this time.
10 comparators inside LM3914 in 10 comparators have been used in Fig. 5, and AC supply voltage is compared into differentiation
For 10 voltage class sections.It can be only with 9 comparators in the comparator of the inside LM3914 10, by AC supply voltage
Compare and divides into 10 voltage class sections;For example, the comparative threshold voltage of each comparator does not change, the comparison of 9 comparators
Threshold voltage is 9 centres point of voltage sample value corresponding with the AC supply voltage value in 10 voltage class sections is separated
Every voltage value;Without being selected as the Y11 in triggering gating controlling value, Y11 by triggering after the output L1 reverse phase of LM3914 in Fig. 5
The Y12-Y110 gated in controlling value controls generation, i.e., when Y12-Y110 is all invalid, keeps Y11 effective, otherwise, keep Y11 invalid;
At this point, the triggering of output gates control when the AC supply voltage of input is in or exceeds maximum voltage grade interval range
Value processed is that Y110 is effective, and main circuit is in maximum voltage grade interval according to AC supply voltage and carries out corresponding voltage step-down benefit
It repays;It is that Y11 output is effective when the AC supply voltage of input is at or below minimum voltage levels interval range, it is main
Circuit is in minimum voltage levels section according to the AC supply voltage of input and carries out corresponding boost in voltage compensation.
The sampling comparing unit embodiment 2 of Fig. 5 can also compensate control for compensation main circuit embodiment 1, this
When only the voltage of the AC supply voltage waving interval range of input need to be divided into no more than 7 voltage class sections, that is, select
Select the comparison output wherein no more than 7 grades.
In addition to the sampling comparing unit embodiment of Fig. 4 or Fig. 5, either implement for compensation main circuit embodiment 1
When example 2 compensates control, it is also an option that other AC supply voltage sample circuits and comparison circuit, realize the function of requirement
Energy.The AC supply voltage sampled value U1 of Fig. 4 AC supply voltage sample circuit output, can send to voltage between the multi-region of Fig. 5
Comparator circuit is compared, output triggering gating controlling value;The AC power source electricity of Fig. 5 AC supply voltage sample circuit output
Sampled value U2 is pressed, can send to voltage comparator circuit between the multi-region of Fig. 4 and be compared, output triggering gating controlling value.
Fig. 6 is delay protection unit embodiment block diagram, wherein delay detection module YC1 respectively gates the triggering of input
Controlling value Y11-Y1M carries out triggering gating controlling value Y21-Y2M, Y21-Y2M after signal delay is postponed and forms P3;YC1
Module carries out Edge check to the signal Y11-Y1M of triggering gating controlling value respectively simultaneously and obtains Edge check signal Y31-Y3M;
The Edge check signal Y31-Y3M of input is not converted to not trigger region and controls signal by trigger region control signal generator module YC2
P4 output.In the embodiment block diagram of Fig. 6, the input of delay detection module YC1 is that sampling comparing unit embodiment 1 exports in Fig. 4
Triggering gate controlling value when, M be equal to 7;In the embodiment block diagram of Fig. 6, the input of delay detection module YC1 is to sample in Fig. 5
When the triggering that comparing unit embodiment 2 exports gates controlling value, M is equal to 10.
Fig. 7 is the delay detection circuit embodiment 1 for gating control value signal Y11 in delay detection module needle to triggering.Electricity
Hinder RY0, capacitor CY0, driving gate FY0 realize the signal delay of Y11 is obtained Y11 it is delayed after signal Y21.Resistance RY1,
Capacitor CY1, diode DY1, phase inverter FY1 composition are directed to the rising edge detection circuit of input signal Y 11, and phase inverter FY1's is defeated
Out in signal YP1, the pulse of corresponding negative pulse form is exported after Y11 rising edge.Resistance RY2, capacitor CY2,
Diode DY2, phase inverter FY2, FY3 composition are directed to the failing edge detection circuit of input signal Y 11, the output letter of phase inverter FY3
In number YP2, the pulse of corresponding negative pulse form is exported after Y11 failing edge.NAND gate FY4 is accomplished that negative patrol
Collect or logic function, when there is negative pulse generation in input signal Y P1, YP2, the Edge check signal of NAND gate FY4 output
Positive pulse is generated in Y31, i.e., when input signal Y 11 changes, NAND gate FY4 exports the pulse of a positive pulse form.
In Fig. 7, the device of driving gate FY0, phase inverter FY1, phase inverter FY3 preferably with Schmidt's input, for example, phase inverter selects
74HC14, CD40106 etc.;Driving gate FY0 can be made of 2 phase inverters with Schmidt's input.
Fig. 8 is the delay detection circuit embodiment 2 for gating control value signal Y11 in delay detection module needle to triggering.Instead
Phase device FY5, resistance RY3, capacitor CY3 carry out reverse phase and delay to input signal Y 11, obtain the delayed inversion signal of Y11
YP0;Phase inverter FY6 again by YP0 reverse phase, obtain Y11 it is delayed after signal Y21.NAND gate FY7 input signal be Y11 and
The pulse of negative pulse form corresponding with Y11 rising edge is generated in Y11 delayed inversion signal YP0, output signal YP1;
Or the signal of door FY8 input is the delayed inversion signal YP0 of Y11 and Y11, is generated and Y11 failing edge phase in output signal YP2
The pulse for the negative pulse form answered.NAND gate FY9 is accomplished that negative logic or logic function, when input signal Y P1, YP2
In when having negative pulse generation, generate positive pulse in the Edge check signal Y31 of NAND gate FY9 output, i.e., when input signal Y 11 has
When variation, NAND gate FY9 exports the pulse of a positive pulse form.In Fig. 8, phase inverter FY6, NAND gate FY7 or door FY8
It is preferred that the device with Schmidt's input, for example, phase inverter selects 74HC14, CD40106 etc.;NAND gate selection 74HC132,
CD4093 etc.;Or door selects 74HC7032, or 2 phase inverters with Schmidt's input of selection and 1 NAND gate to come in fact
Existing or door function.
Fig. 9 is the delay detection circuit embodiment 3 for gating control value signal Y11 in delay detection module needle to triggering,
In the rising edge detection circuit for input signal Y 11 formed by resistance RY1, capacitor CY1, diode DY1, phase inverter FY1, and
Failing edge detection circuit for input signal Y 11 is formed by resistance RY2, capacitor CY2, diode DY2, phase inverter FY2, FY3,
And it is identical as the embodiment 1 of Fig. 7 using the circuit of NAND gate FY4 output Edge check signal Y31.In Fig. 9, by phase inverter
FY11, FY12, FY13, FY14 realize the signal delay of Y11 is obtained Y11 it is delayed after signal Y21.
The embodiment 1-3 of Fig. 7, Fig. 8, Fig. 9 are the delay detection electricity for the signal Y11 in triggering gating controlling value
Road is inputted for the delay detection circuit of other signals Y12-Y1M in triggering gating controlling value with being directed in corresponding embodiment
Signal Y11 carries out the circuit structure of delay detection as function.Delay detection circuit can also use other met the requirements
Circuit realizes its function.
Trigger region, which does not control the function of signal generator module, is, when the Edge check for triggering gating controlling value of input
Any one of signal is multiple when having pulse relevant to edge, does not export one in trigger region control signal
Pulse.Figure 10 is that trigger region does not control signal generator module embodiment, realizes phase by the nor gate FY10 for including M input
The function of answering, the input signal of nor gate FY10 are Edge check signal Y31-Y3M, export and control signal P4 for not trigger region.
In Figure 10 embodiment, the pulse of trigger region control signal output is not negative pulse, i.e., trigger region control signal low level does not have
Effect;Nor gate FY10 is changed into or when door, the pulse of trigger region control signal output is positive pulse.If the edge of input
The pulse relevant to edge that has generated in detection signal Y31-Y3M is negative pulse, then the nor gate FY10 in Figure 10 should
NAND gate is changed to either with door, realizes under negative logic or logic function.
All gate circuits in delay protection unit are all made of single supply+VCC1 power supply.Figure 11 is in delay protection unit
Part waveform correlation schematic diagram.From principle and the requirement of sampling comparing unit it is found that its triggering exported gates controlling value
When normal change, change each time with 2.In Figure 11, a rising edge occurs respectively for the Y11 in triggering gating controlling value
Change and failing edge changes, Y21 is the triggering gating controlling value after the Y11 delay T1 time;Implement in the delay detection circuit of Fig. 7
In example 1, T1 is determined by the product size (i.e. time constant size) of resistance RY0 and capacitor CY0;In the delay detection circuit of Fig. 8
In embodiment 2, T1 is determined by the product size of resistance RY3 and capacitor CY3;In the delay detection circuit embodiment 3 of Fig. 9, T1
It is determined by the gate delay time size of phase inverter FY11, FY12, FY13, FY14 itself.In Figure 11, because Y11 rises in signal YP1
It is T2 along the negative pulse width generated;In the delay detection circuit embodiment 1 of Fig. 7 and the delay detection circuit embodiment 3 of Fig. 9
In, T2 is determined by the product size of resistance RY1 and capacitor CY1;In the delay detection circuit embodiment 2 of Fig. 8, T2 is by resistance
The product size of RY3 and capacitor CY3 determines.In Figure 11, because the negative pulse width that Y11 failing edge generates is T3 in signal YP2;?
In the delay detection circuit embodiment 1 of Fig. 7 and the delay detection circuit embodiment 3 of Fig. 9, T3 is multiplied by resistance RY2 and capacitor CY2's
Product size determines;In the delay detection circuit embodiment 2 of Fig. 8, T3 is determined by the product size of resistance RY3 and capacitor CY3.Figure
In 11,2 positive pulses in Edge check signal Y31 respectively with the negative pulse and signal that generate in signal YP1 by Y11 rising edge
Because the negative pulse that Y11 failing edge generates corresponds in YP2.The Y11 being located in Figure 11 triggering gating controlling value occurs rising edge and changes
When, triggering gates the Y12 in controlling value and failing edge change occurs, its corresponding Edge check signal Y32 accordingly generates one at this time
A positive pulse;If a rising edge occurs simultaneously and changes by the Y12 in triggering gating controlling value when failing edge, which occurs, for Y11 changes,
A positive pulse is accordingly generated in its corresponding Edge check signal Y32 at this time;During this period, other touchings except Y11, Y12
There is no variation, edges corresponding with other triggering gating control value signals except Y11, Y12 to examine for hair gating control value signal
Surveying signal is low level, is not drawn into Figure 11.According to not trigger region above-mentioned control signal generator module or logic function,
The simple venation is not generated jointly in the single pulse width of trigger region control signal generator module output and the Edge check signal of input
Widest pulse width is identical in the input pulse of punching, and this width difference is because determining T2, T3 in different delayed time detection circuit
Resistance, capacitance difference caused by.In Figure 11, the 1st positive pulse in the 1st positive pulse ratio Y32 in Y31 is wide, Y31
In the 2nd positive pulse ratio Y32 in the 2nd positive pulse it is narrow, not trigger region control signal P4 in the 1st negative pulse width with
The 1st positive pulse width in Edge check signal Y31 is consistent, not the 2nd negative pulse width in trigger region control signal P4
It is consistent with the 2nd positive pulse width in Edge check signal Y32.
In the delay detection circuit embodiment 1 of Fig. 7 delay protection unit, triggering gating controlling value changes to correspondence
Not trigger region control signal pulse forward position delay time be gate circuit FY1, FY4 and Figure 10 in FY10 delay time
The sum of or gate circuit FY3, FY4 and Figure 10 in FY10 the sum of delay time;By the product of resistance RY0 and capacitor CY0
The range of choice of the signal delay time T1 for the triggering gating controlling value that size determines is the ms order of magnitude, it is clear that is greater than triggering choosing
Logical controlling value changed to the delay time in corresponding not trigger region control signal pulse forward position, i.e. triggering gating controlling value
Signal delay is later than the forward position moment of the pulse exported after triggering gating controlling value changes at the time of change.It is stringent next
It says, T1 actually includes the sum of lag time and the delay time of gate circuit FY0 caused by resistance RY0 and capacitor CY0.
In Fig. 7 embodiment 1, in selection parameter, the value of the value and T3 that make T2 is all larger than the value of T1, makes triggering gating control value signal
After meeting the not trigger region control signal pulse exported after changing earlier than triggering gating controlling value at the time of delay changes
Along the requirement at moment.
It is delayed in detection circuit embodiment 2 in the delay protection unit of Fig. 8, triggering gating controlling value changes to right
When the delay time in the not trigger region control signal pulse forward position answered is the delay of FY10 in gate circuit FY7, FY9 and Figure 10
Between the sum of or gate circuit FY8, FY9 and Figure 10 in FY10 the sum of delay time;T1 is the numerical value of the ms order of magnitude, is shown
So, the signal delay time T1 of the triggering gating controlling value determined at this time by the product size of resistance RY3 and capacitor CY3 is greater than touching
Hair gating controlling value changed to the delay time in corresponding not trigger region control signal pulse forward position, the i.e. control of triggering gating
Value signal delay processed is later than the forward position moment of the pulse exported after triggering gating controlling value changes at the time of change.Fig. 8
Delay detection circuit embodiment 2 in, triggering gating controlling value signal delay change at the time of with triggering gating controlling value
The rear of the pulse exported after change is influenced by signal YP0 change along the moment;Triggering gating controlling value signal delay changes
At the time of change for signal YP0 after delay again through gate circuit FY6;The pulse that triggering gating controlling value exports after changing
It is rear along the moment be the sum of delay time again through FY10 in gate circuit FY7, FY9 and Figure 10, or letter after signal YP0 changes
The sum of delay time again through FY10 in gate circuit FY8, FY9 and Figure 10 after number YP0 changes;Obviously, triggering gating control at this time
The rear of pulse exported after changing at the time of value signal delay changes than triggering gating controlling value few passes through 2 along the moment
The delay time of gate circuit, controlling value need to be gated earlier than triggering by meeting at the time of triggering gating controlling value signal delay changes
The rear requirement along the moment of the pulse exported after change.
Figure 12 is the compensation main circuit embodiment 1 of Fig. 2 to be triggered in trigger unit, or trigger the compensation main circuit of Fig. 3
The trigger circuit embodiment of bidirectional thyristor SR1 in embodiment 2, is made of altemating trigger optocoupler UG1, resistance RG1, resistance RG2,
Trig control signal P51 low level is effective.Altemating trigger optocoupler UG1 can choose MOC3022, MOC3023, MOC3052,
The phase shifts type bidirectional thyristor output photoelectric coupler such as MOC3053.Power supply+VCCK is the controlled electricity of protected driving unit control
Source.Trigger bidirectional thyristor SR2-SR6 in the compensation main circuit embodiment 1 of Fig. 2, or the compensation main circuit reality of triggering Fig. 3
The trigger circuit of bidirectional thyristor SR2-SR8 in example 2 is applied as the circuit structure of triggering bidirectional thyristor SR1.The friendship of Figure 12
The stream triggering optocoupler UG1 triggering arteries and veins that other altemating trigger optocouplers export from G11, G12 trigger pulse exported and trigger unit
Punching collectively constitutes trigger signal P6.
Figure 13 is the embodiment 1 for triggering gating control cells, compensates control for the compensation main circuit embodiment 1 of Fig. 2
System;TB1 offset voltage is low in Fig. 2, and TB2 offset voltage is high, and AC supply voltage fluctuation range is 220V ± 10%, it is desirable that by it
Stabilization exports in the range of 220V ± 2%.In Figure 13, the triggering of triggering gating control cells input gates controlling value Y21-
Y27 high level is effective, 21 diode D11-D73, triggering gating control alignment Y21-Y27, triggering driving line VK1-VK6 group
Matrix is gated at diode triggered, resistance RS1-RS6, triode VS1-VS6 form the driving electricity of Trig control signal P51-P56
Road forms Trig control signal P5 by P51-P56 at this time.
Table 1 is the triggering gating control function table for triggering gating control cells embodiment 1, lists 7 triggering gatings
7 significance bits in controlling value, i.e., bidirectional thyristor is logical in thyristor bridge corresponding to 7 effective triggering gating controlling values
Disconnected assembled state.7 effective triggering gating controlling values are corresponding with voltage class section 1-7, trigger gating control cells foundation
The on off operating mode that triggering gating controlling value controls bidirectional thyristor in compensation main circuit embodiment 1 carries out corresponding voltage benefit
It repays;In table 1,1 represents corresponding bidirectional thyristor need to be in the conductive state, and 0, which represents corresponding bidirectional thyristor, is off shape
State.
The function connects that diode triggered gating matrix in Figure 13 is required according to table 1, are gated controlling value Y21- by triggering
The control of Y27;I.e. when every triggering gating control alignment is effective with its, corresponding on-off assembled state needs to be connected two-way brilliant lock
It is respectively provided with diode between the triggering driving line of pipe to be attached, when certain root triggering gating control alignment is effective, by two poles
Pipe keeps the triggering driving line signal for needing to be connected bidirectional thyristor effective.For example, input voltage be minimum voltage class 1,
That is when Y21 is effectively high level, diode D11, D12, D13 in triggering gating matrix are connected, triggering driving line VK1,
VK4, VK6 control triode VS1, VS4, VS6 conducting for high level respectively makes P51, P54, P56 effectively go to open bidirectional thyristor
SR1, SR4, SR6, triggering gate other diodes cut-off in matrix, and control shutdown bidirectional thyristor SR2, SR3, SR5 make
TB1, TB2 carry out positive compensation;Input voltage is voltage class 2, i.e. Y22 when being effectively high level, in triggering gating matrix
Diode D21, D22, D23 conducting, triggering driving line VK1, VK3, VK6 be high level control respectively triode VS1, VS3,
VS6 conducting makes P51, P53, P56 effectively go to open bidirectional thyristor SR1, SR3, SR6, other two poles in triggering gating matrix
Pipe cut-off, control shutdown bidirectional thyristor SR2, SR4, SR5, only makes TB2 carry out positive compensation;Input voltage be voltage class 4,
That is when Y24 is effectively high level, diode D41, D42, D43 in triggering gating matrix are connected, triggering driving line VK1,
VK3, VK5 control triode VS1, VS3, VS5 conducting for high level respectively makes P51, P53, P55 effectively go to open bidirectional thyristor
SR1, SR3, SR5, triggering gate other diodes cut-off in matrix, and control shutdown bidirectional thyristor SR2, SR4, SR6 are realized
0 voltage compensation, i.e. TB1, TB2 are without compensation;Input voltage is voltage class 5, i.e. Y25 when being effectively high level, triggering
Diode D51, D52, D53 conducting in matrix are gated, triggering driving line VK2, VK3, VK6 are that high level controls three poles respectively
Pipe VS2, VS3, VS6 conducting make P52, P53, P56 effectively go to open bidirectional thyristor SR2, SR3, SR6, and triggering gates in matrix
Other diodes cut-off, control shutdown bidirectional thyristor SR1, SR4, SR5, only make TB1 carry out Contrary compensation;Input voltage is
When voltage class 7, i.e. Y27 are effectively high level, diode D71, D72, D73 in triggering gating matrix are connected, triggering driving
Line VK2, VK3, VK5 be high level control respectively triode VS2, VS3, VS5 conducting make P52, P53, P55 effectively go to open it is double
To thyristor SR2, SR3, SR5, other diodes in triggering gating matrix end, control shutdown bidirectional thyristor SR1, SR4,
SR6, TB1, TB2 carry out Contrary compensation;Etc..
Table 1
Figure 14 is the embodiment 2 for triggering gating control cells, is equally mended for the compensation main circuit embodiment 1 of Fig. 2
Repay control;TB1 offset voltage is low in Fig. 2, and TB2 offset voltage is high, and the offset voltage of TB2 is 2 times of TB1 offset voltage;Exchange
Mains fluctuations range is 220V ± 10%, it is desirable that is stablized and is exported in the range of 220V ± 2%.In Figure 14, triggering
The triggering gating controlling value Y21-Y27 low level of gating control cells input is effective, 21 diode D11-D73, triggering gating
Alignment Y21-Y27, triggering driving line P51-P56 composition diode triggered gating matrix are controlled, it is direct by triggering gating matrix
Export the effective Trig control signal P51-P56 of low level.There is no the driving of Trig control signal P51-P56 in the present embodiment 2
Circuit.
The function connects that diode triggered gating matrix in Figure 14 is required according to table 1, are gated controlling value Y21- by triggering
The control of Y27;For example, input voltage is minimum voltage class 1, i.e. Y21 when being effectively low level, in triggering gating matrix
Diode D11, D12, D13 conducting, make respectively P51, P54, P56 become effective low level go to open bidirectional thyristor SR1,
SR4, SR6, triggering gating matrix in other diodes cut-off, control shutdown bidirectional thyristor SR2, SR3, SR5, make TB1,
TB2 carries out positive compensation;Input voltage is voltage class 2, i.e. Y22 when being effectively low level, two in triggering gating matrix
Pole pipe D21, D22, D23 conducting, make respectively P51, P53, P56 become effective low level go to open bidirectional thyristor SR1, SR3,
SR6, triggering gate other diodes cut-off in matrix, and control shutdown bidirectional thyristor SR2, SR4, SR5 only carry out TB2
Forward direction compensation;Input voltage is voltage class 4, i.e. Y24 when being effectively low level, diode D41 in triggering gating matrix,
D42, D43 conducting, make P51, P53, P55 become effective low level respectively and go to open bidirectional thyristor SR1, SR3, SR5, trigger
Other diodes cut-off in matrix is gated, controls and turns off bidirectional thyristor SR2, SR4, SR6,0 voltage compensation of realization, i.e. TB1,
TB2 is without compensation;Input voltage is voltage class 5, i.e. Y25 when being effectively low level, two poles in triggering gating matrix
Pipe D51, D52, D53 conducting, make respectively P52, P53, P56 become effective low level go to open bidirectional thyristor SR2, SR3,
SR6, triggering gate other diodes cut-off in matrix, and control shutdown bidirectional thyristor SR1, SR4, SR5 only carry out TB1
Contrary compensation;Input voltage is voltage class 7, i.e. Y27 when being effectively low level, diode D71 in triggering gating matrix,
D72, D73 conducting, make P52, P53, P55 become effective low level respectively and go to open bidirectional thyristor SR2, SR3, SR5, trigger
Other diodes cut-off in matrix is gated, control shutdown bidirectional thyristor SR1, SR4, SR6, TB1, TB2 are reversely mended
It repays;Etc..
In Figure 14, the low level in triggering gating controlling value Y21-Y27 needs to directly drive three altemating trigger optocouplers
Input terminal lumination of light emitting diode;Whens altemating trigger optocoupler selects MOC3022, MOC3052 etc., the driving current of 30mA is needed;
Whens altemating trigger optocoupler selects MOC3023, MOC3053 etc., the driving current of 15mA is needed.
Figure 15 is the embodiment 3 for triggering gating control cells, compensates control for the compensation main circuit embodiment 2 of Fig. 3
System;TB1 offset voltage is minimum in Fig. 3, TB3 offset voltage highest;And the offset voltage of TB2 is 2 times of TB1 offset voltage, TB3
Offset voltage be 2 times of TB2 offset voltage.AC supply voltage fluctuation range is 220V+10% to 220V-20%, it is desirable that
Stablized and is exported in the range of 220V ± 2%.In Figure 15, the triggering of triggering gating control cells input gates controlling value
Y21-Y210 high level is effective, 40 diode D01-D94, triggering gating control alignment Y21-Y210, triggering driving line
VK1-VK8 forms diode triggered and gates matrix, and resistance RS1-RS8, triode VS1-VS8 form Trig control signal P51-
The driving circuit of P58 forms Trig control signal P5 by P51-P58 at this time.
Table 2 is the triggering gating control function table for triggering gating control cells embodiment 3, lists 10 triggering gatings
10 significance bits in controlling value, i.e., 10 effective triggerings gate bidirectional thyristor in thyristor bridge corresponding to controlling values
On-off assembled state.10 effective triggering gating controlling values are corresponding with voltage class 1-10, trigger gating control cells foundation
The on off operating mode that triggering gating controlling value controls bidirectional thyristor in compensation main circuit embodiment 2 carries out corresponding voltage benefit
It repays;In table 2,1 represents corresponding bidirectional thyristor need to be in the conductive state, and 0, which represents corresponding bidirectional thyristor, to be off
State.The function connects that diode triggered gating matrix in Figure 15 is required according to table 2, are gated controlling value Y21-Y210 by triggering
Control;For example, input voltage is voltage class 7, i.e. Y27 when being effectively high level, the diode in triggering gating matrix
D71, D72, D73, D74 conducting, triggering driving line VK1, VK3, VK5, VK7 be high level control respectively triode VS1, VS3,
VS5, VS7 conducting make P51, P53, P55, P57 effectively go to open bidirectional thyristor SR1, SR3, SR5, SR7, triggering gating matrix
In the cut-off of other diodes, turn off bidirectional thyristor SR2, SR4, SR6, SR8, realize 0 voltage compensation, i.e. TB1, TB2, TB3
Without compensation;Input voltage is voltage class 8, i.e. Y28 when being effectively high level, the diode in triggering gating matrix
D81, D82, D83, D84 conducting, triggering driving line VK2, VK3, VK6, VK8 be high level control respectively triode VS2, VS3,
VS6, VS8 conducting make P52, P53, P56, P58 effectively go to open bidirectional thyristor SR2, SR3, SR6, SR8, triggering gating matrix
In other diodes cut-off, turn off bidirectional thyristor SR1, SR4, SR5, SR7, make TB1 carry out Contrary compensation;Input voltage is
When voltage class 9, i.e. Y29 are effectively high level, diode D91, D92, D93, D94 in triggering gating matrix are connected, triggering
Driving line VK2, VK4, VK5, VK8 be high level control respectively triode VS2, VS4, VS5, VS8 conducting make P52, P54,
P55, P58 effectively go to open bidirectional thyristor SR2, SR4, SR5, SR8, other diodes cut-off in triggering gating matrix is closed
Disconnected bidirectional thyristor SR1, SR3, SR6, SR7, make TB2 carry out Contrary compensation;Input voltage is that voltage class 10, i.e. Y210 is effective
When for high level, diode D01, D02, D03, D04 conducting in triggering gating matrix, triggering driving line VK2, VK3, VK5,
VK8 controls triode VS2, VS3, VS5, VS8 conducting for high level respectively makes P52, P53, P55, P58 effectively go to open two-way crystalline substance
Brake tube SR2, SR3, SR5, SR8, triggering gating matrix in other diodes cut-off, shutdown bidirectional thyristor SR1, SR4, SR6,
SR7 makes TB1, TB2 while carrying out Contrary compensation.
Table 2
For another example input voltage is voltage class 6, i.e. Y26 when being effectively high level, the diode in triggering gating matrix
D61, D62, D63, D64 conducting, triggering driving line VK1, VK4, VK5, VK7 be high level control respectively triode VS1, VS4,
VS5, VS7 conducting make P51, P54, P55, P57 effectively go to open bidirectional thyristor SR1, SR4, SR5, SR7, triggering gating matrix
In the cut-off of other diodes, turn off bidirectional thyristor SR2, SR3, SR6, SR8, TB1 made to carry out positive compensation;Input voltage is
When voltage class 4, i.e. Y24 are effectively high level, diode D41, D42, D43, D44 in triggering gating matrix are connected, triggering
Driving line VK1, VK4, VK6, VK7 be high level control respectively triode VS1, VS4, VS6, VS7 conducting make P51, P54,
P56, P57 effectively go to open bidirectional thyristor SR1, SR4, SR6, SR7, other diodes cut-off in triggering gating matrix is closed
Disconnected bidirectional thyristor SR2, SR3, SR5, SR8, make TB1, TB2 while carrying out positive compensation;Input voltage is voltage class 3, i.e.
When Y23 is effectively high level, diode D31, D32, D33, D34 in triggering gating matrix are connected, triggering driving line VK1,
VK3, VK5, VK8 control triode VS1, VS3, VS5, VS8 conducting for high level respectively goes out P51, P53, P55, P58 effectively
Pass two-way thyristor SR1, SR3, SR5, SR8, triggering gate other diodes in matrix and end, shutdown bidirectional thyristor SR2,
SR4, SR6, SR7 make TB3 carry out positive compensation;Input voltage is voltage class 1, i.e. Y21 when being effectively high level, triggering choosing
Diode D11, D12, D13, D14 conducting in logical matrix, triggering driving line VK1, VK3, VK6, VK8 are that high level is controlled respectively
Triode VS1, VS3, VS6, VS8 processed conducting make P51, P53, P56, P58 effectively go to open bidirectional thyristor SR1, SR3, SR6,
SR8, triggering gate other diodes cut-off in matrix, turn off bidirectional thyristor SR2, SR4, SR5, SR7, keep TB2, TB3 same
The compensation of Shi Jinhang forward direction;Etc..
When the triggering gating controlling value Y21-Y210 low level in table 2 is effective, it can equally trigger and gate according to Figure 14
The method of control unit embodiment 2, by 40 diode D01-D94, triggering gating control alignment Y21-Y210, triggering control row
Line P51-P58 composition triggering gating matrix, directly exports the effective Trig control signal P51- of low level by triggering gating matrix
P58.At this point, the low level in triggering gating controlling value Y21-Y210 needs to directly drive the input terminal of four altemating trigger optocouplers
Lumination of light emitting diode;Whens altemating trigger optocoupler selects MOC3022, MOC3052 etc., the driving current of 40mA is needed;Exchange touching
Whens the coupling that shines selects MOC3023, MOC3053 etc., the driving current of 20mA is needed.
Figure 16 is error detection judgement unit embodiment, gates controlling value P3, i.e. effective 10 triggerings of high level for triggering
Gating controlling value Y21-Y210 is differentiated that the triggering of output gating controlling value differentiates that signal P7 high level is effective, low level without
Effect;I.e. output P7 is 1, indicates that triggering gating controlling value is effective;Exporting P7 is 0, indicates that triggering gating controlling value is invalid.Figure 16
In, FD3 is the ROM memory with the input of 10 bit address and the output of 1 data, 10 controlling value Y21-Y210 points of triggering gatings
It is not connected to 10 bit address input A0-A9, triggering gating controlling value differentiates that signal P7 is exported from data output end D0.Table 3 is inspection
The memory cell content tables of data of ROM memory in the logic true value table and Figure 16 of wrong judgement unit.
Table 3
The function of error detection judgement unit be when having in the position M for judging triggering gating controlling value and when only one effective,
Enable output triggering gating controlling value differentiate signal P7 it is effective, otherwise enable output triggering gate controlling value differentiate signal P7 without
Effect;I.e. triggering gating controlling value the position M in only have one it is effective when, or do not have one it is effective when, enable the triggering of output
It gates controlling value and differentiates that signal P7 is invalid.The content of ROM memory storage unit is written according to the data of table 3 in Figure 16, table 3
In, 10 triggering gating equal high level of controlling value Y21-Y210 are effective, and low level is invalid;The triggering gating controlling value of output differentiates
Signal P7 high level is effective, and low level is invalid;Have in input signal Y 21-Y210 and when only 1 is 1, output P7 is 1;Y21-
When Y210 is other inputs, output P7 is 0.
If 10 triggerings gating equal low level of controlling value Y21-Y210 of input is effective, high level is invalid, then will be in table 3
All 0 change 1,1 becomes 0 to the preceding 10 row address content of input.Triggering gating controlling value if necessary to output differentiates signal P7
Low level is effective, and high level is invalid, then by the content of 1 column data last in table 3, all 0 change 1,1 becomes 0.
When error detection judgement unit needs to be differentiated for other digits triggering gating controlling value P3, can equally it use
ROM memory carries out.The triggering gating controlling value P3 that table 4 inputs has 7, and equal high level is effective, and low level is invalid;The touching of output
Hair gating controlling value differentiates that signal P7 high level is effective, and low level is invalid.It is exported using having 7 bit address to input with 1 data
ROM memory, 10 triggerings gating controlling value Y21-Y27 are respectively connected to 7 bit address input A0-A6, triggering gating control
Value differentiates that signal P7 is exported from data output end D0;The content of ROM memory storage unit is written according to the content of table 4.
Table 4
The logic function of error detection judgement unit can also be realized in other ways, for example, table 3, table 4 are logic true value
Table, can with or NOT logic door to combine realize the function.ROM memory in error detection judgement unit, or adopt
When realizing function with logic gate, it is all made of single supply+VCC1 power supply.
Figure 17 is protection drive unit embodiment, if the triggering gating controlling value of input differentiates that signal P7 high level is effective,
That is P7 is that 1 expression triggering gating controlling value is effective;P7 low level is invalid, i.e. P7 is that 0 expression triggering gating controlling value is invalid.If defeated
The not trigger region control signal P4 low level entered is effective, i.e., when P4 is equal to 0, shows that AC supply voltage has fluctuation, make to touch
Hair gating controlling value produces variation, needs to carry out the switching of bidirectional thyristor on off operating mode in thyristor bridge, changes compensation side
Formula;In handoff procedure, when to avoid upper and lower bridge arm switching in thyristor bridge, because the factor that bidirectional thyristor is delayed to turn off is made
At power supply short circuit, when not trigger region controls the signal valid period, i.e. the P4 of embodiment is equal to 0, own in cutoff thyristor bridge
Bidirectional thyristor.
In Figure 17, triode VT, relay coil KA, freewheeling diode VD, resistance RK1 composition protection control circuit, three
Pole pipe VK1, triode VK2, resistance RK2, resistance RK3 and door FY21 form trigger unit controlled source control circuit, with door
FY21 is powered using single supply+VCC1.+ VCC2 is controlled source+VCCK in the power supply and trigger unit of relay coil
Source current.When the triggering gating controlling value of input differentiates that signal P7 is low level, i.e., when triggering gating controlling value is invalid, with door
FY21 exports low level, triode VK1, VK2 cut-off, and controlled source+VCCK power loss, trigger unit does not have power supply, not work
Make, i.e., does not issue the trigger pulse of triggering bidirectional thyristor;P7 is that low level controls triode VT cut-off, relay coil simultaneously
KA power loss disconnects relay normally open switch KA-1, KA-2, KA-3 in the compensation main circuit embodiment 1 of Fig. 2, or makes
Relay normally open switch KA-1, KA-2, KA-3, KA-4 in the compensation main circuit embodiment 2 of Fig. 3 are disconnected, and are realized to thyristor
The open-circuit-protection of bridge;Control is closed relay normally closed switch KA-5, KA-6 in the compensation main circuit embodiment 1 of Fig. 2, makes to apply
The voltage being added on TB1, TB2 magnet exciting coil is 0, or control keeps the relay in the compensation main circuit embodiment 2 of Fig. 3 normal
KA-5, KA-6, KA-7 closure are closed in make and break, make the voltage 0 being applied on TB1, TB2, TB3 magnet exciting coil.It is more single when sampling
Member, which breaks down, causes triggering gating controlling value invalid, or the AC supply voltage of input is lower than minimum voltage levels section
Range, when causing the triggering gating controlling value of output invalid, whether the not trigger region control signal P4 no matter inputted is effective, protection
Driving unit all cuts off the power supply of trigger unit, stops the trigger pulse for issuing all bidirectional thyristors, while controlling disconnected
All bridge arms of thyristor bridge are opened, realize the open-circuit-protection to thyristor bridge.When the triggering gating controlling value of input differentiates signal
P7 is high level, i.e., when triggering gating controlling value is effective, control triode VT conducting, relay coil KA obtains electric, compensates Fig. 2
Relay normally open switch KA-1, KA-2, KA-3 closure in formula main circuit embodiment 1, relay normally closed switch KA-5, KA-6 are disconnected
It opens, or is closed relay normally open switch KA-1, KA-2, KA-3, KA-4 in the compensation main circuit embodiment 2 of Fig. 3, after
Electric appliance normally closed switch KA-5, KA-6, KA-7 are disconnected, and thyristor bridge is in compensation work state.When triggering, gating controlling value is effective,
That is P7 is 1, and trigger region control signal is not effective, i.e. when P4 is equal to 0, exports low level with door FY21, triode VK1, VK2 are cut
Only, controlled source+VCCK power loss, trigger unit do not work, i.e., do not issue the trigger pulse of triggering bidirectional thyristor, turn off brilliant lock
All bidirectional thyristors in pipe bridge show that AC supply voltage has fluctuation at this time, and triggering gating controlling value is made to produce variation,
It needs to carry out the switching of electronic switch, changes compensation way.When triggering gating controlling value is effective, i.e. P7 is 1, and not trigger region control
When invalidating signal processed, i.e. P4 are equal to 1, high level is exported with door FY21, triode VK1, VK2 are both turned on, and controlled source+VCCK is obtained
Electricity, trigger unit work normally, by triggering gating control cells according to effective, corresponding with some voltage class section triggering
Gating controlling value selects corresponding Trig control signal effective, and trigger unit is made to issue trigger pulse, controls double in thyristor bridge
To the on off operating mode of thyristor, main circuit is in compensation work state corresponding with the voltage class section.
When the triggering gating controlling value of error detection judgement unit judgement input is invalid, protection driving unit issues protection control letter
Number to main circuit, when thyristor bridge being made to be in open-circuit-protection state, AC voltage regulator is not compensated input voltage, voltage-stablizer
The voltage of output is the AC supply voltage inputted.When thyristor bridge is in open-circuit-protection state, if error detection differentiates list
The triggering gating controlling value of member judgement input reverts to useful signal, then driving unit is protected to be automatically stopped the open circuit of thyristor bridge
Guard mode, thyristor bridge are in compensation work state again.
From above embodiment and its course of work it is found that when input gates controlling value for effective triggering, triggering gating
Control unit ensure that same full-bridge circuit upper and lower bridge arm bidirectional thyristor does not simultaneously turn on, that is, realize on same full-bridge circuit
The mutual lock control of lower bridge arm bidirectional thyristor;And trigger gating controlling value it is invalid when, protection driving unit is single in rapid cutting triggering
The power supply of member on the basis of avoiding the conducting of bidirectional thyristor mistake from causing short circuit, simultaneously switches off all bridges of thyristor bridge
Arm makes thyristor bridge be in open-circuit-protection state.When thyristor bridge is in open-circuit-protection state, if error detection judgement unit is sentenced
Disconnected AC voltage regulator reenters normal logic control state, i.e. the triggering of error detection judgement unit judgement input gates controlling value
When reverting to useful signal, then protects driving unit that can be automatically stopped the open-circuit-protection state of thyristor bridge and locate it again
In compensation work state.Above-mentioned function effectively strengthens the protection that AC voltage regulator is directed to course of work exception, makes institute
The course of work for stating AC voltage-stabilizing control method is relatively reliable.
Except for the technical features described in the specification, the other technologies of AC voltage-stabilizing control method are those skilled in the art
The routine techniques grasped.